WO2001006554A1 - Verfahren zur herstellung von silizierten polysiliziumkontakten in integrierten halbleiterstrukturen - Google Patents
Verfahren zur herstellung von silizierten polysiliziumkontakten in integrierten halbleiterstrukturen Download PDFInfo
- Publication number
- WO2001006554A1 WO2001006554A1 PCT/DE2000/002098 DE0002098W WO0106554A1 WO 2001006554 A1 WO2001006554 A1 WO 2001006554A1 DE 0002098 W DE0002098 W DE 0002098W WO 0106554 A1 WO0106554 A1 WO 0106554A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- dielectric
- polysilicon
- polysilicon layer
- transistor
- Prior art date
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 84
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 84
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 56
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 31
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 30
- 238000005475 siliconizing Methods 0.000 claims abstract description 5
- 239000004020 conductor Substances 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910000040 hydrogen fluoride Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- 229910021339 platinum silicide Inorganic materials 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 claims description 2
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 210000004072 lung Anatomy 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
- H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
Definitions
- the present invention relates to a method for the manufacture of siliconized ⁇ lung Polysiliziu contacts m integrated semiconductor structures, the use of the method of manufacturing a transistor and a transistor, which is obtainable by the inventive shaped procedures.
- Silicide layer provided. However, this creates the manufacturing problem of siliconizing only certain polysilicon structures, but not siliconizing others, for example those that are to be used for resistors.
- FIG. 1 shows a bipolar transistor known in the prior art in an integrated semiconductor.
- the actual, active transistor 1 here consists of three adjacent differently doped regions of semiconductors, the emitter region 2, the base region 3 and the collector region 4.
- the sequence the letters indicate the sequence of doping in the emitter, base and collector area.
- a transistor arranged in an integrated circuit also has further auxiliary structures surrounding it, which serve on the one hand to isolate the potentials and on the other hand to derive the currents from the active transistor region 1.
- the emitter region 2 is connected to an emitter conductor 6, for example made of aluminum, via an emitter contact 5, usually made of polysilicon.
- the base region 3 is connected to a base conductor track 8 via a base contact 7.
- the collector region 4 is connected to a collector conductor track 12 via a so-called 'buried layer' 9, which is located below the other structures, and an intermediate layer 10 and a collector contact 11.
- Different silicon oxide insulation layers 13 and spacer insulators 14 serve for the electrical separation of the various electrically conductive structures.
- the so-called base path resistance which is the resistance between the base 3 and the base conductor 8 is the decisive transistor parameter in addition to the transit frequency and the base collector capacitance in bipolar transistors, the important parameters of the transistor such as its maximum oscillation frequency, its yarn, its minimum noise figure , be- atterverzögerungs solicit ne G, etc., is determined.
- the base path resistance which is the resistance between the base 3 and the base conductor 8 is the decisive transistor parameter in addition to the transit frequency and the base collector capacitance in bipolar transistors, the important parameters of the transistor such as its maximum oscillation frequency, its yarn, its minimum noise figure , be- atterverzögerungs encouraged ne G, etc.
- the base resistance is composed essentially of three parts, which are referred to below as R B , ⁇ , R B , e and R B , ⁇ .
- the inner part R B ,! arises from the resistance of the base region in the active transistor 1 below the emitter region reichs 2.
- the external component R B , e describes the resistance of the polysilicon path 7, which forms the base contact.
- R B, ⁇ represents the base resistance, the struck by a low do ⁇ zone is formed under the self-aligned emitter-base isolation the Spacerisolator 14 at the active transistor. This area is m the literature generally characterized as Lmk which be ⁇ .
- the transistor is quenzscen for example, in micro-transistors or Hochstfre- instead of a Ba m siscard 7 an arrangement with two base contacts configured (not shown).
- the second base contact can be arranged, for example, between the emitter contact and the collector contact.
- the reduction in base resistance achieved in this way is paid for with increased space requirements, higher capacities, greater power consumption and lower transit frequency.
- the advantages of the low base resistance of a transistor with two base contacts and the small design of a transistor with one base contact can be combined if the polysilicon used for base contact is siliconized, ie provided with a silicide layer.
- the layer contact of the silicide which is significantly lower than that of polysilicon, means that the transistor side facing away from the base contact is also connected to the base contact via the silicide with a low resistance and thus results in a similar, lower base resistance as in the case of a transistor with two base contacts. advantage. In addition, the resistance inherent in the base contact is reduced.
- silicide layers in addition to the above bezele- nen function used as an additional wiring level ⁇ to. This enables the wiring layout and thus the circuit performance to be optimized.
- the siliconization step is introduced immediately after coating and stripping the polysilicon.
- this process has the serious disadvantage of not only the desired base terminal regions and, if appropriate zuslegi ⁇ Liche conductor tracks siliconizing, but all open zutage- lying polysilicon areas, including those in which siliconization is undesirable.
- the polysilicon layers that are used for the base contact and for the emitter and collector connection m integrated circuits are also used to implement ohmic working resistances in the circuits.
- silicide blocking A previously known method for blocking silicide is carried out with the aid of photolithography. With the help of a paint mask, the dielectric that surrounds the resistance and transistor areas is used in areas where no silicide formation occurs should be covered. The dielectric is opened, ie removed, in the areas to be siliconized by means of an etching and siliconization is then carried out. The introduction of this additional photolithographic step means a significant increase in process complexity compared to
- Silicide often does not appear to make sense despite the improvement in transistor performance.
- the present invention is therefore based on the object of providing a method in which a selective, ie. H. targeted siliconization of polysilicon structures is possible without significantly increased process complexity.
- This object is achieved according to the invention by the method for producing siliconized polysilicon contacts in integrated semiconductor structures according to independent claim 1, the transistor obtainable by this method in accordance with independent claim 14 and the use of the method for producing a transistor in an integrated circuit according to independent claim 15.
- the present invention is based on the basic principle of covering polysilicon structures even before they are structured with a dielectric which, in a subsequent step, prevents a previously applied dielectric from being etched away. Siliconization takes place in the following only at locations where the dielectric has been etched away. Accordingly, the present invention is directed to a Ver ⁇ drive for the manufacture of siliconized polysilicon regions in integrated semiconductor structures of a Halbleiterrohlmgs with at least one m a first polysilicon layer formed pattern and one of the first polysilicon layer superimposed layer of a first dielectric with the following steps:
- a semiconductor structure or structure is to be understood here to mean any connected area consisting of a uniform material within an integrated semiconductor circuit.
- a structure can accordingly or also be three-dimensional, but will always have a layered structure, such as that which results from the production of integrated semiconductors.
- a process-produced by a semiconductor ⁇ arrangement of structures is meant, that are still in the process of completion and are therefore not yet fully functional.
- this includes in particular those semiconductors in production in which a polysilicon layer and an overlying dielectric layer have been applied after the introduction of functional elements, the polysilicon layer having already been structured, ie having been formed in the corresponding semiconductor structures.
- a superimposed layer in the sense of the present invention is to be understood as a layer which has been applied to the semiconductor blank in time after another layer superimposed by this in the production process.
- predetermined structure or the structures in the layer of the second dielectric and the second polysilicon layer takes place simultaneously, that is to say that the predetermined structure is imaged both in the layer of the second dielectric and in the second polysilicon layer underneath.
- This predetermined structure or the predetermined structures can be one or more
- Functional elements of an integrated circuit depicting ⁇ len can be resistors, conductor tracks or emitter contacts of an integrated transistor.
- the predetermined structures do not necessarily have to take on a function within the integrated circuit. Rather, they can also or also additionally form a cover that comes to lie over predetermined regions of the first polysilicon layer. In this way it can be achieved that such covered areas in the first polysilicon layer are not siliconized, even if no functional element of the second polysilicon layer should accidentally lie above them.
- the formation of the at least one predetermined structure or the predetermined structures preferably has the following steps:
- a photoresist is understood to mean a conventional photoresist known in the prior art. Since the uncovered regions of the layer of the first dielectric must be removed selectively, the two layers of the dielectric must differ in the materials used in order to enable a selective removal of the layer of the first dielectric. Thus, the removal of the layer may preferably be made of the first dielectric by etching with a selective for the first dielectric Atzmit ⁇ tel.
- the layer of the first dielectric can, for example, contain silicon dioxide or consist of silicon dioxide. This can be etched off with the preferred etchant hydrogen fluoride.
- the layer of the second dielectric should be removable from an etchant not used by the etchant of the first layer of dielectric. Silicon nitride, for example, which cannot be removed with hydrogen fluoride, can be used for the layer of the second dielectric.
- the silicide layer which forms can consist of silicides typically used in semiconductor technology or at least contain them, such as, for example, the preferred titanium silicide, platinum silicide and / or cobalt silicide.
- the at least one exposed structure m of the first polysilicon layer is the base contact of an integrated transistor. In order to maintain some resistance in the base contact, it is preferred that not all of the surface of the base contact be siliconized.
- the invention is further directed to a transistor which can be obtained by the method according to the invention described above.
- the invention is also directed to the USAGE ⁇ extension of the above-cited method of manufacturing a transistor.
- a transistor is preferably a bipolar transistor.
- the method can also be applied to other techniques, for example to CMOS techniques.
- Figure 1 shows, as described above, a prior art transistor an integrated semiconductor
- FIG. 2 shows the steps of the inventive method
- FIG. 3 shows a transistor produced by the method according to the invention
- FIG. 4 shows the possibility of additional masking of certain areas in the first polysilicon layer
- FIG. 5 shows the measured gate delay time of CML-R oscillators as a function of the switching current in a transistor manufactured in accordance with the invention.
- FIG. 2 shows the progress of the method according to the invention in various stages.
- Figure 2a is only the upper one Region of a transistor region m an integrated semiconducting ⁇ ter shown, the collector of which are 'bu ⁇ ed layer' ⁇ so as areas of these elements or Darun are ⁇ ter level, not shown.
- the illustration thus begins with the insulation layer 20, to which the first polysilicon layer 21 has already been applied and this has been structured. For example, there is a base contact as in FIG. 1 and a further resistor 22 in the region of the semiconductor tube shown.
- the spacer insulators 14 have already been formed, as has the layer of the first dielectric 23.
- the second polysilicon layer 24 is deposited on this.
- a thin, additional layer of a second dielectric 25 is deposited, which consists of a different material than the layer of the first dielectric 23, which surrounds the transistors and resistors.
- silicon dioxide is the first dielectric in the usual process
- silicon nitride (Si314) for example, can be used as the second dielectric.
- the combined layer of the second polysilicon layer 24 and the layer of the second dielectric 25 is now structured with the mask with which the second polysilicon layer was otherwise etched, that is to say without subsequent intended siliconization. However, all areas of the second polysilicon layer 24 are now additionally covered with the second dielectric 25. With this method, no changes to already existing masks are necessary, so that it can be easily introduced into existing productions.
- a second resistor 26 m is also structured in this way.
- Darge ⁇ is then treated with an etchant such as m Figure, the layer of the first dielectric 23 m the preparation ⁇ chen selectively etched which are not covered by a layer of the second dielectric 25 (which can not be etched away by the etchant ).
- the etching places predetermined, uncovered regions of the first polysilicon layer 21
- the silicide can now ⁇ er exposed portions of the first polysilicon layer 21 follow it, so that Silzid Anlagenen 27 can form at the predetermined structures ⁇ .
- the structurers in the second polysilicon layer are not siliconized, since they are covered with the layer of the second dielectric and are protected by this.
- FIG. 3 shows a bipolar transistor manufactured according to the invention, which contains the first polysilicon layer 21 and the silicide layer 27 integrated. The transistor is there furthermore from a reconstructed layer of the first
- the base contact in particular in 7 m of selected areas is provided with a silicide layer 27. This lowers the base resistance and thus increases the performance of the transistor with regard to relevant transistor parameters such as oscillation frequency, gate delay times etc.
- the etching with which the first polysilicon layer 21 is exposed means that the second polysilicon layer 24 lies over a resistance region 33 of the first polysilicon layer 21, so that the latter is not opened by the etching and therefore also none in the subsequent siliconization step Silicide layer 27 obtained.
- the mask 30 does not cover the contact area 32 of the resistor, so that after exposure to the etching in these areas 32, 32 the first polysilicon layer 21 can be exposed so that it is siliconized in order to enable good contact.
- Functional elements produced by the method according to the invention for example transistors or resistors, are fully functional. No negative effects on a transistor characteristic due to the integration of a silicide layer were observed.
- FIG. 5 shows the measured gate delay time of CML-Rmgoszillatoren as an example for the transistor performance.
- the functionality of the circuit demonstrates that, in addition to the transistors, the integrated ohmic resistors are also functional and thus effectively protected against siliconization.
- the minimum delay time is 13.7 ps.
- the comparison results a minimum gate delay time of 14.8 ps.
- the transistors produced according to the invention thus switch faster.
- the method according to the invention enables the formation of selectively selected silicide layers on polysilicon structures of integrated semiconductors in a previously unknown simple manner. Compared to known methods for silicide selective structuring, it is considerably easier and less expensive to carry out. It enables simple and targeted influencing of the resistance of polysilicon structures integrated in semiconductors.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/030,358 US6642606B1 (en) | 1999-07-01 | 2000-06-28 | Method for producing siliconized polysilicon contacts in integrated semiconductor structures |
JP2001510910A JP2003519440A (ja) | 1999-07-01 | 2000-06-28 | 集積型半導体構造体におけるシリサイド化されたポリシリコンコンタクトの製造プロセス |
EP00952877A EP1192649A1 (de) | 1999-07-01 | 2000-06-28 | Verfahren zur herstellung von silizierten polysiliziumkontakten in integrierten halbleiterstrukturen |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19930420.3 | 1999-07-01 | ||
DE19930420 | 1999-07-01 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001006554A1 true WO2001006554A1 (de) | 2001-01-25 |
Family
ID=7913342
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2000/002098 WO2001006554A1 (de) | 1999-07-01 | 2000-06-28 | Verfahren zur herstellung von silizierten polysiliziumkontakten in integrierten halbleiterstrukturen |
Country Status (5)
Country | Link |
---|---|
US (1) | US6642606B1 (de) |
EP (1) | EP1192649A1 (de) |
JP (1) | JP2003519440A (de) |
KR (1) | KR100498855B1 (de) |
WO (1) | WO2001006554A1 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002089201A1 (en) * | 2001-04-25 | 2002-11-07 | Advanced Micro Devices, Inc. | Improved salicide block for silicon-on-insulator (soi) applications |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR200457711Y1 (ko) * | 2011-10-10 | 2012-01-02 | 최윤선 | 휴대 단말기 이어폰 접속구 보호구 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4740482A (en) * | 1985-11-13 | 1988-04-26 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing bipolar transistor |
US4873200A (en) * | 1987-04-20 | 1989-10-10 | Oki Electric Industry Co., Ltd. | Method of fabricating a bipolar transistor |
US5268590A (en) * | 1989-12-27 | 1993-12-07 | Motorola, Inc. | CMOS device and process |
JPH07321327A (ja) * | 1994-05-25 | 1995-12-08 | Nippondenso Co Ltd | 半導体装置及びその製造方法 |
EP0895280A2 (de) * | 1990-05-31 | 1999-02-03 | STMicroelectronics, Inc. | Verfahren zur Herstellung von verschiedenen Gebieten mit hohen und niedrigen Widerstandswerten in einer einzigen Polysiliziumschicht und dadurch hergestellte Struktur |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4812417A (en) * | 1986-07-30 | 1989-03-14 | Mitsubishi Denki Kabushiki Kaisha | Method of making self aligned external and active base regions in I.C. processing |
US5219768A (en) * | 1989-05-10 | 1993-06-15 | Oki Electric Industry Co., Ltd. | Method for fabricating a semiconductor device |
JP3469251B2 (ja) * | 1990-02-14 | 2003-11-25 | 株式会社東芝 | 半導体装置の製造方法 |
US5173437A (en) | 1991-08-01 | 1992-12-22 | Chartered Semiconductor Manufacturing Pte Ltd | Double polysilicon capacitor formation compatable with submicron processing |
US5500557A (en) | 1992-04-30 | 1996-03-19 | Sgs-Thomson Microelectronics, Inc. | Structure and method for fabricating integrated circuits |
US5397729A (en) | 1992-06-15 | 1995-03-14 | Asahi Kasei Microsystems Co., Ltd. | Method for fabrication of semiconductor device having polycrystalline silicon and metal silicides |
JP2705476B2 (ja) * | 1992-08-07 | 1998-01-28 | ヤマハ株式会社 | 半導体装置の製造方法 |
US5849629A (en) | 1995-10-31 | 1998-12-15 | International Business Machines Corporation | Method of forming a low stress polycide conductors on a semiconductor chip |
-
2000
- 2000-06-28 EP EP00952877A patent/EP1192649A1/de not_active Withdrawn
- 2000-06-28 KR KR10-2001-7016788A patent/KR100498855B1/ko not_active IP Right Cessation
- 2000-06-28 JP JP2001510910A patent/JP2003519440A/ja not_active Withdrawn
- 2000-06-28 WO PCT/DE2000/002098 patent/WO2001006554A1/de active IP Right Grant
- 2000-06-28 US US10/030,358 patent/US6642606B1/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4740482A (en) * | 1985-11-13 | 1988-04-26 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing bipolar transistor |
US4873200A (en) * | 1987-04-20 | 1989-10-10 | Oki Electric Industry Co., Ltd. | Method of fabricating a bipolar transistor |
US5268590A (en) * | 1989-12-27 | 1993-12-07 | Motorola, Inc. | CMOS device and process |
EP0895280A2 (de) * | 1990-05-31 | 1999-02-03 | STMicroelectronics, Inc. | Verfahren zur Herstellung von verschiedenen Gebieten mit hohen und niedrigen Widerstandswerten in einer einzigen Polysiliziumschicht und dadurch hergestellte Struktur |
JPH07321327A (ja) * | 1994-05-25 | 1995-12-08 | Nippondenso Co Ltd | 半導体装置及びその製造方法 |
Non-Patent Citations (2)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 1996, no. 04 30 April 1996 (1996-04-30) * |
See also references of EP1192649A1 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002089201A1 (en) * | 2001-04-25 | 2002-11-07 | Advanced Micro Devices, Inc. | Improved salicide block for silicon-on-insulator (soi) applications |
US6586311B2 (en) | 2001-04-25 | 2003-07-01 | Advanced Micro Devices, Inc. | Salicide block for silicon-on-insulator (SOI) applications |
Also Published As
Publication number | Publication date |
---|---|
JP2003519440A (ja) | 2003-06-17 |
EP1192649A1 (de) | 2002-04-03 |
KR100498855B1 (ko) | 2005-07-04 |
US6642606B1 (en) | 2003-11-04 |
KR20020021389A (ko) | 2002-03-20 |
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