WO2000065663A1 - Transistor a heterostructure a effet de champ - Google Patents

Transistor a heterostructure a effet de champ Download PDF

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Publication number
WO2000065663A1
WO2000065663A1 PCT/JP1999/002236 JP9902236W WO0065663A1 WO 2000065663 A1 WO2000065663 A1 WO 2000065663A1 JP 9902236 W JP9902236 W JP 9902236W WO 0065663 A1 WO0065663 A1 WO 0065663A1
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WIPO (PCT)
Prior art keywords
layer
gan layer
gan
hetero
source
Prior art date
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PCT/JP1999/002236
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English (en)
Japanese (ja)
Inventor
Masayuki Abe
Original Assignee
Kansai Research Institute
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Publication date
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Priority to PCT/JP1999/002236 priority Critical patent/WO2000065663A1/fr
Publication of WO2000065663A1 publication Critical patent/WO2000065663A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H01L29/7785—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with more than one donor layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the present invention relates to a field effect truck for large power control
  • Si semiconductor devices are generally used in inverters that convert DC power from solar cells or fuel cell power generation systems into AC power for home use.
  • Si semiconductor devices devices having structures such as IGBT (insulated gate bipolar transistor) and MOSFET (metal oxide semiconductor field effect transistor) are used.
  • the Si semiconductor device used as a switching element for high power control of the inverter circuit.
  • the ON resistance of the device must be reduced to reduce the conduction loss, and the switching characteristics of the device must be increased to reduce the switching loss. Is being scaled down.
  • the device will be used as a switching element for high power control, it is necessary to increase the efficiency of the device while maintaining the device withstand voltage. descend. As a result, the current technology for improving the efficiency of Si semiconductor devices is close to its theoretical limit, and it is difficult to significantly improve efficiency.
  • an object of the present invention is to provide a high-efficiency device that can be used as a switching element for high power control. Disclosure of the invention
  • the feature of the heterostructure field effect transistor according to the present invention for achieving the above object is as follows.
  • the signature structure is as follows.
  • the first characteristic configuration is that an A 1 GaN layer doped with impurities is provided above and below a high-purity GaN layer, and a hetero interface between the A 1 GaN layer and the GaN layer is formed in two steps.
  • the point is that at least one set of the formed hetero-stacked film is provided, and channels are respectively formed on the GaN layer side of the hetero interface between the source and the drain.
  • the conductive layer in which the channel serving as the current path is formed is the GaN layer, and the conductive layer is compared with the Si FET (field effect transistor) in which the conductive layer is Si. Since the breakdown electric field strength is as large as about 10 times (3 MV / cm), the channel length can be scaled down (shortened channel) while maintaining the required device withstand voltage. The switching speed can be increased, and a highly efficient device that can be used as a switching element for large power control can be obtained. Furthermore, since multiple channels are formed in parallel in the device depth direction (multi-channeling), the ON resistance is reduced in inverse proportion to the number of channels, and the conduction loss can be reduced without using the most advanced microfabrication technology. Reduction can be achieved. In particular, in the case of a high-power control device used in the inverter or the like described above, high-speed switching characteristics such as high-frequency transistors are not usually required, so that reduction in conduction loss mainly contributes to higher device efficiency.
  • FIG. 2 shows a relative comparison of various characteristics of G a N and S i.
  • the ON resistance is reduced to 40 times lower than that of the Si-based FET. Since the power loss and the power loss are also reduced, it is expected that the conversion efficiency of the inverter using the heterostructure field effect transistor having the first characteristic configuration will be greatly improved.
  • the A 1 GaN layer is n—A 1 GaN doped with an n-type impurity
  • electrons are supplied to the high-purity GaN layer having a smaller band gap, and
  • the electrons are concentrated near the hetero interface, and the hetero interface is confined to the electrons when viewed from the GaN layer side.
  • a so-called two-dimensional electron gas is formed, and an extremely high mobility channel is formed along the hetero interface.
  • the channel when used as a switching element, the channel depends on the gate potential. Enhancement-type FETs that form a channel are preferable. However, even in the case of a depletion-type FET, switching operation is possible because the channel disappears by changing the gate potential to the opposite polarity in the case of a shallow depletion-type FET. Therefore, the heterostructure field effect transistor having this characteristic configuration is not limited to any of the enhancement type and the breakdown type.
  • the heterostructure field effect transistor When the heterostructure field effect transistor is turned on, a plurality of channels are formed in parallel between the source and the drain, and when a voltage is applied between the source and the drain electrodes, electrons supplied from the lower potential side electrode are It moves in a distributed manner in each channel, and drain current flows.
  • some of the upper and lower channels formed in the GaN layer may overlap each other in the vertical direction to form a single channel. a Whether the channels in the N layer are formed separately from each other or partially overlap each other, they contribute to a reduction in ON resistance.
  • a second characteristic configuration is that, in addition to the first characteristic configuration, a second GaN layer to which impurities are added is provided on the uppermost layer side of the source and drain regions of the hetero-stacked film. The point is that a source electrode and a drain electrode are provided on the N layer, respectively, and a gate electrode is formed between the second GaN layers.
  • the impurity concentration of the second GaN layer can be increased, a good omic contact can be obtained when forming the source electrode and the drain electrode.
  • a good omic contact can be obtained when forming the source electrode and the drain electrode.
  • a third characteristic configuration is that a high-purity GaN layer is added to the lowermost layer side of the hetero laminated film.
  • a channel is similarly formed on the GaN layer side of the hetero interface between the high-purity GaN layer added to the bottom layer and the A 1 GaN layer thereon. Therefore, the number of channels is added by one, and the ON resistance can be reduced. Also, Sahuai When it is difficult to directly grow an A 1 GaN layer on a substrate or the like, the GaN layer functions as a buffer layer.
  • a fourth characteristic configuration is that a high-purity or impurity-added A1GaN layer is provided above and below the impurity-added GaN layer, and the heterogeneous layer between the A1GaN layer and the GaN layer is provided. The point is that at least one set of a hetero-stacked film having two levels of interfaces is formed, and channels are respectively formed on the GaN layer side of each of the hetero interfaces between the source and the drain.
  • This fourth characteristic configuration is different from the first characteristic configuration described above in that the impurity is added to the GaN layer in which the channel is formed and the impurity is not added to the A1 GaN layer.
  • a so-called MISFET structure is formed in which the A 1 GaN layer is regarded as an insulator.
  • the G a N layer which is a conductive layer
  • the ON resistance can be reduced in conjunction with the multi-channel technology. Since the mobility is reduced due to the addition of impurities to the conductive layer, the GaN layer, higher switching characteristics cannot be expected compared to the first characteristic configuration, but as described above, it is used for inverters and the like. In the case of high-power control devices, high-speed switching characteristics such as high-frequency transistors are not usually required, so reducing ON resistance is sufficient. The same effect can be obtained when some impurities are added to the A 1 GaN layer.
  • a fifth characteristic configuration is that at least one of the high-purity GaN layers is replaced with an InGaN layer.
  • FIG. 1 is a schematic diagram showing the structure of a heterostructure field effect transistor according to the present invention
  • FIG. 2 is a chart showing a relative comparison of various characteristics of G a N and S i,
  • FIG. 3 is a characteristic diagram schematically showing a relationship between the transconductors g m (3 Id / 3 V g) and the gate voltage V g.
  • FET heterostructure field effect transistor
  • the FET is formed by alternately stacking three layers of a high-purity GaN layer 2 and an impurity-doped A 1 GaN layer 3 on a substrate 1 such as sapphire, A high-impurity-concentration second GaN layer 4 is selectively formed in the source and drain regions on the surface of the A1 GaN layer 3a, and the source and drain regions on the second GaN layer 4 are respectively formed.
  • a source electrode 5 and a drain electrode 6 are formed, and a gate electrode 7 is formed in a gate region on the surface of the A1GaN layer 3a.
  • the A 1 G aN layer 3 is n—A 1 G a N obtained by modulating and doping a donor impurity such as Si with a carrier concentration of about 10 18 cm— 3.
  • the thicknesses of 3a and 3c are about 250A, and the thickness of the middle A1GN layer 3b is about 500A. Further, a region of about 30 A from the interface with the GaN layer 2 in the A 1 GaN layer 3 has high purity except for the lower interface of the lowermost A 1 GaN layer 3 c. Then, a doping contact layer for the GaN layer 2 is formed.
  • the GaN layer 2 is high-purity i-GaN, and each film thickness is about 500A.
  • the lowermost GaN layer 2c functions as a buffer layer for crystal-growing the lowermost A1 GaN layer 3c.
  • the second GaN layer 4 is an n + —GaN doped with a predetermined donor impurity at a carrier concentration of about 5 ⁇ 10 18 cm— 3 , and has a thickness of about 1,000 A. .
  • the uppermost G a N layer 2 a and the above A 1 G a N layer 3 a and the corresponding G a N layer 2 a The upper half of the A 1 G aN layer 3 b located on the lower side of the A 1 G a N layer 2 b and the middle layer G a N layer 2 b and the upper layer of the A 1 G
  • the lower half of the a-N layer 3b and the G aN layer 2c below the G aN layer 2b form another set of hetero-stacked films 8, each of which is a hetero-layered film.
  • a two-stage hetero interface is formed between the A 1 GaN layer 3 and the GaN layer 2.
  • the thickness of the A 1 GaN layer 3 per heterointerface is about 250 A.
  • the height of the energy barrier at the hetero interface based on the difference in band gap between the A 1 GaN layer 3 and the GaN layer 2 is appropriately set, and the ⁇ 3 1 ⁇ layer 23,
  • the crystal growth of the GaN layer 2, the crystal growth of the AIGN layer 3, and the crystal growth and impurity doping of the second GaN layer 4 are performed by existing compound semiconductor thin film forming techniques such as MOCVD and MBE. Will be
  • the other portions are removed by selective etching except for the source / drain regions.
  • the AuZN i is sputtered on the gate region on the surface of the A1GaN layer 3a exposed by the selective etching of the second GaN layer 4, whereby the gate electrode 7 is formed.
  • the second GaN layer 4 and the gate electrode 7 are formed on the uppermost surface of the A1 GaN layer 3a such that their ends are in contact with each other.
  • Au / Pt / Ti or Au / Pt / A1 / Ti is deposited on the source / drain regions on the surface of the second GaN layer 4, and the rabbit gas is heated at 650 ° C. Then, the source electrode 5 and the drain electrode 6 are formed.
  • the source, drain, and gate electrodes 5, 6, and 7 are arranged so that the gate electrode 7 is formed between the source electrode 5 and the drain electrode 6 in the active region of the FET.
  • each is patterned into a predetermined planar shape such as a comb shape.
  • the width (gate length) of the gate electrode 7 is 2 / zm
  • the space between the gate electrode 7 and the source electrode 5 is 5 / Xm
  • the space between the electrodes 6 is ⁇ ⁇ ⁇ ⁇ .
  • the channel 9 is formed near the hetero interface of each of the GaN layers 2 a and 2 b in the F ⁇ thus manufactured.
  • the channel Since such a hetero interface is formed in a total of four steps in the top and middle GaN layers 2a and 2b, four channels 9 are formed in parallel between the source and drain, and only one channel is formed. ON resistance is reduced to one-fourth that of ordinary FETs.
  • a bias voltage of about 50 V to the gate electrode 7 each channel is sequentially formed from the upper channel, and the source and the drain conduct.
  • high-power control FETs can apply a high voltage as a gate bias, so that multiple channels can be turned off in the depth direction.
  • FIG. 1 shows a state in which channels 9a are formed below the gate electrode 7, respectively.
  • the channel 9b is always formed immediately below the source / drain region. For this reason, the parasitic parasitic source resistance and the parasitic drain resistance in the lateral direction of each channel 9 along the hetero interface in the source / drain region are sufficiently reduced, and, as described above, the second GaN layer 4 and the gate electrode 7 is formed on the surface of the uppermost A 1 G a N layer 3 a in a state where the ends are in contact with each other, so that the channel 9 b which is always on and the channel formed on the gate electrode 7 are formed. 9a is continuous in the horizontal direction, contributing to a reduction in ON resistance.
  • the source and drain regions are alloyed at a depth where the bottom channel is formed.
  • the parasitic resistance in the lateral direction is low as described above even when the alloy region is not formed sufficiently deep.
  • the vertical current between the electrode 6 and each channel is secured by the tunnel current, and the thickness of the GaN layer 2 and the A 1 GaN layer 3 is smaller than the area of the source / drain region.
  • the parasitic resistance component in the vertical direction is also sufficiently lower than the ON resistance of the channel in the gate region, so that even if alloying is insufficient, it is possible to suppress the source-drain parasitic resistance. it can.
  • the FET changes from an enhancement type to a depletion type.
  • the number of channels is 4 is illustrated, but the number of channels is set to 2 or 6, or by adjusting the number of layers of the GaN layer 2 and the A1 GaN layer 3. It can be 8 or more.
  • the lower interface of the lowermost layer A 1 GaN layer 3 c is made to have a high purity in the middle layer of about 30 A from the interface with the GaN layer 2 c, and the lowermost layer GaN layer 2 c A channel may be formed in the vicinity of the interface between c and the A 1 GaN layer 3 c.
  • the thickness of the lowermost A 1 GaN layer 3 c is about 500 ⁇ . In this case, the number of channels is odd.
  • Fig. 3 shows the relationship between the transconductances g m OI d / 3 V g) and the gate voltage V g for this case.
  • each hetero laminated film 8 of FIG. 1 the G a N layer 2, in the first embodiment form status is been made in high purity layer, Kiyaria Donna one impurity of about 1 0 1 8 cm- 3 and concentration in de one Bing the n-G a N, wherein a 1 G a a N layer 3 as a high-purity layer or Kiyaria concentration of about 1 0 1 7 cm 3 or lower concentration layer, wherein each of G a N layer 2 a , 2b may be a heterostructure field effect transistor having a structure in which channels are formed near the heterointerface, respectively.
  • At least one of the GaN layers 2 in which the channel 9 is formed may be replaced with InGaN.
  • the A 1 GaN layer 3 or the second GaN layer 4 may contain a small amount of In.
  • the second GaN layer 4 may be an n + -A1 GaN having an A1 composition ratio X close to the high-concentration n + -GaN of X and 0.1.
  • the substrate 1 may be a substrate other than sapphire.
  • the heterostructure field effect transistor of the present invention can be used for a switching element for high power control.
  • a switching element such as an inverter that converts DC power from a solar cell or a fuel cell power generation system into AC power for home use.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

L'invention concerne un transistor à hétérostructure à effet de champ, utilisé comme élément de commutation pour permettre une gestion à haute puissance. Une couche AlGaN dopée (3) est placée de chaque coté d'une couche GaN (2) de haute pureté, formant ainsi deux hétérojonctions entre la couche AlGaN (3) et la couche GaN (2). De plus, au moins une hétérostructure (8) de ce type est prévue, et un canal (9) ménagé dans chaque hétérojonction de ladite couche GaN (2), entre la source et le drain. Des secondes couches GaN dopées (4) sont en outre de préférence formées sur la couche supérieure de la zone source/drain de ladite hétérostructure (8). Enfin, une électrode source (5) et une électrode drain (6) sont situées respectivement sur les secondes couches GaN (4), et une électrode de commande (7) disposée entre ces secondes couches GaN (4).
PCT/JP1999/002236 1999-04-26 1999-04-26 Transistor a heterostructure a effet de champ WO2000065663A1 (fr)

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1246256A2 (fr) * 2001-03-27 2002-10-02 Matsushita Electric Industrial Co., Ltd. Transistor à effet de champ en nitrure
WO2003012877A2 (fr) * 2001-07-20 2003-02-13 Erhard Kohn Composant electronique
EP1965434A2 (fr) 2007-02-27 2008-09-03 Fujitsu Ltd. Dispositif de semi-conducteur à composant et amplificateur Doherty utilisant un dispositif de semi-conducteur à composant
WO2010064362A1 (fr) * 2008-12-05 2010-06-10 パナソニック株式会社 Transistor à effet de champ
JP2013141036A (ja) * 2013-04-22 2013-07-18 Fujitsu Ltd 化合物半導体積層構造
JP2013191670A (ja) * 2012-03-13 2013-09-26 Stanley Electric Co Ltd 半導体発光素子及びその製造方法
WO2014095122A1 (fr) * 2012-12-19 2014-06-26 Robert Bosch Gmbh Commutateur à semi-conducteur à blocage bidirectionnel et étage de commutation de puissance correspondant dans un véhicule
WO2014136250A1 (fr) * 2013-03-08 2014-09-12 株式会社日立製作所 Diode à semi-conducteur au nitrure
KR20210088715A (ko) 2019-02-05 2021-07-14 미쓰비시덴키 가부시키가이샤 반도체 장치 및 반도체 장치의 제조 방법

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Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1246256A2 (fr) * 2001-03-27 2002-10-02 Matsushita Electric Industrial Co., Ltd. Transistor à effet de champ en nitrure
EP1246256A3 (fr) * 2001-03-27 2004-05-26 Matsushita Electric Industrial Co., Ltd. Transistor à effet de champ en nitrure
US6787820B2 (en) 2001-03-27 2004-09-07 Matsushita Electric Industrial Co., Ltd. Hetero-junction field effect transistor having an InGaAIN cap film
WO2003012877A2 (fr) * 2001-07-20 2003-02-13 Erhard Kohn Composant electronique
WO2003012877A3 (fr) * 2001-07-20 2003-09-18 Erhard Kohn Composant electronique
US7663162B2 (en) 2007-02-27 2010-02-16 Fujitsu Limited Compound semiconductor device and doherty amplifier using compound semiconductor device
JP2008211089A (ja) * 2007-02-27 2008-09-11 Fujitsu Ltd 化合物半導体装置及びそれを用いたドハティ増幅器
EP1965434A3 (fr) * 2007-02-27 2009-04-15 Fujitsu Ltd. Dispositif de semi-conducteur à composant et amplificateur Doherty utilisant un dispositif de semi-conducteur à composant
EP1965434A2 (fr) 2007-02-27 2008-09-03 Fujitsu Ltd. Dispositif de semi-conducteur à composant et amplificateur Doherty utilisant un dispositif de semi-conducteur à composant
KR100967779B1 (ko) * 2007-02-27 2010-07-05 후지쯔 가부시끼가이샤 화합물 반도체 장치 및 그것을 이용한 도허티 증폭기
US7777251B2 (en) 2007-02-27 2010-08-17 Fujitsu Limited Compound semiconductor device and doherty amplifier using compound semiconductor device
WO2010064362A1 (fr) * 2008-12-05 2010-06-10 パナソニック株式会社 Transistor à effet de champ
JP2013191670A (ja) * 2012-03-13 2013-09-26 Stanley Electric Co Ltd 半導体発光素子及びその製造方法
WO2014095122A1 (fr) * 2012-12-19 2014-06-26 Robert Bosch Gmbh Commutateur à semi-conducteur à blocage bidirectionnel et étage de commutation de puissance correspondant dans un véhicule
WO2014136250A1 (fr) * 2013-03-08 2014-09-12 株式会社日立製作所 Diode à semi-conducteur au nitrure
JP2013141036A (ja) * 2013-04-22 2013-07-18 Fujitsu Ltd 化合物半導体積層構造
KR20210088715A (ko) 2019-02-05 2021-07-14 미쓰비시덴키 가부시키가이샤 반도체 장치 및 반도체 장치의 제조 방법
DE112019006829T5 (de) 2019-02-05 2021-10-21 Mitsubishi Electric Corporation Halbleitervorrichtung und Verfahren zur Herstellung der Halbleitervorrichtung

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