WO2000048238A1 - Structure multicouche a contraintes internes controlees et procede de realisation d'une telle structure - Google Patents
Structure multicouche a contraintes internes controlees et procede de realisation d'une telle structure Download PDFInfo
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- WO2000048238A1 WO2000048238A1 PCT/FR2000/000308 FR0000308W WO0048238A1 WO 2000048238 A1 WO2000048238 A1 WO 2000048238A1 FR 0000308 W FR0000308 W FR 0000308W WO 0048238 A1 WO0048238 A1 WO 0048238A1
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- 238000000034 method Methods 0.000 title claims description 51
- 230000006978 adaptation Effects 0.000 claims description 105
- 229910052710 silicon Inorganic materials 0.000 claims description 66
- 239000010703 silicon Substances 0.000 claims description 66
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 65
- 239000000463 material Substances 0.000 claims description 35
- 238000002513 implantation Methods 0.000 claims description 32
- 238000010438 heat treatment Methods 0.000 claims description 31
- 239000012528 membrane Substances 0.000 claims description 25
- 238000000926 separation method Methods 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 238000011282 treatment Methods 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 9
- 238000000407 epitaxy Methods 0.000 claims description 9
- 230000010070 molecular adhesion Effects 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 7
- 239000002887 superconductor Substances 0.000 claims description 5
- 238000007740 vapor deposition Methods 0.000 claims description 5
- 239000010432 diamond Substances 0.000 claims description 4
- 238000005234 chemical deposition Methods 0.000 claims description 3
- 229910003460 diamond Inorganic materials 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 229910010293 ceramic material Inorganic materials 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims description 2
- 239000010453 quartz Substances 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 238000005507 spraying Methods 0.000 claims description 2
- 238000010301 surface-oxidation reaction Methods 0.000 claims description 2
- 239000011135 tin Substances 0.000 claims description 2
- 229910052718 tin Inorganic materials 0.000 claims description 2
- 229910001092 metal group alloy Inorganic materials 0.000 claims 1
- 238000005476 soldering Methods 0.000 claims 1
- 238000003466 welding Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 269
- 230000035882 stress Effects 0.000 description 110
- 239000010408 film Substances 0.000 description 52
- 208000010392 Bone Fractures Diseases 0.000 description 22
- 206010017076 Fracture Diseases 0.000 description 22
- 229910052814 silicon oxide Inorganic materials 0.000 description 18
- 229910052581 Si3N4 Inorganic materials 0.000 description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 16
- 239000002344 surface layer Substances 0.000 description 16
- 235000012431 wafers Nutrition 0.000 description 16
- 238000005530 etching Methods 0.000 description 12
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 9
- 229910052739 hydrogen Inorganic materials 0.000 description 8
- 239000001257 hydrogen Substances 0.000 description 8
- 238000007906 compression Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 7
- 238000004140 cleaning Methods 0.000 description 6
- 230000006835 compression Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000012546 transfer Methods 0.000 description 6
- 239000012212 insulator Substances 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000001816 cooling Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000000155 isotopic effect Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical compound [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000005299 abrasion Methods 0.000 description 1
- 230000002730 additional effect Effects 0.000 description 1
- 230000010062 adhesion mechanism Effects 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000004630 atomic force microscopy Methods 0.000 description 1
- 238000004581 coalescence Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000004320 controlled atmosphere Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 229910052805 deuterium Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000005984 hydrogenation reaction Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000011343 solid material Substances 0.000 description 1
- 239000003351 stiffener Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00642—Manufacture or treatment of devices or systems in or on a substrate for improving the physical properties of a device
- B81C1/0065—Mechanical properties
- B81C1/00666—Treatments for controlling internal stress or strain in MEMS structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0161—Controlling physical properties of the material
- B81C2201/0163—Controlling internal stress of deposited layers
- B81C2201/0167—Controlling internal stress of deposited layers by adding further layers of materials having complementary strains, i.e. compressive or tensile strain
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- Y10T428/12528—Semiconductor component
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/31504—Composite [nonstructural laminate]
- Y10T428/31678—Of metal
Definitions
- the present invention relates to a multilayer structure obtained by adhesion or adhesion, in particular molecular, characterized by controlled internal stresses, and to a process for producing such a structure.
- multilayer structure with controlled stresses means a structure comprising at least two layers, called main layers, having tension or compression constraints between them. These constraints are determined and controlled according to the destination of the structure.
- the invention finds applications in the fields of microelectronics, as a substrate or as a stiffener, but also in the fields of micromechanics for the manufacture of membrane sensors, for example.
- an SOI multilayer structure comprises a thick layer of silicon serving as a support, an insulating layer of silicon oxide and a surface layer of thin silicon, of which the thickness is between a few tens of nanometers to a few tens of micrometers.
- the manufacture of SOI structures generally involves contacting by molecular adhesion two silicon wafers, at least one of which is covered by a surface layer of silicon oxide.
- the platelets After contacting, the platelets generally undergo a heat treatment under a controlled atmosphere.
- the function of this heat treatment is to improve intimate contact and therefore the adhesion of platelets.
- the materials present are capable of imposing mutual constraints.
- the constraints are linked in particular to the differences in coefficient of thermal expansion, ⁇ l / 1 of the materials in contact.
- a film of Si0 2 on a silicon wafer when produced at certain temperatures, has the effect of inducing deformation of the wafer during its cooling.
- the relative deformation under the effect of heat, noted ⁇ l / 1, is of the order of 2.6.10 "6 / K for silicon, and of the order of 5.
- 10 " NK for SiO oxide produced by thermal oxidation of silicon.
- FIGS. 1 to 4 appended make it possible to illustrate the stresses generated in SOI structures produced by conventional methods by molecular adhesion.
- FIG. 1 shows a first main layer 10a, or support, in the form of a silicon wafer having on its surface a thin layer of thermal oxide 20a.
- the reference 10b designates a silicon wafer forming a second main layer, the parallel faces of which are planar.
- the main layers 10a and 10b initially have thicknesses of the same order of magnitude.
- Figure 2 shows the structure obtained by assembling the main layers 10a and 10b. These layers are connected by the oxide layer 20a.
- the assembly comprises, as mentioned above, the molecular bonding of the second main layer of silicon 10b on the surface layer of oxide 20a. This bonding is reinforced by a heat treatment. It is observed that the structure obtained after assembly exhibits almost no deformation. In fact, as soon as the thicknesses of the main silicon layers are of the same order of magnitude, the stresses generated by the oxide layer on each of the main layers tend to compensate for each other.
- the silicon surface film of an SOI type structure is generally a thin film whose thickness is adapted to the requirements for electrical insulation of components, for example. The rigidity of the structure is ensured by the thick silicon layer.
- Thinning can take place by one of the thinning techniques known in various BSOI processes.
- Figures 3 and 4 show structures obtained respectively by the thinning of the main layers 10b and 10a. These structures have an arrow and the surface of the thin silicon layer is convex in each case. It is noted that the thickness of the main layers but also the thickness of the buried silicon oxide layer, that is to say the oxide layer sandwiched between the main layer and the thin surface layer, make part of the parameters which govern the deflection of the structure finally obtained.
- values of arrows are obtained which can be greater than 50 ⁇ m when the thin surface silicon film 10a has a thickness of 25 ⁇ m and when the main layer of silicon has a thickness of the order of 500 ⁇ m.
- the thickness of the silicon surface film is increased to more than 50 ⁇ m, the deflection decreases to approximately 25 ⁇ m. This shows the importance of the thickness of the silicon film compared to that of the oxide film.
- One possible measure to reduce the deformations of the structure would consist in making a second oxide film on the free face, called the rear face, of the thick main layer of the structure. This measure would effectively reduce the deformation of the plates before they are brought into contact. In a number of applications, however, it is necessary to remove the rear oxide film. However, after thinning, if the oxide film is removed on the rear face, it is found that the deformation is restored and finally a deformation of the SOI structure is obtained, mainly related to the thickness of the oxide film. Reference can be made to this subject in document (1), the reference of which is specified at the end of the description.
- FIG. 5 one can try to reduce the effect of the stresses by bringing into contact two main layers of silicon 10a, 10b each equipped with an oxide film 20a, 20b on the surface, the films being of comparable thickness.
- a deformation appears for the structure during the thinning of one of the layers.
- the initial deflection of the two main layers increases the difficulty of bringing the surfaces of the surface oxide layers into contact. This can locally generate areas of poor contact and therefore recesses or defects in the final structure.
- the deformation phenomenon described above for a structure combining layers of silicon and silicon oxide exists for a large number of pairs of materials.
- the deformation generated can be variable depending on the materials brought into contact and in particular the type of stress, in tension or in compression which appears.
- FIG. 6 when a film of silicon nitride 30 is deposited on a silicon wafer 10, this deposit can generate, depending on its conditions of use and after cooling, stresses leading also to a deformation.
- the constraints between silicon nitride and silicon have origins intrinsic to materials but also thermal origins linked to differences in coefficients of thermal expansion.
- the coefficient of thermal expansion of a film of silicon nitride obtained by chemical vapor deposition (CVD) is of the order of 4.2 ⁇ 10 ⁇ 6 6 / K while this coefficient is 2, 6.10 "6 / K for silicon.
- CVD chemical vapor deposition
- Document (3) in particular shows that it is possible to compensate for the effects of constraints generated by a surface film of silicon oxide formed on the surface of a silicon wafer, by covering this surface film with a second film of silicon nitride. A substantially planar structure can be obtained.
- the thickness of the second film must be precisely controlled to finally obtain a structure with flat faces.
- the stresses generated between the layers are not simply linked to the materials brought into contact, as is the case for layers produced for example by consecutive deposits, but are also linked to the quality of the molecular adhesion between layers.
- An object of the present invention is to propose a method for producing a multilayer structure, comprising at least one adhesion step, and making it possible to precisely control the stresses appearing in the structure following the association of layers of different materials. .
- One aim is in particular to propose such a method making it possible to modify and adjust the stresses in order to obtain a final planar structure or having a predetermined deflection.
- One aim is to be able to transfer, using adhesion, at least one crystalline layer to obtain a structure whose stress is controlled.
- An aim is also to propose such a method making it possible to produce a structure free from contact defects at the interfaces between the layers of different materials.
- Another aim is to propose a process capable of taking into account treatments before or after the production of the structure and which is compatible with the requirements of an industrial implementation such as, for example, an implantation treatment in to obtain separation.
- the invention more specifically relates to a method for producing a multilayer structure comprising at least a first and a second layer called main layers, interconnected by a stack of at least two adaptation layers of constraints, and having a determined structural stress, in which: a) the first main layer is equipped with a first stress adaptation layer, and at least one second stress adaptation layer is fitted, l one of the second main layer and the first stress adaptation layer, b) an assembly of the first and second main layers is carried out by means of the stress adaptation layers (said assembly advantageously comprising an adhesive bonding between layers), the first and second adaptation layers being made of materials and with thicknesses such that at the end of the process, said determined structural stress is obtained in the structure.
- the first adaptation layer and the second adaptation layer are chosen (type of embodiment, nature, thickness) as if they are respectively on the first main layer and on the second main layer independently (that is i.e. before assembly), they cause deformations in opposite directions. These deformations are not necessarily of the same amplitude.
- At least one of the adaptation layers is surmounted by an intermediate layer to allow the desired multilayer structure to be obtained.
- the adhesion bonding can be a bonding of the molecular adhesion type.
- the invention can also use a bonding chosen from a solder, a weld, a bonding by means of an adhesive substance, an interdiffusion between layers or a combination of these different techniques. In these techniques, bonding takes place by means of a so-called bonding layer.
- This bonding layer is either between the adaptation layers or between one of the adaptation layers and the corresponding main layer.
- structural constraint is meant the constraint resulting from the constraints of each of the adaptation layers, the constraints of each of the main layers, and the constraints linked to the link interface.
- the structural constraint determines the convex or concave deflection, or the plane character of the surfaces of the structure obtained.
- the heat treatment possibly carried out after step b) not only improves the quality of the bonding but above all makes it possible, by adjusting the thermal budget used, to modify the contact constraints between the layers so as to adjust the balance. tension and compression constraints.
- the thermal budget used can be adjusted taking into account in particular the thermal budgets of treatments before or after step c). Thus, other heat treatments carried out on the structure are not detrimental to obtaining a given stress.
- the heat treatment budget is also adjusted according to other parameters governing the stresses in the layers. Among these parameters we can cite:
- the first stress adaptation layer can be formed on the first main layer and the second stress adaptation layer on the second layer main.
- bonding is carried out between the adaptation layers.
- one of the stress adaptation layers has a convex surface and the second adaptation layer has a concave surface.
- the surfaces to be assembled thus have, to a certain extent, a complementarity of shape which makes it possible to obtain a quality contact free from bonding defects such as recesses, or poorly bonded areas.
- the two stress adaptation layers can be formed on the first main layer and bonding can take place between the second main layer and the surface stress adaptation layer, integral with the first main layer.
- step b) before step b), it is possible to prepare the layers to be combined by colla ⁇ e mol pr.nl ai ⁇ - to adjust the surface condition of these layers and give them, for example, a hydrophilic character.
- the adjustment of the surface state can consist either of smoothing (chemical, mechanochemical or by heat treatment) or, on the contrary, in an operation tending to make the surface of at least one of the layers to be assembled rougher.
- the method may include a step of thinning one of the main layers after assembly.
- Obtaining a thin layer, in particular on a thin layer of silicon, over stress adaptation layers of which at least one is insulating, is advantageous for example for the subsequent production of integrated electronic circuits (for example SOI substrate).
- the thinning of one of the main layers can take place by a mechanical or mechanochemical abrasive treatment.
- Thinning can also take place by fracture.
- the method comprises at least one ion implantation of gaseous species in at least one of the main layers or of the adaptation layers to form therein a fracture zone, and the thinning step comprises a step of separation of said implanted layer according to the fracture zone, for example by a thermal and / or mechanical treatment.
- the stress of the structure will then be modified by the thinning step.
- l stress during the process can advantageously be used as an "intermediate" stress of determined structure, to participate in this thinning.
- the final structure obtained after thinning that is to say after separation of one of the layers, presents a new constraint of determined "final" structure.
- the structure according to the invention in certain variants, can contain a certain number of layers, some of which can be thinned, or even eliminated, their role being justified in certain cases only to adapt the intermediate stress which participates in the thinning.
- the adaptation of the intermediate constraint can be an objective in itself.
- the use of an intermediate constraint which participates in the separation makes it possible to reduce the dose of implanted species (hydrogen and / or rare gases), and / or the thermal budget and / or the work induced by the mechanical force or forces applied. for separation. For example, it makes it possible to obtain separation with a very low thermal budget on structures where the main layers have different coefficients of thermal expansion. Control of the intermediate stress makes it possible to considerably improve the process by modifying either the implantation conditions or the separation conditions.
- one of the techniques uses an implantation of gaseous species capable of creating a layer embrittled consisting of microcavities or gaseous microbubbles.
- microcavity or gaseous microbubble is understood to mean any cavity generated by the implantation of ions of hydrogen gas and / or of rare gases in the material.
- the cavities can be in very flattened form, that is to say of low height, for example a few inter-atomic distances as well as in spherical form or any other form different from these two previous forms.
- These cavities may contain a free gas phase and / or gas atoms from the implanted ions attached to atoms of the material forming the walls of the cavities; these cavities can even be empty.
- the cavities are generally called in Anglo-Saxon terminology “platelets”, “microblisters” or even “bubbles”.
- gaseous species elements for example of hydrogen or of rare gases in their atomic form (for example H) or in their molecular form (for example H 2 ) or in their ionic form (for example H + , H 2 + ) or in their isotopic (e.g. deuterium) or isotopic and ionic form.
- the fracture heat treatment is carried out with a thermal budget which depends on the thermal budget supplied to the main layer during the implantation, and during the stages which take place before the fracture. Depending on the case, this heat treatment can be zero in time and / or temperature. Of more, this heat treatment can be adjusted according to other stresses exerted, such as, for example, mechanical forces, traction, shear, bending, etc. exercised alone or in combination.
- the heat treatment leads to the coalescence of the microcavities which bring about a weakening of the structure at the level of the layer of microcavities.
- This embrittlement allows the separation of the material under the effect of internal stresses and / or pressure in the microcavities, this separation being able to be natural or assisted by application of external stresses.
- Mechanical forces can be applied perpendicular to the planes of the layers and / or parallel to them. They can be located in a point or a zone or be applied to different places in a symmetrical or asymmetrical way.
- the stage of adaptation of the constraints of the final structure can also include a stage of thinning, for example by sacrificial oxidation and / or chemical attack and / or plasma etching and / or polishing.
- At least one of the stress adaptation layers can be formed by deposition of material according to a deposition method chosen for example from spraying, epitaxy, chemical deposition methods, such as chemical vapor deposition, low pressure vapor phase deposition, and chemical phase deposition plasma assisted steam.
- a deposition method chosen for example from spraying, epitaxy, chemical deposition methods, such as chemical vapor deposition, low pressure vapor phase deposition, and chemical phase deposition plasma assisted steam.
- a stress adaptation layer can also be obtained by surface oxidation of one of the main layers.
- one of the adaptation layers can be a layer of thermal oxide Si0 2 .
- At least one stress adaptation layer can be obtained by implanting species in a main layer.
- the implantation of species in one of the main layers makes it possible to form on the surface of this layer an area whose properties are modified.
- the implantation of species makes it possible to generate constraints or to locally modify the density of the material.
- the depth where the majority of the implanted species is located depends on the conditions of the implantation. For example of its energy, if the implantation is of the ion implantation type.
- the film of implanted species, defined by this depth, and its vicinity, where most of the implanted species are located, then constitutes one of the layers of the constraint bilayer.
- the film between this film of implanted species and the surface of the second main layer can constitute one of the two films of the stress bilayer.
- the intensity of the constraints can be adapted according to the nature of the species, the dose or the various implantation parameters (temperature, implantation current, energy, etc.).
- the implantation can in particular be carried out with gaseous species, for example hydrogen and / or rare gases.
- the presence of a stress in the structure participates in the separation and makes it possible to reduce the dose of implanted species (hydrogen and / or rare gases), and / or the thermal budget and / or the work induced by the mechanical force (s) applied to separate it.
- implanted species hydrogen and / or rare gases
- thermal budget and / or the work induced by the mechanical force (s) applied to separate it.
- stress control makes it possible to considerably improve the process. It allows for example to have the fracture with a very low thermal budget on structures where the main layers have different coefficients of thermal expansion.
- the implantation can be carried out before or after assembly of the structure.
- the normally adjacent main layer may be omitted or confused with this adaptation layer.
- a modified main layer and a multilayer stack are obtained, the latter being able to be reused as the main layer comprising a stress adaptation layer.
- the production method described above is applicable to main layers of various materials.
- the main layers of identical or different materials can be for example in monocrystalline, polycrystalline or amorphous materials, and for example silicon, germanium, silicon carbide, type III-V or II-VI semiconductor, such as GaAs, GaN, InP, ... made of glass or quartz, superconductive materials, diamonds, or ceramic materials (such as LiTa0 3 , LiNb0 3 , ).
- the main layer can be formed of one or more layers, for example glued, deposited, or epitaxial.
- the stress adaptation layers are for example made of a material chosen from Si0 2 , SiN, Si 3 N 4 , TiN, diamond and metals (such as Pd, alloys, etc.) or one of the materials capable of constitute one of the main layers or in a combination of these materials.
- the invention also relates to a multilayer structure with controlled internal stresses comprising, in order, a stack of a first main layer, of at least a first stress adaptation layer in contact with the first main layer, of at least a second stress adaptation layer in contact with said first stress adaptation layer and a second main layer in contact with the second stress adaptation layer.
- the first and second stress adaptation layers have contact constraints with the first and second main layers which are of opposite sign respectively.
- the structure may have a suspended membrane, the suspended membrane comprising at least a portion of one of the first and second main layers, released from the second respectively of the first main layer.
- the suspended membrane can support other functional layers.
- it may further comprise at least one layer of superconductive material covering said portion of one of the first and second main layers.
- FIG. 1 is a schematic section of first and second main layers before assembly, one of the layers being covered with a surface film of a material capable of generating internal constraints.
- FIG. 2 already described, shows a structure comprising the layers of Figure 1, after assembly.
- FIGS 7, 8 and 9 are schematic sections showing steps in the manufacture of a multilayer structure according to a particular implementation of the method of the invention.
- FIG. 10 is a graph indicating, on an arbitrary scale, the deflection values of the structure obtained by the method, as a function of thermal treatment parameters.
- FIG. 11 to 15 are schematic sections showing successive steps of another possibility of implementing the method of one invention.
- FIG. 16 to 18 are schematic sections, showing successive stages in the production of a suspended membrane structure and illustrating a particular application of the invention.
- FIG. 19 is a schematic section of a structure constituting a variant of the structure of Figure 18.
- FIG. 20 is a diagrammatic section of a structure constituting another variant of the structure of FIG. 18.
- a first example of implementation relates to the production of a stacked structure consisting of a very thin silicon film and a bilayer for adaptation of stresses supported by a thick silicon substrate.
- the described implementation calls upon a separation process for forming the thin surface layer of silicon.
- a film of silicon nitride Si 3 N 4 130, with a thickness of 400 nm, is formed according to a low pressure vapor deposition (LPCVD) process, on a plate. of silicon which forms a first main layer 110a.
- LPCVD low pressure vapor deposition
- the low-pressure vapor deposition makes it possible to produce a film inducing a weak deflection on the main layer. This is the case in particular if the deposition is carried out on the two faces of this layer.
- the silicon nitride film 130 constitutes a first stress adaptation layer.
- this adaptation layer can be surmounted by an intermediate layer produced for example by a film of silicon oxide and by a film of silicon oxynitride, for example a few nm thick.
- This intermediate layer in this case allows either to promote bonding by molecular adhesion used for assembly or to improve the electrical quality of the interface with the main layer.
- the silicon wafer is optionally covered beforehand with a very thin layer of silicon oxide, not shown, for example with a thickness of 10 nm. The advantage of such a very thin layer is, for example to constitute an interface of very good electronic quality with a surface silicon layer described below.
- hydrogen is implanted through the film 130 with an implantation dose of the order of 2.5 ⁇ 10 16 at / cm 2 .
- the implantation leads to the formation of a fracture zone identified with the reference 112.
- the hydrogen implantation parameters can be changed when the deflection of the nitride film is changed, depending on the deposition conditions for example.
- a film 120 of silicon oxide is produced by a heat treatment under an oxidizing atmosphere.
- the thickness of the oxide film is substantially equivalent to that of the nitride film 130.
- the second silicon wafer 110b and the oxide film 120 respectively form a second main layer and a second stress adaptation layer.
- the layers of silicon nitride and the silicon oxide initially formed on the main layers of silicon generate contact stresses of opposite sign. This results in deformations of the main layers such that the surfaces of the nitride and oxide stress adaptation layers are respectively concave and convex.
- the process is continued by a step of cleaning the plates intended to make the surface of the stress adaptation layers 120, 130 hydrophilic.
- the cleaning makes it possible to obtain a controlled surface micro-roughness, of quadratic value (RMS in English). typically less than 0.7 nm, which is compatible with direct molecular adhesion.
- Micro-roughness can be measured and controlled by atomic force microscopy for example in a range of spatial frequencies from 10 "2 ⁇ m _1 to 10 3 ⁇ m -1 .
- the control of the surface roughness, by the step of cleaning the plates before bonding, is presented here as an advantage on surface polishing techniques, for a silicon nitride film, the thickness of which can reach at least several tenths of a micron.
- the cleaning step makes it possible to induce a modification of the binding energy and therefore to induce a modification of the specific stress of the bilayer subsequently formed by the bonding of the stress adaptation layers.
- the cleaning step makes it possible to free the process from a mechanical-chemical polishing step, good thickness homogeneity of the
- the next step in the process actually involves bringing the stress adaptation layers into direct contact to cause them to stick. This operation takes place at room temperature. It is understood from FIG. 7 that the complementary nature of the deformation of the layers makes it possible to minimize the risk of poor contact.
- a first heat treatment carried out for 30 minutes at a temperature of 500 ° C. makes it possible to cause a fracture in the fracture zone 112 indicated in FIG. 7 and therefore to detach from the first main layer 110a a thin surface layer 114
- This surface layer remains integral with the second main layer 110b via the bilayer formed by the stress adaptation layers 120, 130 associated possibly to intermediate layers.
- the heat treatment can be assisted in whole or in part by the application of mechanical stresses. As a result, the thermal budget required for the fracture can be reduced. It can be zero in time and in temperature.
- the thickness of the thin surface layer of silicon 114 is of the order of a few tenths of a micrometer. It is fixed by the penetration depth of the gaseous species of the separation layer (fracture) implanted in the first main layer of silicon. As the implantation takes place through the film 130 of silicon nitride, the depth of implantation and therefore the thickness of the thin layer 114 of silicon also depend on the thickness of the film 130 of silicon nitride.
- first main layer 110a is equipped with a stress adaptation layer makes it possible to reduce the implantation dose necessary for the fracture in the zone 112 and / or to reduce the thermal budget of the first thermal fracture treatment and / or the mechanical separation forces.
- the specific constraints induced by the stress adaptation layers and in particular the layer of silicon nitride 130, in the first main layer of silicon 110a indeed favor fracture. For example, a gain in temperature, energy and ultimately cost can be obtained.
- the minimum dose to obtain a separation is 3.5.10 16 at / cm 2 , for a conventional stacked structure where the nitride film would be replaced by a thermal oxide film 400 nm thick.
- a second heat treatment is carried out.
- This treatment has a double function of making more intimate the connections at the interface between the two layers of adaptation of stresses previously brought into contact, and of modifying or adjusting the stresses induced within the structure finally obtained.
- the second heat treatment takes into account, of course, the thermal budget of the first heat treatment and possibly the use of mechanical stresses.
- the second heat treatment can be carried out at a temperature of 1100 ° C. for 2 hours.
- a concavity of the structure is obtained with a deflection of approximately 50 ⁇ m.
- the deflection of the final stacked structure depends mainly on two parameters which are the ratio Re of the thicknesses E nit and E ox of the layers of nitride 120, and of silicon oxide 130, of stress adaptation and the thermal budget applied to the structure.
- the effect of the thickness ratio of the layers, at fixed sealing temperature, reflects the fact that the deflection of the structure is proportional to the effective stress and to the thickness of the adaptation layers.
- FIG. 10 is a graph which indicates in arbitrary units the deflection of the structure finally obtained as a function of the thickness ratio of the layers
- E oxidizes two different treatment temperatures Ti and T 2 such that T 2 > T ⁇ .
- the stress adaptation bilayer is consisting of a film of Si0 2 and a layer implanted in one of the main layers.
- a first stress adaptation layer 220 is formed by implantation of species in a silicon wafer. The part of this plate not affected by the implantation forms the first main layer 210a.
- the implantation can take place with nitrogen with a dose of 10 16 atoms / cm 2 and with an energy of 135 keV.
- the stress adaptation layer 220 that is to say the zone disturbed by the implantation, induces a compressive stress of a few tens of MPa.
- the deformations of the layers induced by the stresses are no longer shown in FIGS. 11 to 15.
- the energy, and therefore the implantation depth, makes it possible to define in the main layer 210a a thin surface layer 214 more or less thick. This is delimited by the separation layer 212.
- a film of silicon oxide (Si0 2 ) 230 is formed on the surface of another silicon wafer which constitutes the second main layer 210b.
- the silicon oxide film 230 forms a stress adaptation layer.
- the main layers, equipped with the stress adaptation layers are then cleaned so that the micro-roughness and the hydrophilic nature of the stress adaptation layers allow molecular adhesion as soon as these layers are brought into contact.
- the assembly of main layers, by bringing the stress adaptation layers into contact, is illustrated in FIG. 14.
- the contacting of the silicon oxide layer 230 and the implanted layer 220 also makes it possible to constitute a bilayer for adaptation of stresses.
- the normally adjacent main layer may be omitted or confused with this adaptation layer.
- a first heat treatment, called transfer treatment (which optionally also makes it possible to strengthen the adhesion between the stress adaptation layers) is carried out with a thermal budget sufficient to allow a fracture according to the fracture layer.
- This heat treatment can be applied, for example, continuously, variable or pulse.
- This heat transfer treatment can optionally be assisted by the application of mechanical forces, for example by traction and / or shear and / or bending.
- the thermal budget can be carried out at reduced temperature and time, or even zero.
- the divide separates the thin layer 214 and the first main layer 210a, as shown in FIG. 15.
- separation can be caused by heating the structure to 450 ° C for 30 minutes.
- treatment at a temperature of at least 500 ° C. would be necessary, for 30 minutes to obtain a separation .
- each of the stress adaptation layers of the bilayer is subjected to an effective stress, the result of which can be globally modified by the adhesion mechanisms of the two plates and by the various heat treatments applied.
- the final stacked structure is then subjected to an adaptable stress, in particular by the final heat treatment.
- the various heat treatments can advantageously be mechanically assisted (for example by traction, compression, shearing, bending or by application of electrostatic or magnetic fields depending on the nature of the layers) to induce an additional effect of stresses in the specific bilayer.
- an alternative embodiment not shown in the figures consists in not thinning one of the main layers by the layer transfer fracture.
- the other preparation steps being comparable to those described in the second example of implementation, the thinning of one of the main layers, if desired, can then be carried out by simple mechanical and / or chemical abrasion.
- components such as as membranes
- the advantage of such an approach is to be able to have the surface of the surface layer, for example, to carry out an epitaxy there without having to deposit stress adaptation layers of the membranes therein, during the preparation of those -this.
- the surface layer of silicon is that obtained by the process described beforehand, that is to say by implantation of hydrogen and separation, and the stress of the stacked structure, comprising the stress adaptation bilayer, obtained at the end of the process for developing this layer of silicon is therefore essential for the quality of the consecutive epitaxy (s) insofar as it makes it possible to have a prestressed support better suited to these epitaxies.
- main layers may themselves have a multilayer structure with a plurality of sublayers.
- this can be formed by a native, thermal or deposited oxide.
- FIGS. 16 to 20 illustrate in section, different stages and possibilities of making a structure with a suspended membrane.
- Figure 16 shows a multilayer structure comparable to that of Figure 15, at the end of the thinning or fracture of the first main layer.
- the structure of FIG. 16 comprises a thin layer 214 of silicon, coming from the first main layer, a pair of stress adaptation layers 220, 230 and a second main layer 210b, also made of silicon, which here constitutes a support substrate.
- the pair of constraint adaptation layer, or bilayer is designated in the following text by a single reference 225.
- the thin layer 214 is covered with an etching mask 240 having a pattern corresponding to the contours of a membrane which it is desired to produce in the structure. More specifically, the mask has openings which leave areas of the structure to be engraved to define the shape of the suspended membrane.
- the mask 240 is for example a photosensitive resin mask, shaped by exposure through an exposure mask, then by development.
- a first anisotropic etching through the openings of the mask 240 makes it possible to form trenches 242 which extend through the thin layer 214 and all or part of the stress adaptation bilayer 225.
- the etching can also be stopped on the second main layer.
- the etching stop can be facilitated by an etching stop layer, not shown, placed on the second main layer before the formation of the multilayer structure.
- the trenches delimit a central part 244 intended to subsequently form the suspended membrane. It should be noted, however, that the trenches do not completely surround the central part 244 but preserve "bridges" which connect it to the structure 245 surrounding the central part. These "bridges" which are not visible, because outside the section plane of the figures, may possibly constitute in the final structure of the beams for holding the suspended membrane thus allowing for example an electrical and / or thermal conduction.
- a next step, illustrated in FIG. 18, includes a selective anisotropic etching making it possible to eliminate at least part of the stress adaptation bilayer to release a portion of the thin layer, in this case the central part 244 which now constitutes a suspended membrane.
- the figure does. does not take into account a possible attack on the lateral flanks of the bilayer 225 in the trenches, during the anisotropic etching.
- FIG. 19 illustrates a variant in which the membrane is released by means of anisotropic etching which makes it possible to selectively attack the second main layer 210b, that is to say the support substrate.
- the membrane can also be released by a combined etching of the second main layer and the stress adaptation bilayer. Finally, at the end of the engravings, the layer of resin forming the mask 240 can be eliminated.
- FIG. 20 shows a particular embodiment, comparable to that of FIG. 18, in which additional layers were formed on the thin layer 214 before etching.
- the additional layers in the example comprise a layer 246 of germ and / or a buffer layer, and a layer 248 of superconductive material, for example of the YBaCuO type.
- the seed layer 246 and / or a buffer layer, not shown, make it possible to promote the growth of the superconductive material on the thin layer of silicon and / or make it possible to correct any possible mismatch of crystalline mesh between the silicon of the thin layer and the superconductor.
- These layers are etched as already described with reference to Figures 18 or 19 to obtain the final structure of Figure 20 with a suspended membrane 244.
- the location of the engraving mask 240, removed, is shown in broken lines.
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Abstract
Description
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Priority Applications (4)
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DE60041124T DE60041124D1 (de) | 1999-02-10 | 2000-02-09 | Ruktur mit kontrollierten eigenspannungen |
EP00903763A EP1155442B1 (fr) | 1999-02-10 | 2000-02-09 | Procede de realisation d'une structure multicouche a contraintes internes controlees |
JP2000599069A JP4889154B2 (ja) | 1999-02-10 | 2000-02-09 | 多層構造体の製造方法 |
US09/913,006 US6756285B1 (en) | 1999-02-10 | 2000-02-09 | Multilayer structure with controlled internal stresses and making same |
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FR9901558A FR2789518B1 (fr) | 1999-02-10 | 1999-02-10 | Structure multicouche a contraintes internes controlees et procede de realisation d'une telle structure |
FR99/01558 | 1999-02-10 |
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WO2000048238A1 true WO2000048238A1 (fr) | 2000-08-17 |
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PCT/FR2000/000308 WO2000048238A1 (fr) | 1999-02-10 | 2000-02-09 | Structure multicouche a contraintes internes controlees et procede de realisation d'une telle structure |
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US (1) | US6756285B1 (fr) |
EP (1) | EP1155442B1 (fr) |
JP (1) | JP4889154B2 (fr) |
KR (1) | KR100743557B1 (fr) |
DE (1) | DE60041124D1 (fr) |
FR (1) | FR2789518B1 (fr) |
WO (1) | WO2000048238A1 (fr) |
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US7883994B2 (en) | 1997-12-30 | 2011-02-08 | Commissariat A L'energie Atomique | Process for the transfer of a thin film |
US7902038B2 (en) | 2001-04-13 | 2011-03-08 | Commissariat A L'energie Atomique | Detachable substrate with controlled mechanical strength and method of producing same |
US7713369B2 (en) | 2001-04-13 | 2010-05-11 | Commissariat A L'energie Atomique | Detachable substrate or detachable structure and method for the production thereof |
US7045878B2 (en) | 2001-05-18 | 2006-05-16 | Reveo, Inc. | Selectively bonded thin film layer and substrate layer for processing of useful devices |
US7081657B2 (en) | 2001-05-18 | 2006-07-25 | Reveo, Inc. | MEMS and method of manufacturing MEMS |
US7145219B2 (en) | 2001-09-12 | 2006-12-05 | Reveo, Inc. | Vertical integrated circuits |
US7163826B2 (en) | 2001-09-12 | 2007-01-16 | Reveo, Inc | Method of fabricating multi layer devices on buried oxide layer substrates |
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US7588994B2 (en) * | 2002-06-07 | 2009-09-15 | Amberwave Systems Corporation | Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain |
US7176108B2 (en) | 2002-11-07 | 2007-02-13 | Soitec Silicon On Insulator | Method of detaching a thin film at moderate temperature after co-implantation |
US8389379B2 (en) | 2002-12-09 | 2013-03-05 | Commissariat A L'energie Atomique | Method for making a stressed structure designed to be dissociated |
WO2004064146A1 (fr) * | 2002-12-09 | 2004-07-29 | Commissariat A L'energie Atomique | Procede de realisation d'une structure contrainte destinee a etre dissociee |
FR2848336A1 (fr) * | 2002-12-09 | 2004-06-11 | Commissariat Energie Atomique | Procede de realisation d'une structure contrainte destinee a etre dissociee |
US8048766B2 (en) | 2003-06-24 | 2011-11-01 | Commissariat A L'energie Atomique | Integrated circuit on high performance chip |
US6982210B2 (en) | 2003-07-10 | 2006-01-03 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Method for manufacturing a multilayer semiconductor structure that includes an irregular layer |
US8193069B2 (en) | 2003-07-21 | 2012-06-05 | Commissariat A L'energie Atomique | Stacked structure and production method thereof |
EP1667207B1 (fr) * | 2003-09-08 | 2019-07-17 | SUMCO Corporation | Tranche collee et procede de fabrication |
US7772087B2 (en) | 2003-12-19 | 2010-08-10 | Commissariat A L'energie Atomique | Method of catastrophic transfer of a thin film after co-implantation |
WO2005076345A1 (fr) * | 2004-01-09 | 2005-08-18 | S.O.I.Tec Silicon On Insulator Technologies | Substrat a coefficient de dilatation thermique determine |
US7887936B2 (en) | 2004-01-09 | 2011-02-15 | S.O.I.Tec Silicon On Insulator Technologies | Substrate with determinate thermal expansion coefficient |
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US7439092B2 (en) | 2005-05-20 | 2008-10-21 | Commissariat A L'energie Atomique | Thin film splitting method |
US8142593B2 (en) | 2005-08-16 | 2012-03-27 | Commissariat A L'energie Atomique | Method of transferring a thin film onto a support |
US8664084B2 (en) | 2005-09-28 | 2014-03-04 | Commissariat A L'energie Atomique | Method for making a thin-film element |
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US8778775B2 (en) | 2006-12-19 | 2014-07-15 | Commissariat A L'energie Atomique | Method for preparing thin GaN layers by implantation and recycling of a starting substrate |
US7960248B2 (en) | 2007-12-17 | 2011-06-14 | Commissariat A L'energie Atomique | Method for transfer of a thin layer |
US8252663B2 (en) | 2009-06-18 | 2012-08-28 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method of transferring a thin layer onto a target substrate having a coefficient of thermal expansion different from that of the thin layer |
Also Published As
Publication number | Publication date |
---|---|
KR100743557B1 (ko) | 2007-07-27 |
FR2789518A1 (fr) | 2000-08-11 |
US6756285B1 (en) | 2004-06-29 |
KR20010113684A (ko) | 2001-12-28 |
JP2002536843A (ja) | 2002-10-29 |
JP4889154B2 (ja) | 2012-03-07 |
EP1155442B1 (fr) | 2008-12-17 |
DE60041124D1 (de) | 2009-01-29 |
EP1155442A1 (fr) | 2001-11-21 |
FR2789518B1 (fr) | 2003-06-20 |
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