Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/14—Handling requests for interconnection or transfer
  • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
  • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Definitions

• the present invention relates to direct memory access control in microcontrollers, and more particularly to a direct memory access engine for supporting multiple virtual direct memory access channels
• microcontroller or embedded controller which m effect is a microprocessor as used in a personal computer, but with a great deal of additional functionality combined onto the same monolithic semiconductor substrate (i.e , chip)
• the microprocessor performs the basic computing functions, but other mtegrated circuits perform functions such as communicating over a network, controlling the computer memory, and providmg input/output with the user
• a typical microcontroller such as the Aml86EM or AM186ES by Advanced Micro Devices, Inc , of Sunnyvale, California, not only includes a core microprocessor, but further includes a memory controller, a direct memory access (DMA) controller, an interrupt controller, and both asynchronous and synchronous se ⁇ al interfaces
• these devices are typically implemented as separate integrated circuits, requiring a larger area and increasing the size of the product
• DMA direct memory access
• an interrupt controller both asynchronous and synchronous se ⁇ al interfaces
• these devices are typically implemented as separate integrated circuits, requiring a larger area and increasing the size of the product
• size is dramatically reduced, often important in consumer products From a consumer products designer's viewpoint, often the particular combination of added features make a particular microcontroller attractive for a given application
• Many microcontrollers are available that use the standard 80x86 microprocessor instructions, allowing for software to be easily developed for such microcontrollers Because of the similar execution unit instruction sets, the added features often become principal differentiating c ⁇ te
• DMA direct memory access
• timer control units timer control units
• interrupt control units Such units off-load the tasks of waiting for certain external transactions to take place, and, in the case of the DMA unit, actually off-loading the task itself
• the DMA unit can be programmed to perform transfers between memory locations, between input/output ports, or between a memory location and an input/output port. Off-loading these tasks, the execution unit is freed from having to wait for such transfers to take place, and as such, can increase the overall speed of the computer system.
• the DMA unit functions, without involving the microprocessor, by initializing control registers m the DMA umt with transfer control information
• the transfer control information generally mcludes the source address (the address of the beginning of the block of data to be transferred), the destination address (the address where the beginning of the block of data is to be transferred), and the size of the data block
• a DMA umt may provide address and bus control signals to and from a pe ⁇ pheral or memory device such that the pe ⁇ pheral or memory device can access a pe ⁇ pheral or memory device for a read or a w ⁇ te cycle
• Specific channels are implemented in a DMA unit to allow pe ⁇ pheral or memory devices to transfer data (with or without internal data storage by the DMA unit) to or from other pe ⁇ pheral or memory devices.
• a channel can be activated via a DMA request signal (DREQ) from a penpheral or memory device.
• the DMA umt receives the DREQ, provides a DMA acknowledge signal (DACK) or simulated version thereof, and transfers the data over the channel to or from the penpheral or memory device
• DACK DMA acknowledge signal
• Pe ⁇ pheral devices which commonly use DMA channels include DRAM (dynamic random access memory) refresh circuitry, sound cards, SCSI host adapters, parallel ports, tape cards, network cards, modems, and floppy disk controllers.
• Direct memory access channels have traditionally been supported m hardware and managed by control logic within a direct memory access controller.
• This control logic has typically taken the form of multiple registers (e.g., DMA command registers, DMA mode registers, DMA status registers, DMA mask registers, DMA request registers, DMA count registers, and DMA address registers) which take up valuable silicon space.
• Each direct memory access channel has been associated with its own portion of the control logic (e.g., DMA count registers and DMA address registers)
• the present invention provides a direct memory access engine for supporting multiple virtual direct memory access channels
• the direct memory access engme mcludes a direct memory access controller and a parameter table in memory containing parameters for a plurality of virtual direct memory access channels.
• the direct memory access engme provides a single physical direct memory access channel and a plurality of virtual direct memory access channels.
• One channel of the plurality of virtual direct memory access channels may be active at a given time.
• the parameters for the active channel are loaded from the parameter table to the direct memory access controller.
• a physical direct memory access control block of the direct memory access controller utilizes a physical direct memory access channel resource to perform a direct memory access transfer for the active channel based on the loaded parameters
• the physical direct memory access channel resource of the controller is shared by the plurality of virtual direct memory access channels
• the direct memory access engme further mcludes a direct memory access request Ime and a direct memory access acknowledge Ime for an active channel of the plurality of virtual direct memory access channels
• the present invention eliminates the need for each direct memory access channel to be associated with its own control logic. In this way, memory is used to store direct memory access control information for a single direct memory access channel rather than consuming large areas of silicon with direct memory access control logic for multiple direct memory access channels BRIEF DESCRIPTION OF THE DRAWINGS
• Figure 1 is a block diagram of a microcontroller providing a direct memory access engine in accordance with the present invention
• Figure 2 is a schematic diagram of an exemplary direct memory access engine of Figure 1 in accordance with the present invention.
• Figure 3 is a flow chart of an exemplary virtual direct memory access control process in accordance with the present invention.
• FIG. 1 shows a block diagram of an exemplary architecture for a microcontroller M in accordance with the present invention.
• the microcontroller M may support a variety of on- chip units.
• an execution unit 100, a memory unit 102, a bus control unit 104, a direct memory access (DMA) unit 106, a test access port 108, a timer unit 110, a peripheral control unit 112, an interrupt control unit 114, a programmable I/O unit 116, and a port unit 118 are each coupled to a system bus 120.
• the system bus 120 may include a data bus, address bus, and control bus for communicating data, addresses and control irifbrmation between any of these coupled units.
• the execution unit 100 may provide a highly integrated processor 101 for executing code stored by the memory unit 102.
• the execution unit 100 in the disclosed embodiment is compatible with the Aml86 instruction set implemented in a variety of microcontrollers from Advanced Micro Devices, Inc. of Sunnyvale, California. A variety of other execution units could be used instead of the execution unit 100.
• the memory unit 102 may support multiple memory controllers for controlling communication of data to and from on-chip or off-chip memory devices. These memory devices for example may include dynamic random access memory (DRAM), read only memory (ROM), and/or flash memory.
• DRAM dynamic random access memory
• ROM read only memory
• flash memory an example of a memory controller is a DRAM controller providing extended data out (EDO) and synchronous DRAM (SDRAM) support, write buffering support, and read-ahead buffering support.
• EDO extended data out
• SDRAM synchronous DRAM
• the bus control unit 104 may provide a host of bus controllers for controlling a variety of buses and supporting the peripherals connected to those buses. These bus controllers for example may include a USB
• the bus control unit 104 thus permits the microcontroller M to support a number of external buses and peripherals.
• the DMA unit 106 may provide multiple DMA controllers having several DMA channels for controlling direct memory access transfers between the units of the microcontroller M.
• the DMA unit 106 provides a DMA engine 150 for supporting multiple virtual DMA channels.
• the test access port 108 provides a scan interface for testing the microcontroller M in a production environment and supports a test access port (TAP) controller for controlling test logic of the port 108.
• TAP test access port
• the peripheral control unit 112 may provide a host of integrated peripheral controllers for controlling a variety of peripheral devices. These peripheral controllers, for example, may include a graphics controller, a keyboard controller, and/or a PC Card controller.
• the graphics controller preferably provides an internal unified memory architecture (UMA) and software compatibility with a va ⁇ ety of graphic adapters
• UMA internal unified memory architecture
• the PC Card controller or adapter preferably conforms to PCMCIA (Personal Computer Memory Card International Association) standards.
• the interrupt control umt 114 may provide multiple interrupt controllers for supporting several interrupt requests. Each interrupt controller may regulate issuance and acceptance of its associated interrupt requests.
• the programmable I/O umt 116 supports several general-purpose I/O pins. These pins provide a parallel mterface for external devices to the microcontroller M.
• the port umt 118 may provide a standard parallel port mterface, se ⁇ al port mterface, and/or infrared port interface.
• the parallel port mterface may support an enhanced parallel port (EPP) mode for high speed transfers.
• EPP enhanced parallel port
• the se ⁇ al port mterface and infrared mterface may be d ⁇ ven by an lndustry- standard umversal asynchronous receiver/transmitter (UART) so as to permit PC compatibility.
• the microcontroller M could be the Ami 86TM ED microcontroller, the ElanTM SC400 microcontroller, or the Ami 86TM CC microcontroller It should be understood that the disclosed units are illustrative and not exhaustive. A number of the illustrated units could be eliminated, or added to, without detracting from the spi ⁇ t of the mvention. Further, selection of the particular units supported by the microcontroller M may be a function of the particular microcontroller application.
• microcontroller M thus provides architectural flexibility.
• the techniques and circuitry accordmg to the mvention could be applied to a wide va ⁇ ety of microcontrollers.
• microcontroller itself has different definitions m the industry. Some companies refer to a processor core with additional features (such as I/O) as "microprocessor” if it has no on-board memory, and digital signal processors (DSPs) are now used for both special and general purpose controller functions.
• microcontroller covers all of the products, and generally means an execution umt with added functionality all implemented on a single monolithic mtegrated circuit.
• the DMA engme 150 provides a DMA controller 200 and a memory 208.
• the DMA controller 200 supports a smgle physical DMA channel 204 and a plurality of virtual DMA channels 202.
• the plurality of virtual DMA channels 202 are represented as n (n bemg any mteger) virtual DMA channels.
• One channel of the plurality of virtual DMA channels 202 may be active at a given time
• the active virtual DMA channel utilizes the smgle physical DMA channel 204.
• the physical DMA channel 204 thus is alternated among the plurality of virtual DMA channels 202.
• the physical DMA channel 204 mdicated by diagonal references lmes, is shown as corresponding to a VIRTUAL DMA 1 channel.
• a DMA transfer by an active virtual DMA channel 202 is controlled by a physical DMA control block 206 of the DMA controller 200.
• the physical DMA control block 206 may mclude any combination of five standard types of configuration registers 228: DMA mode registers, DMA status registers, DMA mask registers, DMA request registers, and DMA command registers At any given time, the physical DMA control block 206 may be configured to accommodate a virtual DMA channel 202 that utilizes the physical DMA channel 204.
• the DMA controller 200 further mcludes a physical DMA channel resource 220.
• the physical DMA channel resource 220 and the physical DMA control block 206 are programmed with parameters for a DMA transfer by an active virtual DMA channel
• the physical DMA channel resource 220 is configured to only accommodate a smgle physical DMA channel 204
• the physical DMA channel resource 220 may include a set of DMA transfer control resources, such as DMA transfer count registers 224 and DMA address counters (source and destination) 226, for a smgle DMA channel.
• the DMA controller 200 may support any number of physical DMA channels 204 shared by a larger number of virtual DMA channels 202.
• the physical DMA channel resource 220 and the physical DMA control block 206 are programmed with parameters for a DMA transfer by an active virtual DMA channel
• the physical DMA channel resource 220 is configured to only accommodate a smgle physical DMA channel 204
• the physical DMA channel resource 220 may include a set of DMA transfer control resources, such as DMA transfer count registers 224 and DMA address counters (source
• the physical DMA channel resource 220 is preferably configured to ⁇ irnimize hardware
• the DMA controller 200 is further coupled to a memory 208 and a pe ⁇ pheral device 216.
• the DMA controller 200 provides a memory read signal MEM RD and a memory w ⁇ te signal MEM WR to the memory 208.
• a pe ⁇ pheral read signal DEV RD and a pe ⁇ pheral wnte signal DEV WR are provided by the DMA controller 200 to the pe ⁇ pheral device 216
• the memory 208 provides a parameter table or similar data arrangement 210 for storing parameters for the plurality of virtual DMA channels 202.
• the parameters for the plurality of virtual DMA channels 202 may be loaded to the parameter table 210 by the execution unit 100
• the memory 208 provides an address Ime ADDR to the execution umt permitting the execution unit 100 to address the parameter table 210
• DMA channel 202 are provided from the parameter table 210 to the physical DMA channel resource 220 and to the physical DMA control block 206.
• the relevant parameters are loaded to the physical DMA resource 220 of the DMA controller 200 by the execution umt 100.
• the DMA controller 200 performs a DMA transfer based on the loaded parameters During a DMA transfer, the DMA controller 200 owns a local data bus DATA coupled to the memory 208, the pe ⁇ pheral device 216 and the execution umt 100.
• a memory-penpheral device transfer is a data transfer from the memory device 208 to the penpheral device 216 m accordance with the memory read signal MEM RD and the penpheral wnte signal DEV WR.
• a penpheral-memory device transfer is a data transfer from the penpheral device 216 to the memory device 208 in accordance with the penpheral read signal DEV RD and the memory wnte signal MEM WR
• a memory-memory device transfer is a data transfer from one memory address area of the memory device 208 to another memory address area of the memory device 208 m accordance with the memory read signal MEM RD and the memory wnte signal MEM WR.
• a penpheral-pe ⁇ pheral device transfer is a data transfer from an I/O address area of the penpheral device 216 to another I/O address area of the penpheral device 216 m accordance with the penpheral read signal DEV RD and the pe ⁇ pheral wnte signal DEV WR
• a memory-memory device transfer or a penpheral-penpheral device transfer may mclude a read phase, an internal data storage phase, and a wnte phase.
• a read address is applied to a memory 208 or penpheral device 216
• the read data may be stored by a temporary register (not shown) of a DMA controller 200.
• a wnte address is then applied to the memory 208 or penpheral device 216
• a memory-memory transfer or a penpheral-penpheral transfer may be performed without a temporary register While a smgle memory device 208 and a smgle penpheral device 216 are illustrated for simplicity, the DMA controller 150 may also control DMA transfer among a plurality of memory devices and a plurality of penpheral devices.
• a virtual DMA channel 202 may be allocated to the memory device 208 or the penpheral device 216
• the DMA engine 150 further includes a DMA request acknowledge port block 212.
• the DMA request/acknowledge port block 212 may receive a request signal DREQ(n) from the peripheral device 216 or the memory device 208.
• a device provides a DMA request signal DREQ(n) to the DMA request acknowledge port block 212 to request a DMA transfer.
• the DMA request/acknowledge port block 212 may supply a DMA acknowledge signal DACK(n) to the peripheral device 216 or the memory device 208.
• An active DMA acknowledge signal DACK(n) indicates a virtual DMA channel 202 is enabled and the corresponding device that issued the DMA request is being serviced.
• the exemplary virtual DMA control process represents the initialization and execution of a DMA transfer by a virtual DMA channel 202. Beginning in step 300, it is determined if a direct memory access request signal DRQ(n) has been asserted by the peripheral device 216 or the memory device 208 to the DMA request/acknowledge port block 212. If no DRQ(n) is asserted or active, control remains at step 300. If a DRQ(n) is active, control proceeds to step 302 where an interrupt signal INT is provided by the DMA request/acknowledge port block 212 to the execution unit 100.
• DRQ(n) direct memory access request signal
• step 304 the execution unit 100 provides a CPU read signal CPU RD to read the DMA request/acknowledge port block 212 and determine which device has requested service. From step 304, control proceeds to step 306 where the DMA controller 200 is loaded with parameters for the virtual DMA channel 202 located for the DMA transfer. The parameters are loaded from the parameter table 210 to the DMA control block 206 and the physical DMA resource 220. A portion of the parameters may be loaded to the DMA control block 206, and a portion of the parameters may be loaded to the physical DMA channel resource 220.
• the DMA engine 150 may further include a DMA arbiter (not shown) for selecting a virtual DMA channel 202 among multiple virtual DMA channel requests in accordance with a particular arbitration scheme. If multiple direct memory access request signals DRQ(n) go active at the same time, the direct memory access request DRQ(n) with the highest priority is selected.
• step 308 the DMA controller 200 acknowledges the requesting device with a general acknowledge signal ACK.
• step 309 an acknowledge signal DACK(n) is asserted to the requesting device by the
• the DMA request/acknowledge port block 212 to enable or activate the allocated or active virtual DMA channel 202.
• the appropriate DACK(n) signal is determined by steering logic 214 of the DMA request/acknowledge port block 212.
• the steering logic 214 essentially detects the general acknowledge signal ACK co ⁇ esponding to the allocated or active virtual DMA channel 202 so that a corresponding acknowledge signal DACK(n) may be provided to the requesting device.
• the acknowledge signal DACK(n) Prior to this steering phase, the acknowledge signal DACK(n) is shared in a virtual sense at a physical level by the plurality of virtual DMA channels 202. At a physical level, the physical DMA channel 204 virtually shares a general acknowledge signal ACK.
• the general acknowledge signal ACK is steered to the appropriate DACK(n) signal.
• step 310 the DMA transfer for the active virtual DMA channel 202 is performed based on the parameters loaded to the physical DMA control block 206 and the physical DMA channel resource 220. From step 310, the DMA transfer for the active virtual DMA channel 202 is performed based on the parameters loaded to the physical DMA control block 206 and the physical DMA channel resource 220. From step 310, the DMA transfer for the active virtual DMA channel 202 is performed based on the parameters loaded to the physical DMA control block 206 and the physical DMA channel resource 220. From step 310, the DMA transfer for the active virtual DMA channel 202 is performed based on the parameters loaded to the physical DMA control block 206 and the physical DMA channel resource 220. From step 310, the DMA transfer for the active virtual DMA channel 202 is performed based on the parameters loaded to the physical DMA control block 206 and the physical DMA channel resource 220. From step 310, the DMA transfer for the active virtual DMA channel 202 is performed based on the parameters loaded to the physical DMA
• control proceeds to step 312 where the execution unit 100 is informed of completion of the virtual DMA operation such as by an interrupt. Control terminates through step 314 where the virtual DMA control process is complete.
• the present invention provides a direct memory access engine 150 for supporting multiple virtual direct memory access channels 202.
• the direct memory access engine 150 includes a direct memory access controller 200 and a parameter table 210 in memory 208 containing parameters for a plurality of virtual direct memory access channels 202
• the direct memory access engme 150 provides a smgle physical direct memory access channel 204 and a plurality of virtual direct memory access channels 202 One channel of the plurality of virtual direct memory access channels 202 may be active at a given time
• the parameters for the active channel 202 are loaded from the parameter table 210 to the direct memory access control block 206 and the physical direct memory access channel resource 220 of the direct memory access controller 200
• the physical direct memory access control block 206 utilizes the physical DMA channel resource 220 to perform a direct memory access transfer for the active channel 202 based on the loaded parameters
• the physical DMA channel resource 220 is shared by the plurality of virtual direct memory access channels 202
• the direct memory access engme 150 further mcludes a direct memory access request
• the DMA controller 200 may support multiple physical DMA channel resources 200 and multiple physical DMA control blocks 206 to accommodate any number of physical DMA channels 204 shared by a larger number of virtual DMA channels 202
• the present mvention eliminates the need for each direct memory access channel to be associated with its own control logic In this way, memory is used to store direct memory access control information for a smgle direct memory access channel rather than consuming large areas of silicon with direct memory access control logic for multiple direct memory access channels

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• 1998
  • 1998-11-24 US US09/198,797 patent/US6260081B1/en not_active Expired - Lifetime
• 1999
  • 1999-06-29 WO PCT/US1999/014797 patent/WO2000031648A1/en not_active Ceased
  • 1999-06-29 DE DE69903061T patent/DE69903061T2/de not_active Expired - Lifetime
  • 1999-06-29 JP JP2000584397A patent/JP4562107B2/ja not_active Expired - Lifetime
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