WO2000008763A1 - Procede d'elaboration d'un signal d'horloge et circuit a phase asservie - Google Patents

Procede d'elaboration d'un signal d'horloge et circuit a phase asservie Download PDF

Info

Publication number
WO2000008763A1
WO2000008763A1 PCT/FI1999/000607 FI9900607W WO0008763A1 WO 2000008763 A1 WO2000008763 A1 WO 2000008763A1 FI 9900607 W FI9900607 W FI 9900607W WO 0008763 A1 WO0008763 A1 WO 0008763A1
Authority
WO
WIPO (PCT)
Prior art keywords
phase
output
lock circuit
loop
signal
Prior art date
Application number
PCT/FI1999/000607
Other languages
English (en)
Finnish (fi)
Inventor
Paulus Carpelan
Original Assignee
Nokia Networks Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Networks Oy filed Critical Nokia Networks Oy
Priority to AU50417/99A priority Critical patent/AU5041799A/en
Publication of WO2000008763A1 publication Critical patent/WO2000008763A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
    • H03L7/235—Nested phase locked loops

Definitions

  • phase lock circuit which generates a clock signal locked to the reference signal to be input for the circuit.
  • the data stream coming from the network functions as a reference signal.
  • the phase lock circuit has to be as immune as possible against phase noise coming from the network and, in addition, phase noise caused by the circuit itself has to be as low as possible.
  • the technologies involved are ISDN and xDSL.
  • character x means different digital subscriber line technologies, such as ADSL, HDSL or VDSL.
  • ISDN connections are fairly widely available to subscribers.
  • the maximum speed of the basic ISDN connection is 128 kbit/s, whereas e.g. the HDSL (high bit rate digital subscriber line) technique allows a transmission speed of 2 Mbit/s.
  • HDSL high bit rate digital subscriber line
  • the basic problem will be the generation of the clocks for the network terminal for different line speeds.
  • problems are caused by the fixed frame structure of HDSL (16k) and control time intervals dependent on speed, since they create a situation where e.g. when the data speed is halved the line speed will not be halved.
  • the following table illustrates some data speeds (different values of N) and corresponding line speeds.
  • the invention relates to generation of a clock signal using a phase-locked loop.
  • the invention is intended to be used in particular in a network element, such as a network terminal device, in a digital telecommunications system.
  • a terminal device containing a circuit according to the invention can be implemented using e.g. the HDSL technology.
  • Figure 1 illustrates a known phase lock circuit

Abstract

L'invention porte sur un procédé d'élaboration d'un signal d'horloge à l'aide d'un circuit à phase asservie, et sur le circuit à phase asservie lui-même. Le circuit à phase asservie comporte une boucle (300) à phase asservie comprenant séquentiellement: un détecteur de phase (101), un filtre en boucle (102) et un oscillateur commandé par tension (103) dont la sortie est rétroinjectée dans le détecteur de phase (101). Le procédé consiste à transférer un signal extérieur (CLK IN) dans le circuit à phase asservie lequel sert à produire un signal d'horloge de sortie (CLK OUT) asservi au signal extérieur (CLK IN). Pour pouvoir utiliser le circuit à phase asservie, par exemple pour produire un signal d'horloge nécessaire au terminal de réseau et satisfaisant aux exigences de bruit de phase, on crée dans le circuit à phase asservie une deuxième boucle (301) à rétroaction reliant la sortie de la boucle à phase asservie à son détecteur de phase (101). Cette boucle comporte un oscillateur (203) à cristal commandé par la tension créée à partir du signal extérieur (CLK IN), et du signal d'horloge de sortie (CLK OUT) asservi. Ledit signal d'horloge est produit à la sortie de la boucle asservie en phase au moyen du signal de référence (RCLK) provenant de l'oscillateur à cristal en reliant fonctionnellement le signal de référence au détecteur de phase (101) de la boucle asservie en phase.
PCT/FI1999/000607 1998-07-31 1999-07-09 Procede d'elaboration d'un signal d'horloge et circuit a phase asservie WO2000008763A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU50417/99A AU5041799A (en) 1998-07-31 1999-07-09 Method for generating a clock signal and a phase lock circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI981685 1998-07-31
FI981685A FI105425B (fi) 1998-07-31 1998-07-31 Kellotaajuuksien generointi

Publications (1)

Publication Number Publication Date
WO2000008763A1 true WO2000008763A1 (fr) 2000-02-17

Family

ID=8552252

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FI1999/000607 WO2000008763A1 (fr) 1998-07-31 1999-07-09 Procede d'elaboration d'un signal d'horloge et circuit a phase asservie

Country Status (3)

Country Link
AU (1) AU5041799A (fr)
FI (1) FI105425B (fr)
WO (1) WO2000008763A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103812636A (zh) * 2012-11-09 2014-05-21 江苏绿扬电子仪器集团有限公司 针对高速数据采集系统获取高质量采样时钟的装置
WO2014146274A1 (fr) 2013-03-21 2014-09-25 Telefonaktiebolaget L M Ericsson (Publ) Procédé et appareil de mise en œuvre de maintien d'horloge
CN114679173A (zh) * 2021-10-06 2022-06-28 绍兴圆方半导体有限公司 锁相环和系统

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991007016A1 (fr) * 1989-10-25 1991-05-16 Telenokia Oy Boucle a verrouillage de phase servant a produire une porteuse de reference pour un detecteur coherent
US5423075A (en) * 1992-01-21 1995-06-06 Temic Telefunken Microelectronic Gmbh Combined radio transmission and reception apparatus with a PLL circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991007016A1 (fr) * 1989-10-25 1991-05-16 Telenokia Oy Boucle a verrouillage de phase servant a produire une porteuse de reference pour un detecteur coherent
US5423075A (en) * 1992-01-21 1995-06-06 Temic Telefunken Microelectronic Gmbh Combined radio transmission and reception apparatus with a PLL circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103812636A (zh) * 2012-11-09 2014-05-21 江苏绿扬电子仪器集团有限公司 针对高速数据采集系统获取高质量采样时钟的装置
WO2014146274A1 (fr) 2013-03-21 2014-09-25 Telefonaktiebolaget L M Ericsson (Publ) Procédé et appareil de mise en œuvre de maintien d'horloge
EP2976851A4 (fr) * 2013-03-21 2016-11-16 Ericsson Telefon Ab L M Procédé et appareil de mise en oeuvre de maintien d'horloge
US9660797B2 (en) 2013-03-21 2017-05-23 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for implementing clock holdover
CN114679173A (zh) * 2021-10-06 2022-06-28 绍兴圆方半导体有限公司 锁相环和系统
CN114679173B (zh) * 2021-10-06 2022-08-30 绍兴圆方半导体有限公司 锁相环和时钟同步系统

Also Published As

Publication number Publication date
FI981685A0 (fi) 1998-07-31
AU5041799A (en) 2000-02-28
FI105425B (fi) 2000-08-15
FI981685A (fi) 2000-02-01

Similar Documents

Publication Publication Date Title
EP0644657B1 (fr) Circuit de boucle à verrouillage de phase
US5910753A (en) Direct digital phase synthesis
EP1867092B1 (fr) Nettoyage de donnees avec une horloge de reference asynchrone
US5661765A (en) Receiver and transmitter-receiver
US8537957B2 (en) Clock synchroniser
EP0671829B1 (fr) Circuit de regénération d'horloge
US4972442A (en) Phase-locked loop clock
KR100834393B1 (ko) 클럭 데이터 복원장치.
CA2125443C (fr) Circuit pour oscillateur controlable
US6703877B2 (en) Clock shaping circuit and electronic equipment
US7170964B2 (en) Transition insensitive timing recovery method and apparatus
US6150855A (en) Phase-locked loop and resulting frequency multiplier
US6389090B2 (en) Digital clock/data signal recovery method and apparatus
US7502435B2 (en) Two-point modulator arrangement and use thereof in a transmission arrangement and in a reception arrangement
EP1239627B1 (fr) Circuit de récupération d'horloge et de données
US20030025564A1 (en) Multi-frequency synthesizer apparatus and method
KR100317679B1 (ko) 링 발진기 출력파형간의 위상 오프셋을 보정하기 위한자기 보정회로 및 방법
US6333678B1 (en) Method and apparatus for agile phase noise filtering using phase locked loops
CN112994687B (zh) 一种参考时钟信号注入锁相环电路及消除失调方法
WO2000008763A1 (fr) Procede d'elaboration d'un signal d'horloge et circuit a phase asservie
US6683920B1 (en) Dual-loop system and method for frequency acquisition and tracking
US20040071168A1 (en) System and method for providing network timing recovery
JPS6059822A (ja) 周波数変換回路
Jiang et al. A compact phase interpolator for 3.125 G Serdes application
AU705852B2 (en) Clock and data regenerator for gigabit signals

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW SD SL SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: CA