AU5041799A - Method for generating a clock signal and a phase lock circuit - Google Patents

Method for generating a clock signal and a phase lock circuit

Info

Publication number
AU5041799A
AU5041799A AU50417/99A AU5041799A AU5041799A AU 5041799 A AU5041799 A AU 5041799A AU 50417/99 A AU50417/99 A AU 50417/99A AU 5041799 A AU5041799 A AU 5041799A AU 5041799 A AU5041799 A AU 5041799A
Authority
AU
Australia
Prior art keywords
generating
clock signal
phase lock
lock circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU50417/99A
Inventor
Paulus Carpelan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Oyj
Original Assignee
Nokia Networks Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Networks Oy filed Critical Nokia Networks Oy
Publication of AU5041799A publication Critical patent/AU5041799A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
    • H03L7/235—Nested phase locked loops

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
AU50417/99A 1998-07-31 1999-07-09 Method for generating a clock signal and a phase lock circuit Abandoned AU5041799A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FI981685 1998-07-31
FI981685A FI105425B (en) 1998-07-31 1998-07-31 Generation of clock frequencies
PCT/FI1999/000607 WO2000008763A1 (en) 1998-07-31 1999-07-09 Method for generating a clock signal and a phase lock circuit

Publications (1)

Publication Number Publication Date
AU5041799A true AU5041799A (en) 2000-02-28

Family

ID=8552252

Family Applications (1)

Application Number Title Priority Date Filing Date
AU50417/99A Abandoned AU5041799A (en) 1998-07-31 1999-07-09 Method for generating a clock signal and a phase lock circuit

Country Status (3)

Country Link
AU (1) AU5041799A (en)
FI (1) FI105425B (en)
WO (1) WO2000008763A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103812636A (en) * 2012-11-09 2014-05-21 江苏绿扬电子仪器集团有限公司 Device for high-speed data acquisition system to acquire high-quality sampling clock
US9660797B2 (en) 2013-03-21 2017-05-23 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for implementing clock holdover
CN114679173B (en) * 2021-10-06 2022-08-30 绍兴圆方半导体有限公司 Phase-locked loop and clock synchronization system

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI895068A0 (en) * 1989-10-25 1989-10-25 Telenokia Oy Frequency synthesizer.
DE4201415A1 (en) * 1992-01-21 1993-07-22 Telefunken Microelectron COMBINED RADIO TRANSMITTER AND RECEIVER WITH A PLL CIRCUIT

Also Published As

Publication number Publication date
WO2000008763A1 (en) 2000-02-17
FI981685A (en) 2000-02-01
FI981685A0 (en) 1998-07-31
FI105425B (en) 2000-08-15

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase