AU705852B2

AU705852B2 - Clock and data regenerator for gigabit signals

Info

Publication number: AU705852B2
Application number: AU59967/96A
Authority: AU
Inventors: Wolfgang Zirwas
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 1995-06-26
Filing date: 1996-06-18
Publication date: 1999-06-03
Anticipated expiration: 2016-06-18
Also published as: BR9608981A; CN1193434A; EP0835571A1; AU5996796A; WO1997001901A1; CN1135781C

Description

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e According to one aspect of the present invention there is provided an arrangement for clock and data regeneration, said arrangement comprising: an exclusive OR gate the output of which is connected to a control input of a voltage-controlled oscillator via a low-pass filter, a first, second, and third D-flip-flops wherein the data inputs of said first, second and third D-flip-flops are each connected to a data input of said arrangement and each of said D-flip-flops receive a separate clock signal, and wherein said clock signals of said D-flip-flops have half the frequency of a maximum data rate, wherein said clock signals of said first D-flip-flop and of said second D-flipflop have opposite phase, and wherein said clock signal of said third D-flip-flop are phase-shifted by 900 relative to said clock signals of said first and second D-flip-flops, wherein the outputs of said second and said third D-flip-flop are connected to associated inputs of said exclusive OR gate, an output of which delivers a phase discriminator signal determining the frequency of said voltage-controlled oscillator) said voltage- 15 controlled oscillator having an output signal connected directly to said third D-flip-flop or through a delay element to said clock inputs of said first D-flip-flop, and said second D-flip-flop or said third D-flip-flop.

In a number of applications, when there is severe temperature- or age-related frequency drift in the voltage-controlled oscillator used for the phase-locked loop, the problem may occur that the latter has a capture range which is too small for the intended purpose. For this reason, in one development of the invention, the phaselocked loop is supplemented by a frequency control loop with a comparatively large capture range, which is based on the fact that the mean value of the phase detector 0e@C S [N:\LIBPP0O1038:IAD 2Aoutput voltage is a measure of the frequency offset of the voltage-controlled oscillator, and therefore the phase detector can also be used as a frequency detector. In addition, these developments can have a window comparator or a frequency detector.

The invention is intended to be explained in more detail below using exemplary embodiments, illustrated in the drawing, of the arrangement for clock and data regeneration and additions to it.

In the drawing: Figure 1 shows an arrangement for clock and data regeneration with a phaselocked loop Figure 2 shows a pulse diagram for the arrangement according to Fig. 1, Figure 3 shows an arrangement according to Figure 1 with the addition of a window comparator, Figure 4 shows an arrangement according to Figure 1 with the addition of a 15 frequency detector, and Figure 5 shows a phase-locked loop with an interference-compensated phase detector o a a a o *oa oO a [N:\LIBPP]01038:BFD 3 The basic circuit, shown in Figure 1, of an arrangement for clock and data regeneration simultaneously carries out the function of a demultiplexer, which splits up data signals arriving at the data input Din at a bit rate of, for example, 20 GBit/s into two data streams at 10 GBits/s each which are present at the first and second data outputs D1, D2. The D-inputs of first, second and third D-flip-flops DF1, DF2, DF3 contained in a regenerator unit PDM are connected to the data input Din, and either the non-inverting or the inverting outputs of these D-flip-flops are connected to associated output connections D1, D2 for the useful signal and D3 for test purposes for the regenerator unit DPM. In addition, the first input of a first exclusive OR gate EXOR1 is connected to the output of the second Dflip-flop DF2 directly or via a fourth D-flip-flop DF4, and the second input of an exclusive OR gate EXOR is connected in a corresponding manner to the output of the third D-flip-flop DF3 directly or via a fifth D-flip-flop DF5. The output of this exclusive OR gate is connected via a low-pass filter TPF to a first voltage-controlled oscillator VCO1, which produces a clock signal at the desired frequency of, for example, 10 GHz and supplies it to the clock inputs C3, C4 and C5 of the third, fourth and fifth D-flip-flops DF3, DF4, DF5. In addition, the clock signal produced is supplied to a delay element T, contained in the regenerator unit PDM, which supplies a clock signal delayed by half a clock cycle by 25 ps in the exemplary embodiment to the clock input C2 of the second D-flip-flop DF2, and, in addition, supplies the same signal inverted to the clock input C1 of the first D-flip-flop DFl, and can be measured and adjusted via an additional connection AS.

To explain the operation of the arrangement according to Figure 1, the pulse diagram according to Figure 2 illustrates the waveforms of a few signals in the desired state. The data signal arriving at the data input Din is illustrated in the top line with its poss- 4N ible amplitudes. In the steady state, 4 this signal is synchronized with the clock signals at the clock inputs C2 and C3 firstly at the bit center and secondly at the data edges, with the result that the signal at the data output D2 is produced. The second and the third D-flip-flop DF2 and DF3, with a probability, then use either the same bit twice or directly adjacent bits. With a similarly 50% probability that two adjacent bits assume different values this relates to scrambled data signals different values are detected in the desired state in 25% of cases. Now, if the sampling instant changes, the second and the third Dflip-flop DF2, DF3 use either the same bit or the adjacent bits correspondingly more frequently. The lower lines of the diagram in Figure 2 show the signal D1, produced by sampling with the clock signal Cl, at the corresponding output connection, shifted accordingly with respect to the signal D2.

The exclusive OR gate EXOR receives the output signals of the second and the third D-flip-flop DF2, DF3 either directly or after intermediate sampling in the fourth and fifth D-flip-flops DF4, DF5, respectively, for the purpose of adjusting the delay. If these output signals are now different then the exclusive OR gate EXOR produces a signal pulse. These pulses are passed through the low-pass filter TPF for time-averaging and serve to control the voltage-controlled oscillator VCO which oscillates at a frequency of 10 GHz, corresponding to half the bit repetition rate of the incoming data, and produces a corresponding clock signal. Thus, with little complexity, the arrangement shown combines a clock and data regeneration system with a demultiplexer, in which the highest processing speeds occur only in the regenerator unit PDM.

Although in many cases the capture range of the phase-locked loop in the arrangement according to Figure 1 is sufficiently large, as it is, for the operation intended, there are applications 5 in which frequency changes occur, with the result that the circuit arrangement according to Figure 1 requires the addition of a frequency control loop with a correspondingly large capture range. Figure 3 illustrates an arrangement with such an addition which again contains the regenerator unit PDM according to Figure 1, the fourth and fifth D-flip-flops DF4, DF5 and the exclusive OR gate EXOR following on from the data input Din, with the first and second data outputs Dl, D2 being retained and the output connection of the exclusive OR gate EXOR being connected to the low-pass filter TPF. In the present case, this low-pass filter is designed as an active module using a first operational amplifier OP1, and the output of the exclusive OR gate EXOR is passed via a first resistor R1 to an inverting input of the first operational amplifier OPi, whose non-inverting input is connected to a source VR for a reference voltage. The output connection of the first operational amplifier is connected to the inverting input of the first operational amplifier via a series circuit formed by a first capacitor C1 and a second resistor R2 in order to produce the desired filter function; in addition the output connection of this operational amplifier is connected to a third resistor R3 which forms a potential divider to reference-ground potential with a fourth resistor R4, and the center connection of this potential divider is connected to the control input of the voltagecontrolled oscillator VCO via a fifth resistor The section described represents the phase discriminator circuit with a low-pass filter disclosed in Figure i, which now has a comparator stage for frequency control added to it. To this end, the non-inverting input of a second operational amplifier OP2, which, in addition, is connected to reference-ground potential via the series circuit formed by an eleventh resistor R11 and a third capacitor, is connected to the output connection of the first operational amplifier OPI via a thirteenth resistor R13, a fourth capacitor C4 being connected in parallel with this series circuit as a filter capacitor.

6 In addition, a variable reference-voltage source VRV is connected via a ninth resistor R9 to the inverting input of the second operational amplifier OP2, whose output is connected to the inverting input of the second operational amplifier OP2 via the series circuit formed by a second capacitor C2 and a tenth resistor R10 for the purpose of setting the desired function. This second operational amplifier OP2 uses the waveform of the output voltage of the first operational amplifier OPI to recognize whether the phase-locked loop has locked on, and readjusts the frequency loop after comparison with the variable reference voltage. To this end, the output connection of the second operational amplifier OP2, which at the same time is the output connection of the frequency loop, is connected to ground via a potential divider formed from a second and an eighth resistor R7, R8, a sixth resistor R6 being connected to the center tap of the potential divider and passing on a corresponding control signal to the regulation-voltage input of the first voltage-controlled oscillator VC01. In addition, this regulation-voltage input is connected to an operating voltage UO via a twelfth resistor.

As an aid to capturing, particularly after switching on, a commercially available window comparator FK is connected to the output of the second operational amplifier OP2 and represents two comparators connected in parallel and having different threshold voltages, with the result that an upper and a lower threshold are produced for the control range of the frequency loop. The output connection of the window comparator FK is connected to the inverting input of the first operational amplifier OPI via a diode D and a fourteenth resistor R14. When designing the output connections of the two comparators forming the window comparator, wiring of the output connections can be chosen differently, in each case using a separate diode-resistor element for the first operational amplifier OPl, with the result that the limits of the control range can also be set S asymmetrically.

7 Figure 4 illustrates an alternative solution for the combination of a phase-locked loop with a frequency controller. Besides the signal input of the regenerator unit PDM, a frequency detector FD known per se is additionally connected to the data input Din, although this frequency detector is relatively complex for the frequency range under consideration. Omitting the fourth and fifth D-flip-flops, the inputs of the exclusive

OR

gate EXOR are connected directly to the output connections D2, D3 of the regenerator unit and the output of the exclusive OR gate Exon, as shown in the circuit arrangement according to Figure 3, is connected to a control input of the voltage-controlled oscillator

VCO

via an active loop filter formed from the first operational amplifier OPI and additional circuitry.

Again, the second operational amp-lifier OP2 is also provided and its output connection is connected to the control input of the voltage-controlled oscillator

VCO

via the sixth resistor R6 and to the inverting input of the second operational amplifier OP2 via the series circuit formed by the second capacitor C2 and the tenth resistor RI0. The non-inverting input of this operational amplifier is connected to reference-ground potential via the series circuit formed by the eleventh resistor R11 and the third capacitor C3 and, in addition, optionally via the thirteenth resistor R13 to the output of the first operational amplifier OPl. Add-itionally, the noninverting input of the second operational amplifier OP2 is connected via the fourteenth resistor R14, and the inverting input is connected via associated output connections of the frequency detector FD. At its output connections, the frequency detector FD produces signals which correspond to the frequency difference between the clock frequency of the data signals received and the locally produced clock frequency. Furthermore, a connection between the frequency control loop and the phase-locked loop is additionally formed via the thirteenth resistor R13, and allows for regulation as in the arrangement according to Figure 3 in the case of 7a small frequency differences.

8 The embodiments to date have been based on a phase discriminator or phase detector implemented by the combination of a D-flip-flop contained in the regenerator unit PDM and an exclusive OR gate EXOR. As a result of sampling the data signals in the D-flip-flop, an interference spectrum arises at the output of a phase discriminator of this type which can lead to unwanted phase modulation of the voltage-controlled oscillator VCO and thus to increased phase jitter in the data signals emitted. Hence, Figure 5 illustrates an arrangement for clock and data regeneration according to the invention which contains a jitter-compensated phase discriminator.

Again, Figure 5 is based on the regenerator unit PDM, to the second and third signal outputs D2, D3 of which the inputs of the exclusive OR gate EXOR are connected either directly or via the fourth and fifth D-flip-flops. In the arrangement according to Figure 5, the first and second data outputs D1, D2 of the regenerator unit PDM are connected to the inputs of an additional exclusive

OR

gate ZXOR, whose output is connected to one input of a commercially available analog multiplexer AMUX. The other input of this analog multiplexer is connected to reference-ground potential, whilst the control input is connected to the output of a generator G, which oscillates at a frequency of, for example, 100 MHz, which is many times less than the bit rate of the regenerated data signals. The output of the analog multiplexor represents the non-inverting phase discriminator output, and the output of the exclusive OR gate EXOR represents the inverting phase discriminator output, and both output connections can be connected directly or via resistors to the non-inverting and the inverting input of the first operational amplifier OPl in Figure 3. The output of the generator G is additionally connected to a clock input of a phase shifter dt, whose signal input is connected to the output of the voltage-controlled oscillator VCO in the phase-locked loop. In addition, this output is connected as before to the input of the delay element T ST of the 9 regenerator unit PDM. The output of the phase shifter dt is connected to the clock input of the third D-flip-flop DF3 of the regenerator unit PDM. Low-pass filters which suppress the residual components of the high-frequency data signal and interference signals can additionally be inserted into the connection between the output of the analog multiplexor AMX and the non-inverting phase discriminator output PDA, and into the connection between the outputs of the exclusive OR gate EXOR and the inverting phase discriminator output

(PDA).

In the arrangement according to Figure 5, the interference-signal suppression is performed by two measures: the first measure is to simulate the interference signal and combine the simulation, in antiphase, with the original interference signal, thus compensating for the latter. In addition, a high-frequency oscillation at, for example, 100 MHz is supplied, in antiphase in each case, to two clock inputs of the phase discriminator which are in antiphase and form a differential clock input, and this produces phase modulation of the clock signal acting on the third D-flip-flop, as a result of which the interference signals are suppressed. As a result of the phase modulation of the clock signal acting on the third D-flip-flop DF3 by the output signal of the generator

G,

during one half cycle of the output signal of the generator G, the second and the third D-flip-flops DF2, DF3 use the same bit of the data signal, with the result that the exclusive OR gate EXOR goes to the zero level.

During the other half cycle, the first and the third

D-

flip-flops DFl, DF3 use the same bit, with the result that identical signals occur at the exclusive OR gate EXOR and at the additional exclusive OR gate ZXOR. When the output signal of the exclusive OR gate EXOR becomes zero, the analog multiplexor AMUX is likewise set to zero. In the desired state, the same signal is formed at both outputs of the exclusive OR gate EXOR and is compensated for by antiphase addition in the course of FZZ1, further processing.

The claims defining the invention are as follows: 1. An arrangement for clock and data regeneration, said arrangement comprising: an exclusive OR gate the output of which is connected to a control input of a voltage-controlled oscillator via a low-pass filter, a first, second, and third D-flip-flops wherein the data inputs of said first, second and third D-flip-flops are each connected to a data input of said arrangement and each of said D-flip-flops receive a separate clock signal, and wherein said clock signals of said D-flip-flops have half the frequency of a maximum data rate, wherein said clock signals of said first D-flip-flop and of said second D-flipflop have opposite phase, and wherein said clock signal of said third D-flip-flop are phase-shifted by 90° relative to said clock signals of said first and second D-flip-flops, wherein the outputs of said second and said third D-flip-flop are connected to associated inputs of said exclusive OR gate, an output of which delivers a phase discriminator 15 signal determining the frequency of said voltage-controlled oscillator, said voltagecontrolled oscillator having an output signal connected directly to said third D-flip-flop or through a delay element to said clock inputs of said first D-flip-flop, and said second D-flip-flop or said third D-flip-flop.

2. The arrangement according to Claim 1, wherein an additional fourth and fifth D-flip-flop clocked with said output signal of said voltage-controlled oscillator is inserted in each of connections between said output of said second and said third D-flip-flop and said inputs of said exclusive OR gate.

3. The arrangement according to Claim 1 or 2, wherein an input of a comparator stage is connected directly or via said low-pass filter to said output of said exclusive OR gate with said comparator stage generating an Radditional control signal for said voltage-controlled oscillator out of said phase S discriminator signal and a reference voltage.

[N:\LIBPP0O1038:IAD

Claims

4. The arrangement according to Claim 1, wherein said output of said exclusive OR gate is connected to said control input of said voltage-controlled oscillator via an active loop filter and said output of said exclusive or GATE is connected via a first resistor to said inverting input of a first operational amplifier a noninverting input of which is connected to a source for a reference voltage (VR), and wherein said output of said first operational amplifier is connected, on the one hand, via a series circuit formed by a first capacitor and a second resistor (R2) to a inverting input of said operational amplifier and, on the other hand, via a series circuit formed by a third and fourth a resistor to reference potential, wherein 00 a junction point of said third and said fourth resistor has a fifth resistor •o 0 connected to it, another terminal of which is connected to the control input of said S. voltage-controlled oscillator, and wherein •go 15 there is provided a second operational amplifier a noninverting input of which is connected to reference potential via a series circuit formed by a third capacitor and an eleventh resistor, wherein said noninverting input is also connected via a fourth capacitor to reference potential and via a thirteenth resistor to an output of said first operational amplifier, and wherein "said inverting input of said second operational amplifier is connected via a ninth resistor to an adjustable bias voltage source and via a series circuit formed by a :tenth resistor and a second capacitor to said output of said second operational amplifier, o•wherein said output terminal is connected to reference potential via a series circuit formed by a seventh and an eighth resistor and at a junction point of said seventh and said eighth resistor and at a junction point of said seventh and said eighth resistor there .[N:\LIBPP01038:IAD -12- is connected a sixth resistor another terminal of which is connected to the control input of said voltage-controlled oscillator, and wherein said control input is additionally connected to a bias voltage source via a twelfth resistor, wherein said output of said second operational amplifier is connected to an input of a window comparator which comprises two comparators connected in parallel and having different threshold voltages, and wherein said output of said window comparator is connected to an inverting input of said first operational amplifier via a series circuit formed by a diode and a fourteenth resistor. S. S•o•
5. The arrangement according to Claim 1, 2 or 3, owherein said output of said exclusive OR gate is connected to said control input of said voltage-controlled oscillator via an active loop filter formed by means of a first operational amplifier, and wherein S. a noninverting input of a second operational amplifier is connected to a reference potential via an eleventh resistor and a third capacitor and can be optionally connected to an output of said first operational amplifier via a thirteenth resistor, wherein an inverting input of said second operational amplifier is connected to an output of said second operational amplifier via a series circuit formed by a second capacitor and a tenth resistor and this second operational amplifier is connected to said control input of said voltage-controlled oscillator via a sixth resistor, and wherein -there is provided a frequency detector an input of which is connected with said data input, and outputs of which are separately connected via a fourteenth and a fifteenth resistor to said inverting input and noninverting input respectively of said second operational amplifier (OP2). [N:\LIBPP]01038:IAD -13-
6. The arrangement according to Claim 1, 2 or 3, wherein said outputs of said second and said third D-flip-flop are connected to said inputs of said exclusive OR gate via a fourth and a fifth D-flip-flop.
7. The arrangement according to any one of the preceding claims, wherein an additional exclusive OR gate is provided for generating a reference signal to said phase discriminator signal out of said output signals of said first D-flip-flop and said second D-flip-flop.
8. The arrangement according to Claim 7, wherein two inputs of said additional exclusive OR gate are respectively separately connected to said first and said second output of said first D-flip-flop and said second D-flip-flop, and wherein S• said output of said additional exclusive OR gate is connected to one input of an o* 15 analog multiplexer another input of which is connected to reference potential, and a clock input of which is connected to an output of a generator and said output of said additional exclusive OR gate is a noninverting phase discriminator output, wherein said output of said exclusive OR gate forms a inverting phase discriminator output, and wherein said output of said generator which oscillates at a single frequency approximately 100 times lower than the clock frequency of regenerated data signals, is connected to a control input of a phase shifting phase a signal input of which is "connected to an output of said voltage-controlled oscillator of said phase control loop and said output of which is connected to said clock input of said third D-flip-flop, wherein said output of said voltage-controlled oscillator is connected to a signal input of a delay element. IN:\LIBPP]01038:IAD
14- 9. The arrangement acording to any one of the preceding claims, wherein said clock and data regeneration occurs at gigabit rates. An arrangement for clock and data regeneration substantially as herein described with reference to the accompanying drawings. DATED this Eleventh Day of March 1999 Siemens Aktiengesellschaft Patent Attorneys for the Applicant SPRUSON FERGUSON e* S S S IN:\LIBPP]O1038:IAD Abstract Clock and data regenerator for gigabit signals During the transmission of digital signals at gigabit rates, the critical path lengths are so small that, in customary clock recovery circuits, phase jitters between the clock phase and data phase are to be expected of the order of the very short bit length. A clock and data regenerator is therefore proposed containing only three D-flip-flops connected in parallel at the input side and one delay element, which receive the high bit rates of the input signal, whereas the design as a 2:1 demultiplexer at the same time means that all other components work at lower clock and data rates. To widen the capture range, developments of the invention contain a frequency control loop connected to a downstream window discriminator or frequency detector. Figure 1 7 fz -U QpT\~ OSFNGJ O DD