CN101546206B - Method and device for achieving digital circuit clock source with dynamically variable frequencies - Google Patents
Method and device for achieving digital circuit clock source with dynamically variable frequencies Download PDFInfo
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- CN101546206B CN101546206B CN2008100841406A CN200810084140A CN101546206B CN 101546206 B CN101546206 B CN 101546206B CN 2008100841406 A CN2008100841406 A CN 2008100841406A CN 200810084140 A CN200810084140 A CN 200810084140A CN 101546206 B CN101546206 B CN 101546206B
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Abstract
The invention provides a method for achieving a circuit capable of dynamically changing the clock frequency of a synchronous digital circuit system. By adopting the method, the clock frequency of a system can be changed randomly between thousands of hertz and thousands of megahertz in real time, and the system can respond to and execute various task requests in real time and can enter a low power consumption state in real time when no task is requested so that the system reduces useless power consumption to the utmost extent, thus the method is particularly suitable for systems which have a wide variation range of task request amount and need to respond to and execute the task requests in real time.
Description
Technical field
The present invention relates generally to contain the system of synchronous sequence digital circuit; Dynamically change the various electronic equipments that contain synchronizing sequential circuit of performance and power consumption such as needs; Adopt method of the present invention can realize dynamically, surpass the digital circuit clock frequency control of three one magnitude frequency ranges, reduce the ineffective power consumption of electronic equipment to greatest extent.What specifically, the present invention relates to is to come the dynamically performance and the power consumption of control electronic equipment with the method for control clock frequency; Rare or when not having task in electronic system, make system works under enough low clock frequency, reach the purpose that reduces system power dissipation; When the electronic system task increases, can be real-time system clock frequency is improved the performance requirement that satisfies system, clock frequency can improve until maximum operation frequency in real time.
Background technology
In actual life; Not always not the operating at full capacity of electronic equipment that much contains synchronizing sequential circuit (like electronic digital computer); In order to reduce power consumption; When system's underloading or no-load, stop partial circuit work, let system get into the method that holding state or sleep state are common minimizing ineffective power consumptions, for needs real-time return to the electronic equipment of the state of operating at full capacity from low power consumpting state, these methods that reduce power consumptions are difficult to meet the demands.
Present synchronizing sequential circuit basically all is the cmos digital circuit; The performance of cmos digital circuit and dynamic power consumption all are directly proportional with clock frequency; And the quiescent dissipation of cmos digital circuit is very low almost can ignore; If the clock frequency of real-time and dynamic control cmos digital circuit just can make the electronic equipment that contains synchronizing sequential circuit have best performance and power consumption ratio.
The invention provides the implementation method of a kind of dynamic control figure Circuits System clock source frequency of operation; The real-time change scope of clock frequency can surpass 3 one magnitude; Therefore can be in system reduce system clock frequency during few or underloading; Make system works under can battery-powered low power consumpting state, and need not get into standby or sleep state, when system load increases; In several clock period, promptly can improve clock frequency and satisfy performance requirement, realize the high-performance and the low-power consumption of electronic equipment until maximum operation frequency.
Adopt method provided by the invention; Can there be the clock source of a plurality of different frequencies in a synchronous digital circuit system; The clock source of three frequencies for example; A low-frequency clock (1-1000KHz) makes the power consumption of system drop to extremely low level, and an intermediate frequency clock (1-100MHz) makes system works under medium-performance, and a high frequency clock (0.1-10GHz) makes the performance of system perform to the limit; Switching clock source only needs several clock period, and unwanted clock source can quit work and further reduce power consumption.Because the change of frequency in clock source is consuming time few; System can set a working clock frequency for each task, and after a task obtained the control to system, at first clock frequency was set to the clock frequency of this task; After task scheduling continues to regain the control to system; Again clock frequency is reverted to the task scheduling clock frequency, so just can keep real-time response and execution, can in time restore the system to low power consumpting state again the task request.
Summary of the invention
Method of the present invention provides a kind of implementation method of clock source circuit of dynamically variable frequencies of synchronous sequence digital circuit, and clock source circuit is by constituting like all or part of of lower component, and the quantity of each parts can be 0 or 1 or more:
The band or not with the reference clock source that enables control signal;
2. the clock-signal generator of dynamically variable frequencies;
3. the frequency counter of variable division coefficient;
4. based on the frequency multiplication oscillator of phase-locked loop (Phase Lock Loop) or delay-locked loop (Delay Lock Loop).
The dynamically changeable frequency clock source circuit that adopts method of the present invention to realize, can satisfy various static state or (with) requirement of dynamic synchronization sequential digital circuitry.The not restriction of the frequency range of clock output both can be the circuit maximum operation frequency, also can be the frequency than low several orders of magnitude of circuit maximum operation frequency.Clock output both can be that dutycycle is 1: 1 a single-phase or polyphase signa, also can be that dutycycle is not 1: 1 a single-phase or polyphase signa.
Description of drawings
Below at first the accompanying drawing of instructions of the present invention is simply introduced, and then combined these accompanying drawings that each enforcement example of the present invention is introduced, principle and advantage of the present invention is described.
In the accompanying drawings:
Fig. 1 is according to a preferred synoptic diagram of implementing the reference clock source (0000) of example design of the present invention.
Fig. 2 is according to a preferred circuit structure block diagram of implementing the clock-signal generator (1000) of example design of the present invention.
Fig. 3 is according to a preferred circuit structure block diagram of implementing the frequency counter (2000) of example design of the present invention.
Fig. 4 is according to a preferred synoptic diagram of implementing the frequency doubling clock source (3000) of example design of the present invention.
Fig. 5 is according to a preferred circuit structure block diagram of implementing the middling speed clock generator (4000) of example design of the present invention.
Fig. 6 is according to a preferred circuit structure block diagram of implementing example designed high speed clock generator (5000) of the present invention.
Fig. 7 is according to a preferred circuit structure block diagram of implementing the middling speed dynamic clock source (6000) of example design of the present invention.
Fig. 8 is according to a preferred circuit structure block diagram of implementing example designed high speed dynamic clock source (7000) of the present invention.
Fig. 9 is according to a preferred circuit structure block diagram of implementing the middling speed combination clock source (8000) of example design of the present invention.
Figure 10 is according to a preferred circuit structure block diagram of implementing example designed high speed combination clock source (9000) of the present invention.
The practical implementation method
The invention provides a kind of implementation method of clock source circuit (hereinafter to be referred as the V-CLK source) of dynamically variable frequencies; The V-CLK source circuit is by reference clock source (0000), clock-signal generator (1000), frequency counter (2000), frequency doubling clock source (3000; Can not have) etc. parts constitute, its principle of work is following:
1. reference clock source (0000) produces reference frequency clock signal (0900);
2. clock-signal generator (1000) produces the clock signal (1900) of dynamically variable frequencies under the control of reference frequency clock (0900) and upset control signal (1040);
3. frequency counter (2000) to clock signal (2010) frequency division, produces periodic upset control signal (2900) according to the divide ratio of setting (2040);
4. frequency doubling clock source (3000) produce the clock signal (3900) that is higher than reference clock frequency according to the frequency multiplication coefficient of setting (3060); Alternative reference clock signal de-energisation clock-signal generator (1000) and frequency counter (2000) when needed are to produce the output clock that frequency is higher than reference clock frequency.
Fig. 1 is according to a preferred synoptic diagram of implementing the reference clock source (0000) of example design of the present invention.When enable signal (0010) was invalid, reference clock source was not worked, when enable signal (0010) is effective, and the continual output reference clock signal of reference clock source (0000) (0900).
Fig. 2 is according to a preferred circuit structure block diagram of implementing the output clock source (1000) of example design of the present invention.(1500), (1600), (1700) are D-latchs among the figure; The equivalent logical operation of D-latch (1500) and (1700) is that the equivalent logical operation of
D-latch (1600) is that
(1010) are input clock signals, and this signal can be also can be the signal (3900) from frequency doubling clock source (Fig. 4) from the signal of reference clock source (Fig. 1) (0900); D-latch (1500) and D-latch (1600) have constituted T-flip flop (1400); Signal (1030) is the enable signal of (1400), and signal (1040) is the upset control signal of (1400), promptly from the signal (2900) of frequency counter (Fig. 3); The output signal (1130) of D-latch (1700) the output signal (2120) of D-latch (1600) relatively postpones half clock period; Signal (1020) is the enable signal of D-latch (1700), and when (1020) were effective, clock signal (1900) frequency was 2 times of signal (1120) frequency; When (1020) invalid, signal (1900) and signal (1120) same frequency.The frequency of signal (1020) and (1040) decision signals (1900), the frequency of (1900) and clock (1010) frequency ratio can be 1,1/2,1/4,1/6,1/8 ...
Fig. 3 is according to a preferred circuit structure block diagram of implementing the frequency counter (2000) of example design of the present invention.The effect of this module is the pulse signal (2900) that periodically produces a single clock cycle according to the divide ratio (2040) that is provided with, and this signal is sent to the upset that the signal (1120) in the control chart 2 is removed in output clock source (1000).The bit number of divide ratio (2040) receives the restriction of input clock (2010) frequency; When (2010) frequency was high, the bit number of (2040) possibly be low to moderate 2bit, when (2010) frequency is low; (2040) bit number can suitably increase, to increase the frequency range of output signal (2900).Signal (2110) is the divide ratio N after latching, and signal (2120) is a count value of removing the Fractional-N frequency counter, and signal (2130) is to remove the zero clearing of Fractional-N frequency counting or put several signals.
Fig. 4 is according to a preferred synoptic diagram of implementing the frequency doubling clock source (3000) of example design of the present invention.Reference clock source (0000) generally is the outer crystal oscillator of a chip; Therefore reference clock frequency is difficult to bring up to the maximum clock frequency of circuit working in the chip; In the time of need being operated in high clock frequency like fruit chip; Clock source circuit in the chip just needs frequency doubling clock source (3000), and it is the clock signal (3900) of the integral multiple of reference clock (3010) frequency that its effect produces frequency according to the Clock Multiplier Factor (3060) that is provided with exactly.The critical piece in frequency doubling clock source (3000) is phase-locked loop (Phase Lock Loop) or delay-locked loop (Delay Lock Loop), is not the content that application of the present invention need be explained, seldom explanation here.
Fig. 5 is according to a preferred circuit structure block diagram of implementing the middling speed clock source (4000) of example design of the present invention.Circuit is made up of an output clock source (1000) and a frequency counter (2000); Directly adopt reference clock (4010) as circuit clock; Under the control of control signal (4020), (4030) and (4040), produce the output clock (4900) that frequency dynamic changes, the function of each control signal all has description in the explanation of Fig. 1, Fig. 2 and Fig. 3.
Fig. 6 is according to a preferred circuit structure block diagram of implementing example designed high speed clock source (5000) of the present invention.Circuit is made up of output clock source (1000), a frequency counter (2000) and a frequency doubling clock source (3000); Reference clock (5010) becomes high frequency clock (5110) as circuit clock through after the frequency multiplication; Under the control of control signal (5020), (5030), (5040) and (5060), produce the output clock (5900) that frequency dynamic changes, the function of each control signal all has description in the explanation of Fig. 1, Fig. 2, Fig. 3 and Fig. 4.
Fig. 7 is according to a preferred circuit structure block diagram of implementing the middling speed dynamic clock source (6000) of example design of the present invention.Circuit is made up of a reference clock source (0000) and two middling speed clock sources (4000); Under the control of control signal (6020), (6030), (6040), (6050), (6120), (6130) and (6140), produce the output clock (6900) that frequency dynamic changes, the explanation of the visible Fig. 1 of the function of each control signal and Fig. 5.The cascade in two middling speed clock sources (4000) is for the output clock frequency that produces has enough big variation range, if reference clock frequency is lower or only need less frequency range, can only need a middling speed clock source (4000).
Fig. 8 is according to a preferred circuit structure block diagram of implementing example designed high speed dynamic clock source (7000) of the present invention.Circuit is made up of a reference clock source (0000), a high-speed clock source (5000) and two middling speed clock sources (4000); Under the control of control signal (4020), (4030) and (4040), produce the output clock (4090) that frequency dynamic changes, the explanation of the visible Fig. 1 of the function of each control signal and Fig. 5 and Fig. 6.The cascade in a high-speed clock source (5000) and two middling speed clock sources (4000) is in order to produce the output clock frequency of enough big variation range, if only need less frequency range, can only need one or without middling speed clock source (4000).
Fig. 9 is according to a preferred circuit structure block diagram of implementing the middling speed combination clock source (8000) of example design of the present invention.Circuit is made up of two reference clock sources (0000), three middling speed clock sources (4000) and a clock selector (8800).Under the control of control signal (8020), (8040), (8050), (8120), (8140), (8150), (8220) and (8240), produce the output clock (8900) that frequency dynamic changes, the explanation of the visible Fig. 1 of the function of each control signal and Fig. 5.Two reference clock sources (0000) are operated in low frequency (8010) and medium frequency (8110) respectively; Under the control of signal (8330), select to produce output clock (8900) by clock selector (8800), so just can only produce an internal clock signal (8310) or (8320) where necessary by which reference clock source (0000).The process that clock selecting is switched is: 1. make signal (8030) and (8130) invalid a period of time (for example several switching controls clock period) simultaneously, 2. make the enable signal (8030) in selecteed middling speed clock source (4000) or (8130) effective.
Figure 10 is according to a preferred circuit structure block diagram of implementing example designed high speed combination clock source (9000) of the present invention.Circuit is made up of three reference clock sources (0000), a high-speed clock source (5000), two middling speed clock sources (4000) and a clock selector (9800).In control signal (9020), (9040), (9050), (9120), (9140), (9150), (9220), (9240), (9250), (9260), (9320), (9340), (9420) and 9440) control under produce the output clock (9900) that frequency dynamic changes, the explanation of the visible Fig. 1 of the function of each control signal and Fig. 5 and Fig. 6.Three reference clock sources (0000) are operated in low frequency (9010), medium frequency (9110) and high-frequency (9210) respectively; Under the control of signal (9540), select to produce output clock (9900) by clock selector (9800), so just can only produce an internal clock signal (9510) or (9520) or (9530) where necessary by which reference clock source (0000).The process that clock selecting is switched is: 1. make signal (9030), (9130) and (9230) invalid a period of time (for example several switching controls clock period) simultaneously, 2. make the enable signal (9030) of selecteed middling speed clock source (4000) or high-speed clock source (5000) or (9130) or (9230) effective.
Claims (7)
1. the frequency changer of a digital dock comprises:
A) one-period is the reference clock source of T;
B) the variable counter cnt of settings N programmed control, clock is a reference clock source, its output is that width is that T, cycle are the pulse signal of N*T, N is 1,2,3 ...;
C) two D-latch D1 and D2 by level control constitute one except that two counter DIV; The output of D1 connects the input of D2, connects the input of D1 after the output anti-phase of D2, and the control end that latchs of D1 and D2 connects reference clock source respectively; A positive output that connects reference clock source; A negative output that connects reference clock source, D1 and D2 enable control end with the output that meets CNT, and the output of DIV is to be the square-wave signal of 2*N*T in the cycle;
D) delay D-latch LTH by level control; Latch control termination reference clock source; The phase place of the reference clock source that connects is identical with the phase place of the reference clock source that D1 connect among the DIV, when outside input enable control end when effective, with the cycle of half reference clock source of output delay of DIV;
E) output of the output of D2 and LTH generates the output clock by XOR gate among the DIV, and the ratio of the frequency of input clock and the frequency of output clock is 1 or 2*N.
2. digital dock frequency-transposition arrangement comprises:
A) exercisable frequency changer as claimed in claim 1;
B) pulse signal generator of exercisable variable cycle.
3. the DCS digital clock source of a dynamically variable frequencies comprises:
A) exercisable frequency-transposition arrangement as claimed in claim 2;
B) reference clock source.
4. digital dock frequency-transposition arrangement comprises:
A) exercisable frequency changer as claimed in claim 1;
B) pulse signal generator of exercisable variable cycle;
C) the frequency multiplication oscillator of exercisable variable power.
5. the DCS digital clock source of a dynamically variable frequencies comprises:
A) exercisable frequency-transposition arrangement as claimed in claim 4;
B) reference clock source.
6. the DCS digital clock source of a dynamically variable frequencies comprises:
A) number is more than 1 exercisable DCS digital clock source like claim 3 or claim 5;
B) control of exercisable a plurality of DCS digital clock sources like claim 3 or claim 5 and multiselect 1 device;
C) selectable do not have or one or more frequency-transposition arrangements according to claim 2.
7. the kinetic controlling equation method of a digital circuitry clock frequency adopts one or more exercisable DCS digital clock sources like claim 3 or claim 5 or claim 6, makes the dynamically variable frequencies of system clock.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100841406A CN101546206B (en) | 2008-03-26 | 2008-03-26 | Method and device for achieving digital circuit clock source with dynamically variable frequencies |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008100841406A CN101546206B (en) | 2008-03-26 | 2008-03-26 | Method and device for achieving digital circuit clock source with dynamically variable frequencies |
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| CN101546206A CN101546206A (en) | 2009-09-30 |
| CN101546206B true CN101546206B (en) | 2012-02-08 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2014039817A2 (en) * | 2012-09-07 | 2014-03-13 | Calhoun Benton H | Low power clock source |
| CN103955256B (en) * | 2014-04-24 | 2017-04-12 | 华为技术有限公司 | Clock frequency modulation method and clock frequency modulation device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1193434A (en) * | 1995-06-26 | 1998-09-16 | 西门子公司 | Clcok and data regenerator for gigabit signals |
| CN2922277Y (en) * | 2005-10-25 | 2007-07-11 | 中兴通讯股份有限公司 | Clock burr testing circuit |
| CN101087141A (en) * | 2007-07-10 | 2007-12-12 | 中国人民解放军国防科学技术大学 | Idle percent adjustable N-time frequency division circuit of pulse mixing mode |
-
2008
- 2008-03-26 CN CN2008100841406A patent/CN101546206B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1193434A (en) * | 1995-06-26 | 1998-09-16 | 西门子公司 | Clcok and data regenerator for gigabit signals |
| CN2922277Y (en) * | 2005-10-25 | 2007-07-11 | 中兴通讯股份有限公司 | Clock burr testing circuit |
| CN101087141A (en) * | 2007-07-10 | 2007-12-12 | 中国人民解放军国防科学技术大学 | Idle percent adjustable N-time frequency division circuit of pulse mixing mode |
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| CN101546206A (en) | 2009-09-30 |
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