WO2000002134A2 - Protocole ameliore de bus en serie entre dispositifs - Google Patents

Protocole ameliore de bus en serie entre dispositifs Download PDF

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Publication number
WO2000002134A2
WO2000002134A2 PCT/US1999/014696 US9914696W WO0002134A2 WO 2000002134 A2 WO2000002134 A2 WO 2000002134A2 US 9914696 W US9914696 W US 9914696W WO 0002134 A2 WO0002134 A2 WO 0002134A2
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WO
WIPO (PCT)
Prior art keywords
data
wire
master
slave
clock
Prior art date
Application number
PCT/US1999/014696
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English (en)
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WO2000002134A3 (fr
Inventor
Sanjay K. Jha
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Priority to CA002336385A priority Critical patent/CA2336385A1/fr
Priority to JP2000558463A priority patent/JP2003534580A/ja
Priority to BR9911732-0A priority patent/BR9911732A/pt
Priority to IL14056899A priority patent/IL140568A0/xx
Priority to KR1020017000012A priority patent/KR20010053365A/ko
Priority to EP99932038A priority patent/EP1145132A3/fr
Priority to AU48432/99A priority patent/AU4843299A/en
Publication of WO2000002134A2 publication Critical patent/WO2000002134A2/fr
Priority to NO20006698A priority patent/NO20006698L/no
Publication of WO2000002134A3 publication Critical patent/WO2000002134A3/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol

Definitions

  • the present invention relates to inter-device serial buses.
  • the invention relates to an inter-device serial bus having a small number of lines and using a protocol for facilitating simple master/slave relationships between devices connected to the bus, some of which may utilize a different protocol.
  • Electronic devices hand-held cellular phones, electronic calculators, CD players, camcorders, to name a few — include various internal components (ICs or chips) controlled by a single-chip microprocessor. Frequently, these devices incorporate an inter-device serial bus to link their internal components together. The chips communicate with an internal microprocessor, transferring data to and from the microprocessor via the inter-device serial bus.
  • the microprocessor has certain control over the chip. For example, it can configure the chip so that it uses no power, change its functionality, and otherwise interact with the chip to change its performance. Absent a serialization process, i.e., the use of an inter-device serial bus, each communication from the microprocessor to a particular chip would need to be routed separately to the chip's appropriate register using more pins and potentially including greater power consumption. However, with the use of an inter-device serial bus, a small number of pins can be used to facilitate the control of hundreds of functions in various chips by a microprocessor.
  • the Phillips I 2 C-bus is a commonly used inter-device serial bus protocol.
  • slave chips listen to the bus, and when addressed by the processor serving as a master, respond by grabbing the appropriate messages, internally decoding address information, and directing the data accordingly.
  • processor serving as a master
  • responses by grabbing the appropriate messages, internally decoding address information, and directing the data accordingly.
  • an improved inter-device serial bus protocol which is operable over a wide range of clock rates, and can coexist with the two-wire Phillips I 2 C bus protocol.
  • Such a protocol would need to accommodate the transferring of clock information, data information, and information controlling the starting and stopping of transactions among inter- connected chips.
  • such a protocol would need to include mechanisms for arbitrating among plural masters accessing the serial bus, for addressing slave devices, and for indicating when data should be read from or written to a slave device. Communication between devices via such an improved serial bus protocol would preferably involve a synchronous operation.
  • Information for controlling the flow of information over a bus may include a start transaction indication, and a stop transaction indication.
  • Parity This term denotes a quality of sameness or equivalence between devices communicating with each other. It may comprise an error-checking procedure in which transfer data is checked, for example, to determine if the information being transmitted is transmitted without error.
  • Any device receiving data from a data line provided on the bus Any device receiving data from a data line provided on the bus.
  • Serial Communication The transfer of information between computers or other devices one bit at a time over a single line.
  • Serial communication can be synchronous (controlled by a time standard such as a clock) or asynchronous (managed by the exchange of control signals that govern the flow of information).
  • a time standard such as a clock
  • asynchronous manufactured by the exchange of control signals that govern the flow of information.
  • both the sender and receiver use the same parity and control information.
  • a device that can be written to and read from, but which does not initiate a transaction.
  • a transaction comprises the transfer of data between a master and a slave for a period of time extending between the time at which the data transfer is initiated by the master until the time at which the data transfer is terminated by the master or another device.
  • Any device connected to a bus which is transmitting information over a data line provided on the bus Any device connected to a bus which is transmitting information over a data line provided on the bus.
  • the present invention is provided to improve upon existing serial interface protocols for linking master and slave devices within small multi-chip devices.
  • the present invention generally provides mechanisms for implementing a synchronous protocol between devices via a bus interface.
  • the mechanisms facilitate efficient communication between various devices using only a small number of lines and otherwise facilitate the design and implementation of multiple chip devices and systems.
  • the protocol mechanisms presented herein further should further help with fault diagnosis and debugging of various components of the multi-chip system.
  • the present invention is directed to an inter-device serial bus protocol, or one or more parts thereof, for facilitating the interconnection and the communication among various devices via a serial bus.
  • the serial bus may comprise a clock wire, a data wire, and a start/stop wire.
  • a master serial bus interface may be provided which couples a master device to the serial bus.
  • a slave serial bus interface may be provided which couples a slave device to the serial bus.
  • the master serial bus interface comprises a transaction initiator, a data write mechanism, a data read mechanism, and a clock driver.
  • the transaction initiator initiates a transaction by pulling the signal level of the start/stop wire low.
  • the data write mechanism controls the signal level on the data wire in accordance with the data to be written to the slave device.
  • the data read mechanism reads data by monitoring the signal level on the data wire.
  • the clock driver controls the signal level on the clock wire in accordance with a desired clock signal.
  • Fig. 1. illustrates the connections of devices to an I 2 C-bus
  • Fig. 2 is a waveform diagram depicting a bit transfer on an I 2 C-bus
  • Fig. 3 is a waveform diagram depicting start and stop indications on an I 2 C-bus
  • Fig. 4 is a schematic representation of the basic data format of the I 2 C-bus protocol
  • Fig. 5 is a schematic diagram of a serial bus configuration in accordance with the illustrated embodiment of the present invention.
  • Fig. 6 shows a serial bus connected to devices utilizing the new protocol as well as devices utilizing the I 2 C-bus protocol
  • Fig. 7 illustrates an interrupt transfer mode (ITM) message format
  • Fig. 8 illustrates a fast transfer mode (FTM) message format
  • Fig. 9 illustrates a bulk transfer mode (BTM) message format
  • Fig. 10 is a block diagram of a master device
  • Fig. 11 is a more detailed block diagram of the master SBI controller illustrated in Fig. 10;
  • Fig. 12 is a block diagram of a data path block
  • Fig. 13 is a flow chart showing the operation of the master SBI controller of Fig. 10 performing a transaction; and Fig. 14 is a block diagram of a slave device.
  • Figs- 1-6 illustrates various aspects of the I 2 C-bus protocol and some example implementations thereof.
  • Figs. 7-24 illustrate in various respects an exemplary embodiment of the present invention, directed to a new serial bus interface (SBI) protocol.
  • SBI serial bus interface
  • the illustrated SBI protocol utilizes a bus having three wires. Devices can be coupled to the bus allowing them to transfer information to and from each other. Such devices include master devices and slave devices. An arbitration procedure may be incorporated in the SBI protocol for allowing more than one master to initiate a data transfer at the same time.
  • the illustrated SBI protocol is compatible not only with devices accommodating the new protocol, but also accommodates I 2 C-bus devices.
  • Fig. 1 shows a pair of devices connected to an I 2 C-bus, otherwise referred to as an I 2 C-bus configuration 10.
  • the illustrated I 2 C-bus configuration 10 comprises a bus 11 having a pair of wires.
  • the pair includes a first wire which is a serial data line SDA, and a second wire which is a serial clock line SCL.
  • Pull-up resistors 12, 13 are connected respectively at first ends thereof to serial clock line SCL and serial data line SDA, and at their second end to a common DC voltage source +V DD .
  • a pair of devices including a first device 14 and a second device 16 are coupled to the illustrated I 2 C-bus 11.
  • First device 14 comprises, among other elements (not shown), a clock interface circuit 18 and a data interface circuit 19.
  • Second device 16 comprises, among other elements (not shown), a clock interface circuit 18' and a data interface circuit 19'.
  • Each of the illustrated clock interface circuits 18, 18' comprises an amplifier and a transistor. When each wire SDA and SCL is free, both lines are high or in a one state.
  • the transistors of the respective data interface circuits 18, 18', 19, and 19' are coupled in an open-drain or open- collector fashion in order to perform a wired-AND function, so that when activated, they pull their respective line SDA or SCL down to a low state, thereby indicating a logical "zero".
  • CMOS complementary metal-oxide-semiconductor
  • NMOS NMOS
  • BIPOLAR a variety of different technologies
  • Fig. 2 is a waveform diagram depicting a bit transfer on an I 2 C-bus.
  • the top waveform is the signal and data line SDA
  • the bottom line is the signal and clock line SCL.
  • a stability check period 20 during which the clock signal is high, the level of the data signal on data line SDA cannot change.
  • a data line change period 22 the period during which the clock signal is low, the high or low state of the data line SDA can change.
  • One clock pulse is generated for each data bit transferred on data line SDA.
  • Fig. 3 shows a waveform diagram depicting the stop and start indications on an I 2 C-bus.
  • the two waveforms on data line SDA and clock line SCL, respectively, represent a start condition 24 and a stop condition 26 as shown.
  • Start condition 24 is indicated when there is a high to low transition on data line SDA while the signal on clock line SCL is high.
  • Stop condition 26 is indicated when there is a transition from a low to a high on data line SDA while the signal level on clock line SCL is high.
  • start and stop conditions are always generated by the master.
  • Fig. 4 is a schematic block diagram representing the general protocol format of the I 2 C-bus protocol.
  • a single transaction is shown, the start of which is indicated by start condition 24 and the end of which is indicated by stop condition 26.
  • the first byte of information transmitted includes a seven-bit slave address 28 followed by a one-bit read/write bit (R/W) 30.
  • An acknowledge bit A 32 then follows. Following the first acknowledge bit 32 is a byte of data and a second acknowledge bit 36.
  • An additional byte of data 38 follows, together with another acknowledge bit 40. As shown, each byte is followed by an acknowledge bit as indicated by the "A" blocks in the sequence.
  • R/W bit If the R/W bit is zero, data is written from the master to the slave device, in which case an acknowledge or failure to acknowledge only comes from the slave device to the master. If the R/W bit is a one, data is read from the slave to the master. If the R/W bit is a one, data is read from the slave device to the master device, and the acknowledgement bits are sent from the master device to the slave device.
  • Fig. 5 shows a serial bus configuration in accordance with an illustrated embodiment of the present invention.
  • a master device 50 is connected via a serial bus 48 to first and second slave devices 52, 54.
  • Serial bus 48 comprises a clock wire SBCK, a start/stop wire SBST and a data wire SBDT.
  • Clock wire SBCK and data wire SBDT are each connected to a pull-up DC voltage V DD via pull-up resistors R.
  • the pull-up resistor values may be adjusted to maintain a certain RC constant, as more devices are added on serial bus 48.
  • the start/stop wire SBST is not connected in a pull-up fashion.
  • Each of master device 50, first slave device 52, and second slave device 54 comprises a respective SBI controller and a set of bus interaction circuits which collectively serve as a serial bus interface for coupling the respective device to serial bus 48.
  • Master SBI controller 56 is connected to clock wire SBCK, start /stop wire SBST, and data wire SBDT via respective interaction circuits comprising a clock wire interaction circuit 62, a start/ stop wire interaction circuit 64, and a data wire interaction circuit 66.
  • the illustrated clock wire interaction 62 comprises a field effect transistor 68 comprising source, drain, and gate electrodes. Its source electrode is connected to clock wire SBCK. Its drain electrode is connected to ground, and its gate electrode is connected to a clock wire operation terminal 78 of master SBI controller 56.
  • Start/ stop interaction circuit 64 comprises an amplifier 70 having input and output terminals. Its output terminal is connected to start/stop wire SBST, and its input terminal is connected to a start/stop wire operation terminal 80.
  • Data /wire interaction circuit 66 comprises an amplifier 72 and a field effect transistor 74.
  • Amplifier 72 comprises an input terminal and an output terminal, the input terminal being connected to data wire SBDT, and the output terminal being connected to a data monitoring terminal 82 of master SBI controller 56.
  • Field effect transistor 74 comprises source, drain, and gate electrodes. Its source electrode is connected to data wire SBDT in common with the input terminal of amplifier 72. Its drain electrode is connected to ground. Its gate electrode is connected to a data operation terminal 84 of master SBI controller 56.
  • Each of slave devices 52 and 54 comprises a plurality of interaction circuits respectively coupled to clock wire SBCK, start/stop wire SBST, and data wire SBDT. More specifically, slave devices 52 and 54 comprise clock wire interaction circuits 63a and 63b connected to clock wire SBCK, start/stop wire interaction circuits 65a and 65b connected to start/stop wire SBST, and data wire interaction circuits 67a and 67b connected to data wire SBDT.
  • Clock interaction circuits 63a and 63b comprise respective amplifiers 86a and 86b.
  • Start/stop wire interaction circuits 65a and 65b comprise respective amplifiers 88a and 88b.
  • Data wire interaction circuits 67a and 67b comprise respective first and second sets of circuit elements.
  • the first set of circuit elements forming data wire interaction circuit 67a comprises an amplifier 90a and a field effect transistor 92a.
  • the second set of circuit elements forming data wire interaction circuit 67b comprises an amplifier 90b and a field effect transistor 92b.
  • Amplifier 86a comprises an input terminal and an output terminal, the input terminal being connected to clock wire SBCK, and the output terminal being connected to a clock monitoring terminal 94a.
  • Amplifier 88a comprises input and output terminals, the input terminal being connected to start/stop wire SBST, and the output terminal being connected to a start/stop monitoring terminal 96a.
  • Amplifier 90a comprises input and output terminals, the input terminal being connected to data wire SBDT, and its output terminal being connected to a data monitoring terminal 98a.
  • Field effect transistor 92a comprises source, drain and gate electrodes. Its source electrode is connected in common with the input terminal of amplifier 90a to data wire SBDT. Its drain electrode is connected to ground. Its gate electrode is connected to a data operation terminal of slave controller 58.
  • a zero is represented on any one of the wires SBCK, SBST, SBDT by a low voltage level.
  • a zero is indicated by pulling down the line, and a one is indicated by tri- stating the driver and letting an external pull-up take the voltage level high.
  • start/stop wire SBST a zero or a one is indicated under the exclusive control of the appropriate master controller 56 via an amplifier 70. When the signal at the output terminal of amplifier 70 is low, a zero is indicated on the start/stop wire SBST, and when the signal is high a "1" is indicated.
  • the clock wire interaction circuit 62 of master device 50 serves to allow a master SBI controller 56 to operate on clock wire SBCK via a clock wire operation terminal 78, thereby pulling the voltage level on clock wire SBCK low.
  • Start/stop wire detection circuit 64 of master device 50 facilitates the operation of master SBI controller 56 on start/stop wire SBST via a start/stop operation terminal 80, so as to control the signal level present on start/stop wire SBST.
  • Data wire interaction circuit 66 of master device 50 allows master SBI controller 56 to operate on data wire SBDT and to monitor the signal level on data wire SBDT via data monitoring terminal 82 and data operation terminal 84, respectively.
  • clock wire and master controller 56 will operate on the gate electrode of field effect transistor 68 via clock wire operation terminal 78, thus allowing the current to flow between the source and drain of field effect transistor 68 and bringing the voltage level present on clock wire SBCK low.
  • Master controller 56 operates on data wire SBDT by triggering the gate electrode of field effect transistor 74 via data operation terminal 84, thus causing the current to flow from the source to the drain of field effect transistor 74 and accordingly bringing the voltage level present on data wire SBDT low.
  • Each slave device 52 and 54 may monitor the signal level at each of clock wire SBCK, start/stop wire SBST, and data wire SBDT via a monitoring terminal which receives an output terminal of a corresponding amplifier.
  • slave SBI controller 58 of slave device 52 includes a clock monitoring terminal 94a which receive the output terminal of amplifier 86a, the input terminal of which is connected to clock wire SBCK.
  • Slave controller 58 also includes a start /stop monitoring terminal 96a which receives the output terminal of amplifier 88a, the input terminal of which is connected to start/stop wire SBST.
  • Data monitoring terminal 98a of slave controller 58 receives the output terminal of amplifier 90a, the input terminal of which is connected to data wire SBDT.
  • Data wire operation terminal 100a of slave controller 58 is connected to the gate electrode of field effect transistor 92a. This allows slave controller 58 to switch field effect transistor 92a, thus causing current to flow from the source to the drain of field effect transistor 92a and bringing the voltage level on data wire SBDT low.
  • Master device 50 is allowed to communicate with slave devices 52 and 54 (and optionally other devices, not specifically shown) via serial bus 48.
  • the illustrated serial bus 48 includes a set of bus wires (i.e., clock wire SBCK, start/stop SBST, and data wire SBDT).
  • a transaction between master device 50 and one or more of slave devices 52 and 54 can be initiated by master device 50 providing a start indication on start /stop wire SBST.
  • master SBI controller 56 of master device 50 will set the voltage level on start/stop wire SBST by outputting a voltage level at start /stop operation terminal 80 which will cause amplifier 70 to output the desired voltage level. More specifically, in the illustrated embodiment, master SBI controller 56 initiates a transaction by outputting a signal at start/stop operation terminal 80 resulting in pulling the signal level on start /stop wire SBST low.
  • a clock signal is placed on clock wire SBCK by master device 50.
  • Master controller 56 includes a clock driver (not shown in Fig. 5) which causes the appropriate operation signal to be output at clock wire operation terminal 78 in order to switch field effect transistor 68.
  • master SBI controller 56 controls the signal level on clock wire SBCK in accordance with a desire clock signal.
  • the resulting desired clock signal is used in common by master device 50 and slave devices 52 and 54 to facilitate synchronous operation of master device 50 and any one or more slave devices 52, 54 participating in the transaction.
  • Master SBI controller 56 of master device 50 comprises a data write mechanism, utilizing data operation terminal 84 to switch field effect transistor 74, thus either tri-stating field effect transistor 74 and leaving the voltage level on data wire SBDT high or pulling the voltage level down by causing a current flow from the source to the drain of field effect transistor 74. Accordingly, the signal level on data wire SBDT is controlled in accordance with data to be written to the slave device 52 or 54 participating in the particular transaction. This operation will be further described below with reference to subsequent figures.
  • Fig. 6 shows a serial bus configuration, wherein a master device and slave device of a first type (using the new protocol described herein) are connected to a serial bus 48 in common with a master and slave device of a second type (using the I 2 C-bus protocol).
  • a serial bus 48 comprising a clock wire SBCK, a start/ stop wire SBST, and a data wire SBDT.
  • Clock wire SBCK and data wire SBDT are each connected to a DC voltage V DD via a pull-up resistor R.
  • a first type master 100 comprising a master device utilizing a first serial bus interface protocol, is connected via separate terminals to each of clock wire SBCK, start/stop wire SBST, and data wire SBDT.
  • a first type slave 102 comprising a slave device utilizing the first serial bus interface protocol, is connected via respective terminals to clock wire SBCK, start/stop wire SBST and data wire SBDT.
  • First type master 100 and first type slave 102 may comprise master and slave devices as described above in reference to Fig. 5.
  • first type master 100 may comprise master SBI controller 56 and interaction circuits including clock wire interaction circuit 62, start/stop wire interaction circuit 64, and data wire interaction circuit 66.
  • First type slave 102 may comprise slave controller 58 and interaction circuits including clock wire interaction circuit 63a, start/stop wire interaction circuit 65a, and data wire interaction circuit 67a.
  • I 2 C master 104 and I 2 C slave 106 may comprise master and slave devices as described, for example, in the Philips Semiconductors document entitled "The I 2 C-bus and How to Use It (Including Specifications)" — 1995 update, pages 1-24 (April 1995), the content of which is hereby incorporated by reference herein in its entirety. In any event, I 2 C master 104 and I 2 C slave 106 may be constructed in any well known manner.
  • I 2 C master 104 comprises a first terminal connected to clock wire SBCK, and comprises a mechanism for controlling the signal level on clock wire SBCK in accordance with a desired clock signal.
  • the desired clock signal is used in common by I 2 C master 104 and I 2 C slave 106 to facilitate the synchronous operation of I 2 C master 104 and I 2 C slave 106 when a transaction is occurring between those two devices.
  • I 2 C master 104 further includes a second terminal connected to data wire SBDT and a transaction initiator (not shown) for initiating a transaction by providing a start indication on data wire SBDT in accordance with the I 2 C-bus protocol, which is described above with reference to Fig. 3.
  • I 2 C master 104 is further provided with a master data write mechanism (not shown) for controlling the signal level on data wire SBDT in accordance with data to be written to I 2 C slave 106. That data may include payload data and overhead data including information addressing I 2 C slave 106, in accordance with the I 2 C protocol.
  • first type master device 100 initiates a transaction by providing a start indication on a designated bus wire designated for the transmission of control information —including transaction start and stop indications.
  • the designed bus wire comprises a start/stop wire SBST, which is separate and distinct from clock wire SBCK and data wire SBDT.
  • First type master device 100 controls the signal level on data bus wire SDBT in accordance with data to be transferred to first type slave device 102. That data may include payload data and overhead data including information addressing the first type slave device 102 as well as one or more specific registers therein.
  • the signal level on clock wire SBCK is controlled by first type master device 100 in accordance with a desired clock signal being used in common by first type master device 100 and first type slave device 102 to facilitate synchronous operation of first type master device 100 and first type slave device 102.
  • First type master device 100 terminates a transaction by providing a stop indication on the designated bus wire (start /stop wire SBST) and maintaining that stop indication irrespective of the existence of any indications present on data and clock wires SBDT and SBCK. In the illustrated embodiment, this is done by maintaining the level of the start/stop wire SBST in a high state. Accordingly, first type master device 100 inhibits the control by first type master device 100 of the signal level on data wire SBDT to transfer data and inhibits the control by first type master device 100 of the signal level on clock wire SBCK for as long as the stop indication is provided and maintained.
  • I 2 C master device 104 initiates a transaction by providing an I 2 C start indication in accordance with the I 2 C protocol on data wire SBDT.
  • I 2 C master device 104 controls the signal level on data wire SBDT in accordance with data to be transferred to I 2 C slave device 106, and that data may include payload and overhead data including information addressing I 2 C slave 106, in accordance with the I 2 C-bus protocol.
  • I 2 C master device 104 controls the signal level on clock wire SBCK in accordance with a desired clock signal. The desired clock signal is used in common by I 2 C master device 104 and I 2 C slave device 106 to facilitate synchronous operation of the two devices during the transaction.
  • the transaction is terminated by I 2 C master 104 by providing a stop indication on data wire SBDT.
  • Fig. 7 shows a timing diagram illustrating an interrupt transfer mode message (ITM) format of the illustrated serial bus interface protocol.
  • ITM interrupt transfer mode message
  • the illustrated ITM transaction 110 includes a start indication 112, a transfer mode identifier 114, a slave address 116, an encoded message 118, a clock rest period 120, and a stop indication 122.
  • Start indication 112 triggers a first bit transmitted on data line SBDT, the first bit being latched on the second falling edge of the internal clock signal of the master device (such signal is not shown explicitly in Fig. 7) after the start/stop signal has gone low. Accordingly, the first bit of data is shown in Fig. 7 as starting at the start time 124. This is the transaction start time.
  • transfer mode identifier 114 comprises a pair of bits which are 00 indicating that the master device is initiating a transaction in an interrupt mode. Accordingly, the signal level on data wire SBDT is low for two clock cycles until a slave address start time 126 is reached which corresponds to a falling edge of clock signal SBCK. A one bit slave address 116 is then transmitted. Accordingly, only two receivers (which may comprise masters or slaves) can be addressed in the interrupt mode.
  • the interrupt transfer mode (ITM) is used to transfer only one byte of encoded information.
  • An ITM message may be used as a write-only message used by one master to signal an interrupt to another master.
  • the encoded message 118 comprises five transmitted data bits. Following encoded message 118, a clock rest period 120 is shown, after which a stop indication 122 is signaled on start- stop wire SBST.
  • a master device when more than one master device is connected to a serial bus, a master device will yield to another master device which is the first to transmit a zero on the data wire. Accordingly, an ITM transaction will take priority over other transactions, since the first two bits of information (transfer mode identifier 114) transmitted on data wire SBDT are zeros — i.e., low voltage levels, which preclude other master devices which are not transmitting two consecutive zeros as their initial bits fail to maintain the signal level on data wire SBDT in their intended state.
  • a master device 50 will control a signal level on data wire SBDT via a data operation terminal 84, and will simultaneously monitor the signal level on data wire SBDT via a data monitoring terminal 82.
  • the signal level on data wire SBDT does not correspond to the intended signal level per the operation of data operation terminal 84 in connection with field effect transistor 74
  • master controller 56 of master device 50 will release the bus. Accordingly, a master transmitting a zero always wins an arbitration over a master transmitting a one. For this reason, an ITM transaction is appropriate for one master device to interrupt another master device or to otherwise supersede another master device's control over the serial bus.
  • FIG. 8 shows a transaction and corresponding waveforms corresponding to a fast transfer mode (FTM) transaction.
  • An FTM transaction 134 is illustrated which comprises five bytes of transmitted information. Specifically, the illustrated FTM transaction 134 starts upon the occurrence of a start indication 136 which is followed by an initial two bits of information ("01") transmitted on data wire SBDT, i.e., transfer mode identifier 138, followed by a six bit slave address 140 which completes the first byte of transmitted information.
  • a first clock rest period 141a then follows.
  • the second transmitted byte includes an initial R/W (read/write) bit 142 followed by a seven bit register address 144.
  • a second clock rest period 141b then separates another byte of information transmitted via data wire SBDT.
  • the first set of information transmitted between the transmitter and the receiver comprises a first byte of data 146.
  • This data may be sent from the master device (serving as transmitter) to the slave device (serving as receiver) or transferred from the slave device (serving as transmitter) to the master device (serving as receiver) depending upon the state of the previously transmitted read /write bit 142.
  • a second read /write bit 147 is then transmitted by the master device as an initial bit followed by a register address 148 to which data is to be forwarded or from which data is to be retrieved.
  • the slave device will drive the data wire SBDT during the following byte of data 150, which will commence upon completion of another clock rest period 141d. Near the end of the transmission, a final clock rest period 141e will occur, and the transaction will end upon a stop indication being signaled by the master device on start/stop wire SBST.
  • FTM transactions are intended for data transfer to and from slave devices which may not support the other transfer modes. Transmissions to such slave devices are of moderate priority, and are thus preceded by a transfer mode identifier of "01". In this mode, data may be both read to and written from the slave device within the same transaction.
  • Fig. 9 shows a bulk transfer mode (BTM) transaction together with the signals on each of the clock, start/stop and data wires.
  • the illustrated BTM transaction 160 commences with a start indication 162 followed by a 2 bit transfer mode identifier 164 and a slave address 166.
  • the information transmitted in the illustrated BTM transaction 160 includes many bytes.
  • the second byte, transmitted following a first clock rest period 169a, includes a read/write bit 167 followed by a seven-bit register address 168.
  • the third byte of data 170 is then transmitted following a second clock rest period 169b. All remaining bytes are transferred in a similar fashion until the master asserts the SBST line, indicating the end of the transaction.
  • the number of data bytes transferred only depends on the time limit of the protocol.
  • a final clock rest period 169d then occurs followed by a stop indication placed on start/stop wire SBST.
  • the first and second bytes (and subsequent bytes) of data 170, 172 may be either written to a particular register of a slave device, or may be read from a particular register of a slave device, in accordance with the value placed within the read /write bit 167. More specifically, in the illustrated embodiment, when the read /write bit 167 is clear, i.e., the level of the signal on data wire SBDT is low, the master device is writing data to the slave device. When the read /write bit 167 is set, i.e., the signal level on data wire SBDT is high, the master device is reading data from the slave device.
  • the master device When the master device wants to read data following a particular register address byte, it accordingly releases the data wire SBDT after the edge of the signal on clock wire SBCK which immediately follows the last bit transferred within the register address 168. Following each of the second and third clock rest periods 169b and 169c, the slave device then transmits the data. The master device continues to control the signal level on clock wire SBCK. The signal level on start/stop wire SBST remains low throughout the transaction.
  • the register address is a 7-bit field. This allows the addressing of up to 128 registers in a slave.
  • the slave In a bulk transfer mode the slave generates its own register addresses and therefore unlimited number of register addresses can be generated internal to the slave.
  • the master SBI controller of each master device may be configured to have two operating modes, including a functional mode and a test mode.
  • the master device will only keep control of the bus for a limited time.
  • the master device provides a stop indication on the designated clock wire SBCK when a threshold indicative of the length of the transaction has been reached.
  • that threshold is an amount of data transferred, i.e., when thirty two bytes have been transferred.
  • the test mode the master device will be permitted unlimited data transfer. By limiting the amount of bytes transferable within a given transaction governed by a single master, this will allow other master devices to share the use of the serial bus.
  • SBST, SBDT, and SBCK must all be high for at least one clock period (which would be 600ns should the clock rate be 1.53MHz) before a new transaction can begin. If any one of the three wires is low, a master cannot initiate a new transaction and must wait for all three signal levels to remain high for one clock period.
  • MSB most significant bit
  • LSB last significant bit
  • a master releases its transmission on the serial bus if the data it transmits does not appear on the bus.
  • the master transmitting a zero will always win an arbitration over a master transmitting a one.
  • this rule facilitates inter-master arbitration, and also facilitates the assignment of priorities to certain receivers and to certain types of modes of transfer, for example, as described above with respect to the interrupt mode, fast transfer mode, and bulk transfer mode.
  • the interrupt transfer mode starts a transaction by transmitting two zeros on data wire SBDT, while the fast transfer mode starts a transaction by transmitting a zero followed by a one on data wire SBDT.
  • a bulk transfer mode starts the transmission by transmitting a one followed by a zero on data wire SBDT. Accordingly, they are given priority in precisely that order by the master devices which may be concurrently attempting to gain control of the serial data bus.
  • Data transmission can be terminated at any time by taking a signal level at the start/stop wire SBST high.
  • Slave devices and master devices should be provided with mechanisms for recovering from this condition.
  • No master device or slave device can drive the data wire SBDT during a clock spacer time.
  • Fig. 10 is a block diagram further illustrating an exemplary master device 178 which may be coupled to the illustrated serial bus 48, for example, as shown in Fig. 5.
  • the master device 178 as shown in Fig. 10 comprises a master serial bus interface (SBI) 180 which comprises a master SBI controller 181, a parallel processor interface 183, and a serial interface 185.
  • SBI master serial bus interface
  • Parallel processor interface 183 links master SBI controller 181 to a master device processor 182.
  • Serial interface 185 links master SBI controller 181 to a serial bus — i.e., serial bus 48 as shown in Fig. 5.
  • serial interface 185 comprises a clock wire interaction circuit 188, a start/stop wire interaction circuit 190, and a data wire interaction circuit 192.
  • Each of these interaction circuits may be constructed as described above with respect to the master device 50 as shown in Fig. 5.
  • Parallel processor interface 183 comprises a primary interface 184 which in the illustrated embodiment includes a sixteen bit bi-directional data bus, and a secondary interface 186 provided for other connections between master device processor 182 and master SBI controller 181.
  • Master SBI controller 181 implements a serial link interface between master device processor 182 and the various slave devices which may be connected to the serial bus. Master SBI controller 181 may accordingly allow master device processor 182 to interact with the slave devices, for example, initializing, configuring, and selectively powering up specific functions of such slave devices. Master SBI controller 181 will further facilitate the ability of master device 182 to monitor the operation of the slave devices.
  • Parallel processor interface 183 may comprise any known microprocessor parallel interface that is either commercially available or constructed using techniques well known in the art.
  • Master SBI controller 181 receives data from a parallel processor 183, and serializes addresses and data using a serial interface 185 comprising three pins, thereby implementing the serial bus interface protocol as described herein.
  • parallel processor interface 183 comprises a primary interface 184 and a secondary interface 186.
  • Primary interface 184 comprises a 16-bit bi-directional data bus which allows the transfer of pairs of assembled 8- bit SBI addresses and 8-bit data for transmission to and from slave devices connected to the serial bus.
  • Master device processor 182 will have to address master SBI controller 181 periodically e.g., once every NSBI clock cycles to replenish a buffer provided within master SBI controller 181 with new address pairs for transmission to the appropriate slave devices.
  • Fig. 11 illustrates master SBI controller 181 in further detail.
  • the illustrated master SBI controller 181 may comprise (among other elements, not specifically shown to simplify the explanation herein) a processor interface 194 coupled to a divider 196 and a data path block 198.
  • Processor interface 194 receives at one side parallel processor 183.
  • Data path block 198 interfaces with the serial bus via serial bus I/O pins 200.
  • parallel processor interface 183 comprises a plurality of parallel connections and control pins, among others, a micro_ reset input pin 202 and a clock CLK input pin 204.
  • Micro_reset pin 202 is an input pin of processor interface 194 which allows the master device processor to reset master SBI controller 181.
  • Clock pin CLK 204 comprises an input pin receiving a two-phase clock input from master device processor 182.
  • the remaining data pin connections 206 comprise remaining pins of secondary processor connection 186 as well as of the primary interface 184 as shown in Fig. 10.
  • Processor interface 194 comprises several internal connections including a write enable connection WR_EN 208, a write data connection WR_DATA 210, a write address connection WR_ADDR 212, and a read data connection RD_DATA 214.
  • Read data connection 214 is an input to processor interface 194, and the other connections 208, 210, and 212 are outputs. They are coupled, via internal buses of master SBI controller 181, to divider 196 and data path block 198.
  • the illustrated divider 196 comprises an internal bus connection 208 and a clock "CLK" input pin 210. It further comprises a first output 210 for outputting a serial bus clock signal MSBI_SBCK, and a second output 212 for outputting a master SBI controller enable signal MSBI_EN.
  • Data path device 198 has an internal bus connection 215 at one side thereof, and comprises a plurality of serial bus I/O interfacing pins 200 at an opposite side.
  • Serial bus I/O interfacing pins 200 may comprise (among other pins not specifically shown for the sake of simplicity), a clock wire operation terminal 218, a start/stop operation terminal 220, a data monitoring terminal 222, and a data operation terminal 224.
  • Processor interface 194 asynchronously interfaces master SBI controller 181 to a processor bus while retaining synchronous operation for register reads and writes in master SBI controller 181.
  • Divider block 196 subdivides a main CLK clock input, received at clock input 210, to produce a serial shift clock and appropriate enables for the operation of master SBI controller 181.
  • Divider 196 may be provided with a mechanism for allowing serial operation with clock rates in a range of, for example, 1.5MHz down to 100 KHz.
  • the illustrated divider 196 would facilitate such a range of clock rates and would enable master SBI controller 181 to function at clock rates defined with a resolution of 1/M sub- multiples of the main clock input CLK, with duty cycles of 40-50%.
  • Fig. 12 is a block diagram of a data path block 228 in further detail. Various details and specific elements that may form part of data path block 228 are omitted for purposes of simplifying the description herein.
  • the illustrated data path block 228 comprises a plurality of write registers 238, a plurality of read registers 240, a multiplexer 242, and a central shift register 244.
  • Data path block 228 further includes an SBI control register 246, a start control register 248, and an output portion 250.
  • Plural write registers 238 comprise a write register 230 and a working buffer 232.
  • Write register 230 comprises a one-byte register address portion 234a and a one-byte register data portion 234b.
  • Register address and register data portions 234a and 234b comprise outputs respectively connected to a register address portion 236a and a register data portion 236b of working buffer 232.
  • Working buffer 232 comprises a working buffer enable input 233 for receiving an enable signal.
  • Each of the register address and register data portions 236a and 236b of working buffer 232 comprises an output which is input to a multiplexer 242.
  • Multiplexer 242 further comprises a serial register selection input 243 receiving a serial register selection signal.
  • Multiplexer 242 also receives a slave ID from SBI control register 246.
  • SBI start control register 248 comprises an output which is coupled to a control word input of SBI control register 246.
  • Plural read registers 240 comprises a register address portion 252 and an
  • Read registers 240 further comprises a read register enable input 256 receiving a read register enable signal.
  • Shift register 244 comprises a data input terminal 258 which corresponds to data monitoring terminal 222 of data path device 198 as shown in Fig. 11.
  • Shift register 244 further comprises a shift register enable input 260 for receiving a shift register enable signal.
  • Shift register 244 comprises an output directed to the input side of an output multiplexer 262 which forms part of output portion 250.
  • Output multiplexer 262 comprises a clock output terminal 264 which corresponds to clock wire operation terminal 218 as shown in Fig. 11, a start/stop output terminal 266 which corresponds to start/stop operation terminal 220, and a data output terminal 268 which corresponds to data operation terminal 224, as shown in Fig. 11.
  • Fig. 13 is a flowchart which illustrates certain operations performed by data path block 228 and other components of master SBI controller 181 in performing a multi-word transaction with a slave device through a serial bus as disclosed in the illustrated embodiment.
  • the controller will write to a clock control register provided in divider 196 in order to pick a desired divide ratio.
  • step S4 the controller will write to SBI control register 246.
  • the appropriate mode of operation of the controller will be chosen by writing the desired slave ID (SLV_ID) and serial bus protocol mode bits in SBI control register 246.
  • the controller will write to write register 230 (SBI_WR) the address and data to be transferred to a particular slave device.
  • step S8 the controller, when ready to start the transaction, will write to bit zero of the SBI start control register 248 to set the start_flag to the number 1.
  • step S10 the controller will first transfer the serial transfer mode bits and slave ID bits, and then transfer the contents of write register 230 to its working buffer 232. The controller will then assert its interrupt to let master device processor 182 know that the write register 230 is empty.
  • step S12 the controller will serialize bits [15:8] and then bits [7:0] of working register 232.
  • step S14 a determination is made as to whether write register 230 has been re-written. If write register 230 has been re-written, the process will return to step S10, at which point the data will be transferred to working buffer 232 and an interrupt will be sent to master device processor 182. If a determination is made at step S14 that write register 230 has not been written to, the transaction is terminated at step S16. Controller 181 may be provided with a status register which gives a complete picture of the state of the controller with one read operation. Such a register would be readable by master device processor 182.
  • Fig 11 is a block diagram illustrating a slave device 270.
  • the illustrated device 270 comprises a slave SBI controller 272 coupled to a read /write register 274 and a read register 276 by a bus structure 278.
  • a serial interface is provided at the front end of slave SBI controller 272 which comprises a data wire interaction circuit 280, a clock wire interaction circuit 282, and a start/stop interaction circuit 284.
  • the illustrated slave 272 more specifically comprises a bi-directional 7-bit parallel databus connection 286 coupled to a 7-bit parallel bus 287, a 5-bit parallel address bus connection 288 coupled to an address bus 289, a write clock pin 290 coupled to a write clock bus (wire) 291, and a read enable pin 292 coupled to a read enable bus (wire) 293.
  • a master device e.g., the master device 178 shown in Fig. 10
  • master device processor 182 will instruct master SBI controller 181 to perform a write transaction, and will transfer the data to be written via primary interface 184 to master SBI controller 181.
  • Master SBI controller 181 will then control the serialization process, first signaling a start indication on start/stop wire SBST via start/stop interaction circuit 190.
  • Slave SBI controller 272 of slave device 270 will be in a ready state listening for such a start indication via start/stop interaction circuit 284.
  • Slave SBI controller 272 will receive the clock signal via its clock interaction circuit 282.
  • the transmitted data is received through data interaction circuit 280.

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  • General Physics & Mathematics (AREA)
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Abstract

L'invention concerne un protocole de bus en série entre dispositifs qui facilite l'interconnexion et la communication entre plusieurs dispositifs via un bus en série. Le bus (48) comprend une connexion d'horloge, une connexion de données et une connexion marche/arrêt. Une interface de bus en série principale raccorde un dispositif principal au bus en série. Une interface de bus en série asservie raccorde un dispositif asservi au bus en série. L'interface (180) de bus en série principale peut comprendre un initiateur de transaction, un mécanisme d'écriture de données, un mécanisme de lecture de données et une commande d'horloge. L'initiateur de transaction initie une transaction en abaissant le niveau du signal de la connexion marche/arrêt. Le mécanisme d'écriture de données commande le niveau du signal dans la connexion de données en fonction des données à inscrire dans le dispositif asservi. Le mécanisme de lecture de données lit des données en contrôlant le niveau de signal dans la connexion de données. La commande d'horloge commande le niveau de signal dans la connexion d'horloge en fonction d'un signal d'horloge voulu.
PCT/US1999/014696 1998-07-01 1999-06-30 Protocole ameliore de bus en serie entre dispositifs WO2000002134A2 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
CA002336385A CA2336385A1 (fr) 1998-07-01 1999-06-30 Protocole ameliore de bus en serie entre dispositifs
JP2000558463A JP2003534580A (ja) 1998-07-01 1999-06-30 改善された装置間シリアルバスプロトコル
BR9911732-0A BR9911732A (pt) 1998-07-01 1999-06-30 Protocolo aperfeiçoado para barramento serial entre dispositivos
IL14056899A IL140568A0 (en) 1998-07-01 1999-06-30 Improved inter-device serial bus protocol
KR1020017000012A KR20010053365A (ko) 1998-07-01 1999-06-30 디바이스간 직렬 버스 프로토콜
EP99932038A EP1145132A3 (fr) 1998-07-01 1999-06-30 Protocole ameliore de bus en serie entre dispositifs
AU48432/99A AU4843299A (en) 1998-07-01 1999-06-30 Improved inter-device serial bus protocol
NO20006698A NO20006698L (no) 1998-07-01 2000-12-29 Protokoll for seriell databuss mellom enheter

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US9138398P 1998-07-01 1998-07-01
US60/091,383 1998-07-01
US24893999A 1999-02-11 1999-02-11
US09/248,939 1999-02-11

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WO2000002134A2 true WO2000002134A2 (fr) 2000-01-13
WO2000002134A3 WO2000002134A3 (fr) 2001-09-27

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JP (1) JP2003534580A (fr)
KR (1) KR20010053365A (fr)
AU (1) AU4843299A (fr)
BR (1) BR9911732A (fr)
CA (1) CA2336385A1 (fr)
IL (1) IL140568A0 (fr)
NO (1) NO20006698L (fr)
WO (1) WO2000002134A2 (fr)

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FR2828947A1 (fr) * 2001-08-27 2003-02-28 Pierre Trazic Fonctions out et in de connection sur un bus uce
WO2003060737A1 (fr) * 2001-12-28 2003-07-24 Koninklijke Philips Electronics N.V. Système de communication
WO2005114436A1 (fr) * 2004-05-20 2005-12-01 Qualcomm Incorporated Interoperabilite entre bus unifilaires et trifilaires
US7342310B2 (en) 2004-05-07 2008-03-11 Avago Technologies General Ip Pte Ltd Multi-chip package with high-speed serial communications between semiconductor die
DE102005007333B4 (de) * 2004-05-07 2008-07-03 Avago Technologies General Ip (Singapore) Pte. Ltd. Mehrchip-Gehäuse mit seriellen Hochgeschwindigkeitskommunikationen zwischen Halbleiterformen
JP2009010959A (ja) * 2001-02-16 2009-01-15 Qualcomm Inc ダイレクトコンバート受信機アーキテクチャ
KR100910446B1 (ko) 2007-12-03 2009-08-04 주식회사 동부하이텍 디스플레이 장치용 ｉ２ｃ 타임 콘트롤러의 데이터 동기화구현 회로 및 방법
US8750324B2 (en) 2004-05-20 2014-06-10 Qualcomm Incorporated Single wire bus interface
WO2015120339A1 (fr) * 2014-02-07 2015-08-13 Bayer Healthcare Llc Méthodes et appareil pour un protocole de bus à multiples maîtres
US9300129B2 (en) 2013-03-12 2016-03-29 Ascensia Diabetes Care Holding Ag Reverse battery protection for battery-powered devices
US9734121B2 (en) 2014-04-28 2017-08-15 Qualcomm Incorporated Sensors global bus
IT201800002767A1 (it) * 2018-02-16 2019-08-16 St Microelectronics Srl Circuito per il pilotaggio di led, dispositivo e procedimento corrispondenti
US10417172B2 (en) 2014-04-28 2019-09-17 Qualcomm Incorporated Sensors global bus

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JP4831899B2 (ja) * 2001-08-28 2011-12-07 富士通セミコンダクター株式会社 半導体集積回路及びクロック制御方法
KR100698303B1 (ko) * 2005-03-21 2007-03-22 엘지전자 주식회사 직렬 버스 디렉션 컨트롤러
WO2011056729A2 (fr) * 2009-11-05 2011-05-12 Rambus Inc. Gestion d'horloge d'interface

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EP0629063A1 (fr) * 1993-05-21 1994-12-14 Nortel Networks Corporation Système bus sériel

Cited By (28)

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JP2009010959A (ja) * 2001-02-16 2009-01-15 Qualcomm Inc ダイレクトコンバート受信機アーキテクチャ
EP2267888A2 (fr) * 2001-02-16 2010-12-29 Qualcomm Incorporated Architecture de récepteur de conversion directe
EP2273674A2 (fr) * 2001-02-16 2011-01-12 Qualcomm Incorporated Architecture de récepteur de conversion directe
FR2828947A1 (fr) * 2001-08-27 2003-02-28 Pierre Trazic Fonctions out et in de connection sur un bus uce
WO2003019401A1 (fr) * 2001-08-27 2003-03-06 Pierre Trazic Unite centrale eclatee
WO2003060737A1 (fr) * 2001-12-28 2003-07-24 Koninklijke Philips Electronics N.V. Système de communication
US7342310B2 (en) 2004-05-07 2008-03-11 Avago Technologies General Ip Pte Ltd Multi-chip package with high-speed serial communications between semiconductor die
DE102005007333B4 (de) * 2004-05-07 2008-07-03 Avago Technologies General Ip (Singapore) Pte. Ltd. Mehrchip-Gehäuse mit seriellen Hochgeschwindigkeitskommunikationen zwischen Halbleiterformen
US7537960B2 (en) 2004-05-07 2009-05-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Method of making multi-chip package with high-speed serial communications between semiconductor dice
WO2005114436A1 (fr) * 2004-05-20 2005-12-01 Qualcomm Incorporated Interoperabilite entre bus unifilaires et trifilaires
US8750324B2 (en) 2004-05-20 2014-06-10 Qualcomm Incorporated Single wire bus interface
KR100910446B1 (ko) 2007-12-03 2009-08-04 주식회사 동부하이텍 디스플레이 장치용 ｉ２ｃ 타임 콘트롤러의 데이터 동기화구현 회로 및 방법
US9673612B2 (en) 2013-03-12 2017-06-06 Ascensia Diabetes Care Holdings Ag Reverse battery protection for battery-powered devices
US9300129B2 (en) 2013-03-12 2016-03-29 Ascensia Diabetes Care Holding Ag Reverse battery protection for battery-powered devices
TWI636367B (zh) * 2014-02-07 2018-09-21 瑞士商安晟信醫療科技控股公司 用於多個主機匯流排協定的方法與裝置
WO2015120339A1 (fr) * 2014-02-07 2015-08-13 Bayer Healthcare Llc Méthodes et appareil pour un protocole de bus à multiples maîtres
US10204065B2 (en) 2014-02-07 2019-02-12 Ascensia Diabetes Care Holdings Ag Methods and apparatus for a multiple master bus protocol
US10417172B2 (en) 2014-04-28 2019-09-17 Qualcomm Incorporated Sensors global bus
US9921998B2 (en) 2014-04-28 2018-03-20 Qualcomm Incorporated Sensors global bus
US9734121B2 (en) 2014-04-28 2017-08-15 Qualcomm Incorporated Sensors global bus
US10452603B2 (en) 2014-04-28 2019-10-22 Qualcomm Incorporated Sensors global bus
US10482057B2 (en) 2014-04-28 2019-11-19 Qualcomm Incorporated Multi-protocol dynamic address allocation
IT201800002767A1 (it) * 2018-02-16 2019-08-16 St Microelectronics Srl Circuito per il pilotaggio di led, dispositivo e procedimento corrispondenti
EP3528387A1 (fr) * 2018-02-16 2019-08-21 STMicroelectronics Srl Circuit d'attaque de del, dispositif et procédé correspondants
CN110167228A (zh) * 2018-02-16 2019-08-23 意法半导体股份有限公司 Led驱动器电路、对应的设备和方法
US10757779B2 (en) 2018-02-16 2020-08-25 Stmicroelectronics S.R.L. LED driver circuit, corresponding device and method
CN110167228B (zh) * 2018-02-16 2021-07-16 意法半导体股份有限公司 Led驱动器电路、对应的设备和方法
US11271555B2 (en) 2018-02-16 2022-03-08 Stmicroelectronics S.R.L. LED driver circuit, corresponding device and method

Also Published As

Publication number Publication date
IL140568A0 (en) 2002-02-10
BR9911732A (pt) 2002-01-29
JP2003534580A (ja) 2003-11-18
AU4843299A (en) 2000-01-24
CA2336385A1 (fr) 2000-01-13
EP1145132A2 (fr) 2001-10-17
NO20006698L (no) 2001-02-20
EP1145132A3 (fr) 2002-08-21
WO2000002134A3 (fr) 2001-09-27
NO20006698D0 (no) 2000-12-29
KR20010053365A (ko) 2001-06-25

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