Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W99/00—Subject matter not provided for in other groups of this subclass
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/01—Manufacture or treatment
  • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
  • H10W70/097—Cleaning

Definitions

• This invention relates generally to a method of assembly of a semiconductor device in a flip chip configuration. More specifically this invention relates to a method of applying flux to the substrate in a semiconductor device in a flip chip configuration. Even more specifically this invention relates to an automated method of applying flux in a controlled amount to the substrate in a semiconductor device via a brush during a programmed pattern of strokes.
• Flip chip technology is defined as mounting the semiconductor chip to a substrate with any kind of interconnect materials and methods such as fluxless solder bumps, tape- automated bonding (TAB), wire interconnects, conductive polymers, anisotropic conductive adhesives, metallurgy bumps, compliant bumps, and pressure contacts as long as the active chip surface is facing the substrate.
• interconnect materials and methods such as fluxless solder bumps, tape- automated bonding (TAB), wire interconnects, conductive polymers, anisotropic conductive adhesives, metallurgy bumps, compliant bumps, and pressure contacts as long as the active chip surface is facing the substrate.
• the flip chip interconnects are being used in the semiconductor industry primarily because of their high I/O density capability, small profiles, and good electrical performance. Demands on performance, reliability, and cost have resulted in the development of a variety of flip chip technologies using solder, conductive epoxy, hard metal bump (such as gold) and anisotropic conductive epoxy interconnects. Among these materials, solders have remained a preferred choice as the material forming electrical connections in flip chip assemblies.
• Solder flip chip interconnect systems consist of essentially three basic elements. These include the chip, the solder bump, and the substrate. The bumps are first deposited on a wafer and reflowed. The wafer is then diced into chips. The chips are flipped over, aligned to a substrate, tacked, and reflowed. An underfill may be used to improve the reliability of the interconnects.
• Each of these elements and the processes used to assemble them together affect the performance and the cost of the interconnect system. Therefore, the performance and cost must be compared on the basis of the interconnect system as a whole, and not merely on any single element of the interconnect assembly.
• the materials and processes involved in the manufacture of the flip chip interconnect system determine its performance.
• the semiconductor device or the chip may be silicon or gallium arsenide.
• the bond pad metallization on the wafer can be Ni-Au, Cr-Cu-Au, TiW-Cu, Ti-Cu, or Ti W-Au.
• the bump material can be one of a variety of Pb-based or Pb-free solders.
• the substrate can be silicon, alumina, glass, or one of a variety of organic substrates.
• the substrate metallization can be gold or copper. Underfills are used primarily to improve reliability of flip chip interconnect systems. These materials fill the gap between the chip and substrate around the solder joints, reducing the thermal stresses imposed on the solder joint.
• the process step used in the manufacture of the interconnect systems can be varied and include process technologies such as plating, evaporation, wire bumping, dispensing, and printing.
• the reflow process may be performed in air with flux or in a controlled ambient.
• Flip chip bonding processes include those based on the controlled-collapse chip connection (C4) approach or those in which the geometry of the bump is controlled by the bonding equipment.
• C4 controlled-collapse chip connection
• the cost of manufacturing a solder flip chip interconnect system is related to the manufacturing process technologies. Some basic elements of a cost model are the materials cost, number of process steps, equipment costs, floor space, and labor. The number of process steps has a significant influence on the cost, since they also affect equipment costs, floor space, and labor. A smaller number of process steps invariably results in lower costs. A significant reduction in cost is also achieved when a manual process step that requires an interruption of the process flow can be replaced by an automated process step.
• a sticky flux is applied to the substrate and the bumps.
• This flux provides the adhesion needed to hold the chips in place until the reflow process takes place.
• the methods available to apply flux to the substrate include manually brushing the flux onto the substrate, die dip fluxing or spraying the flux onto the substrate.
• the quality of the process of manually brushing the flux onto the substrate is dependent upon the training of the person doing the brushing, the time of day (how long the person has been working) etc. For example, if the flux is not put on in sufficient thickness the bumps or pads may not be covered.
• the die will float off of the substrate during reflow due to the boiling action of the flux.
• the quality of the process of spraying the flux onto the substrate depends upon the material of the substrate. Different substrate materials/flux materials have different surface tensions that cause the flux materials to bead. The beading of the flux material has a serious deleterious effect of the quality of the interconnect assembly.
• an automated method of applying flux to a substrate on which a semiconductor chip is to be assembled in a flip chip configuration A controlled amount of flux is applied to the substrate by a brush that applies the flux to the substrate in a programmed pattern of strokes.
• the brush is attached to a movable mechanical stage that is controlled by a program in a CPU.
• the program in the CPU is an empirically determined program determined for the specific combination of substrate and chip being assembled. The empirically determined program is based upon uniformity of flux coverage of bumps on the specific semiconductor device being assembled and an optimization of manufacturing throughput of the specific semiconductor device being assembled.
• the CPU controls the motion of the brush in three dimensions.
• the brush is caused to contact the substrate with an initial force and then is caused to back off until a programmed height above the substrate is achieved before the programmed pattern of strokes is begun.
• the automated programmed mechanical application method thus applies a controlled amount of flux to the substrate to achieve a desired uniform thickness by overcoming the surface tension of the flux/substrate interface.
• the empirically determined automated programmed mechanical application for each substrate/chip/flux combination is thus repeatable and operator independent.
• Figure 1 is a flow diagram showing a prior art method of attaching a chip face down on a substrate package
• Figure 2 is a flow diagram showing a method of attaching a chip face down on a substrate package in accordance with the present invention
• Figure 3A is a plan view of four substrate packages on a boat ready to have flux applied to a region on the substrate packages having bumps;
• Figure 4 A is a side view of the four substrate packages shown in Figure 3 A showing flux being brushed onto one of the four packages and a chip ready to be applied to one of the four packages.
• Figure 1 is a flow diagram showing a prior art method of assembling a chip and a substrate in a flip chip configuration.
• Figure 1 shows a substrate, indicated at 100 that has been formed by standard methods in the semiconductor manufacturing art.
• the substrate could be silicon, alumina (ceramic), glass, or one of a variety of organic substrates. Bond pads or solder bumps are formed on the substrate that will be electrically connected to corresponding structures on a die.
• Flux is applied to the substrate as indicated at 102 by manually brushing or spraying the flux onto the appropriate portion of the substrate or by dipping the die into the flux.
• a major quality issue is present at the manual application step because the quality of the applied flux varies as to the person that brushes on the flux.
• the die indicated at 104 is a normal die and can be made on a silicon substrate or a gallium arsenide substrate. Bond pads or solder bumps are formed on the die and correspond to the bond pads or bumps formed on the substrate as discussed above.
• the bump material can be a variety of Pb-based or Pb-free solders.
• the bond pad metallization of the wafer can be Ni-Au, Cr-Cu- Au, TiW-Cu, Ti-Cu, or TiW-Au.
• the die is placed on the substrate in a flip chip configuration as indicated at 106.
• a flip chip configuration is one in which the active surface area is placed "face-down" onto the substrate.
• the substrate/chip combination is then heated to cause the solder to reflow as indicated at 108.
• the substrate/chip combination is cleaned as indicated at 110 and subjected to normal manufacturing steps as indicated at 112. The reflow, cleaning and remaining steps are standard in the semiconductor packaging art and will not be further discussed.
• Figure 2 is a flow diagram showing the method of assembling a chip and a substrate in a flip chip configuration in accordance with the present invention.
• Figure 2 shows a substrate, indicated at 200 that has been formed by standard methods in the semiconductor manufacturing art.
• the substrate could be silicon, alumina (ceramic), glass, or one of a variety of organic substrates.
• the flux is applied to the substrate as indicated at 202 by an automated process by mechanically brushing on the flux in a programmed pattern of brush strokes. The details of the programmed automated mechanical application of flux will be discussed below in conjunction with Figure 3B.
• the programmed automated mechanical application of flux to the substrate solves the problems encountered with the manual application of flux or the application of flux by spraying discussed above in conjunction with Figure 1.
• the programmed automated mechanical application of flux provides a uniform layer of flux on the substrate and bumps. The quality of the application is consistent from one substrate to the next.
• the programmed automated mechanical application of flux by brush avoids the beading problem caused by some of the different surface tensions caused by the interaction of different substrate materials and the flux.
• the programmed automated mechanical application of flux is achieved by a programmed pattern of brush strokes that has been empirically determined for the specific substrate and chip being assembled.
• An additional advantage is that the assembly system can be quickly reprogrammed if it is desired to assemble a different substrate/chip combination.
• the die (chip) as indicated at 204 can be made on a silicon substrate or gallium arsenide substrate. Interconnects on the die can be either bumps or pads.
• the bump material can be a variety of Pb-based or Pb-free solders.
• the bond pad metallization of the wafer can be Cr-Cu-Au, TiW- Cu, Ti-Cu, or TiW-Au.
• the die is placed on the substrate in a flip chip configuration as indicated at 206.
• a flip chip configuration is one in which the active surface area is placed "face-down" onto the substrate.
• the substrate/chip combination is then heated to cause the solder to reflow as indicated at 208.
• the substrate/chip combination is cleaned as indicated at 210 and subjected to normal manufacturing steps as indicated at 212. The reflow, cleaning and remaining steps are standard in the semiconductor packaging art and will not be further discussed.
• Figure 3A is a plan view of four substrate structures 300, 302, 304 and 306 mounted on a carrier or boat 308 that moves in the direction of the arrow 310. It is noted that the substrate structures 300, 302, 304 and 306 are identical. The dots, some of which are indicated at 310, represent the pads on the substrate material 312. The dashed lines 314 are the boundaries of the region on the substrate on which flux will be applied. The rectangular structures, some of which are indicated at 316, are capacitor pads formed on the substrate.
• Figure 3B is a side view of the four substrate structures 300, 302, 304 and
• a flux application structure is shown at 318.
• a CPU (central processing unit) 320 controls the mechanical stage 322 and the amount of flux that is dispensed via a valve from the flux reservoir 324.
• the mechanical stage 322 has a brush 326 structurally attached thereto and moves the brush in the x, y, and z directions as indicated at 328.
• the z direction is up and down from the surface of the substrate as indicated at 330.
• the x direction is in the direction of the movement of the carrier as indicated at 332.
• the y direction is in and out of the plane of the paper as indicated at 334.
• the flux is dispensed by a
• the CPU 320 controls the movement of the brush 326 via the mechanical stage 322 and the amount of flux that is dispensed from the flux reservoir 324 by a program that is empirically determined for the specific substrate and chip that are being assembled.
• the empirically generated program determines the pattern of the brush strokes that is required to achieve a uniform layer of flux to the regions 314 and the amount of flux that is required to be dispensed onto the surface to achieve the uniform layer of flux.
• the layer of flux is indicated at 340.
• a semiconductor chip 342 is shown in position to be placed on the substrate.
• the empirically generated program determines the initial downward distance that the brush 326 travels toward the surface of the substrate, determines the distance that the brush 326 backs off of the surface of the substrate and determines the force that needs to be applied to the brush to hold it at the desired distance from the surface of the substrate.
• the empirically generated program can be determined using one of a number of available fluxes that are generally available commercially.
• the two major criteria used to determine the empirically generated program is uniformity of the flux coverage, thickness and the optimization of the throughput of the process. Different programs can be determined for different fluxes.
• the flux materials are generally available from Alpha Metals, Indium Corporation, Kester and other manufacturers.
• a major advantage of having a program for each substrate/chip combination/flux is that the assembly system can be quickly changed from one substrate/chip/flux combination to another substrate/chip/flux combination.
• the results and advantages of the automated programmed mechanical application method thus applies a controlled amount of flux to the substrate to achieve a desired uniform thickness by overcoming the surface tension

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• Wire Bonding (AREA)
• Electric Connection Of Electric Components To Printed Circuits (AREA)

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• 1998
  • 1998-03-17 US US09/040,511 patent/US6098867A/en not_active Expired - Lifetime
• 1999
  • 1999-03-17 WO PCT/US1999/005924 patent/WO1999048141A1/en not_active Ceased
  • 1999-03-17 EP EP99912664A patent/EP1064677A1/en not_active Ceased
  • 1999-03-17 JP JP2000537254A patent/JP2002507836A/ja active Pending
  • 1999-03-17 KR KR10-2000-7010253A patent/KR100529746B1/ko not_active Expired - Fee Related

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