Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
  • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
  • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
  • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
  • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
  • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
  • H10P76/2041—Photolithographic processes
  • H10P76/2043—Photolithographic processes using an anti-reflective coating

Definitions

• the present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of etching inorganic antireflective coatings (also referred to as Dielectric Antireflective Coatings or DARCs) without etching excessive amounts of the underlying oxide layer.
• inorganic antireflective coatings also referred to as Dielectric Antireflective Coatings or DARCs
• Inorganic antireflective coatings are used to counteract the overexposure which can occur with structures that reflect exposure light.
• FIG. 1 there is shown a partially completed integrated circuit.
• Field oxide regions 11 have been formed in and on a semiconductor substrate 10.
• Polysilicon or polycide gate electrodes 14 have been formed.
• a dielectric layer 16 covers the gate electrodes.
• An oxide layer 20, typically borophosphosilicate glass (BPSG) is grown over the dielectric layer 16.
• a layer of photoresist is coated over the oxide layer 20 and patterned to form a mask. Because of the reflective surface of the oxide layer 20 and the intensity of the deep ultraviolet light 22 used, the light rays 22 are reflected onto the photoresist layer (PR) causing overexposure.
• PR photoresist layer
• etching the DARC it is meant that the etch is preferential to the DARC relative to the adjacent oxide and that the DARC is etched at a rate greater than the oxide.
• the present invention provides a method for selectively etching antireflective coatings such as DARC.
• DARC is selectively etched using a flourine-containing, ionizable compound in solution with an acid or a base.
• the etchant is composed of about 35-40 wt.% NH 4 F and about 0.9-5.0 wt.% H 3 P0 4 in an aqueous solution.
• the present invention relates generally to the etching of DARC preferentially to surrounding oxide layers and structures. Accordingly, the present invention is broadly applicable to all fields where it is desirable to remove DARC and preserve oxide .
• FIG. 3 there is shown a portion of a partially completed integrated circuit consisting of a substrate 10, preferably composed of monocrystalline silicon. Field oxide regions 11 and semiconductor device structures such as polysilicon or polycide gate electrodes 14 are formed in and on the substrate 10. A thick insulating dielectric layer 16 is deposited over the semiconductor device structures . An oxide layer 20 is then grown over the dielectric layer 16. According to the preferred embodiment, the oxide layer is composed of borophosphosilicate glass (BPSG) ; however other oxides such as phosphosilicate glass (PSG) , silicon dioxide, or the like can also be used. Next, a DARC layer 24 is deposited over the oxide layer 20, typically by Chemical Vapor Deposition (CVD) .
• CVD Chemical Vapor Deposition
• DARC/BPSG etch rates >1 can additionally be
• agents include but are not limited to 0 3 and H 2 0 2 .

Landscapes

• Weting (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Publications (1)

Family

ID=21919957

Family Applications (1)

Country Status (6)

Cited By (2)

Families Citing this family (20)

Citations (5)

Family Cites Families (14)

• 1998
  • 1998-03-13 US US09/042,086 patent/US5981401A/en not_active Expired - Lifetime
• 1999
  • 1999-01-28 JP JP2000536100A patent/JP4152589B2/ja not_active Expired - Lifetime
  • 1999-01-28 EP EP99905487A patent/EP1062691B1/en not_active Expired - Lifetime
  • 1999-01-28 WO PCT/US1999/001696 patent/WO1999046808A1/en not_active Ceased
  • 1999-01-28 KR KR1020007009905A patent/KR100575128B1/ko not_active Expired - Fee Related
  • 1999-01-28 AU AU25637/99A patent/AU2563799A/en not_active Abandoned
  • 1999-08-25 US US09/382,399 patent/US6103637A/en not_active Expired - Lifetime
• 2000
  • 2000-02-01 US US09/495,518 patent/US6200909B1/en not_active Expired - Lifetime

Patent Citations (5)

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