WO1998052223A1 - Method and apparatus for cooling a semiconductor die - Google Patents

Method and apparatus for cooling a semiconductor die Download PDF

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Publication number
WO1998052223A1
WO1998052223A1 PCT/US1998/007490 US9807490W WO9852223A1 WO 1998052223 A1 WO1998052223 A1 WO 1998052223A1 US 9807490 W US9807490 W US 9807490W WO 9852223 A1 WO9852223 A1 WO 9852223A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor die
cooling plate
cooling
device described
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1998/007490
Other languages
English (en)
French (fr)
Inventor
Paul Winer
Mario J. Paniccia
Karl J. Ma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to AU69718/98A priority Critical patent/AU6971898A/en
Priority to JP54923498A priority patent/JP4040695B2/ja
Publication of WO1998052223A1 publication Critical patent/WO1998052223A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/40—Arrangements for thermal protection or thermal control involving heat exchange by flowing fluids
    • H10W40/43—Arrangements for thermal protection or thermal control involving heat exchange by flowing fluids by flowing gases, e.g. forced air cooling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/40—Arrangements for thermal protection or thermal control involving heat exchange by flowing fluids
    • H10W40/47—Arrangements for thermal protection or thermal control involving heat exchange by flowing fluids by flowing liquids, e.g. forced water cooling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors

Definitions

  • the present invention relates generally to integrated circuit technology and, more specifically, the present invention relates to controlling the temperature of an integrated circuit.
  • C4 packaging In C4 packaging technology, the integrated circuit die is flipped upside down relative to integrated circuit dies are packaged using wire bond technology.
  • the removal of heat from a wire bonded semiconductor device 101 generally involves attaching a finned heat sink 103 to a bottom surface 107 of a package 111 and passing an air flow 109 over heat sink 103.
  • a heat flow path is established across a back side surface 105 of semiconductor device 101 through package 111 and into heat sink 103.
  • a heat slug (not shown) that may be embedded within package 111 thermally couples semiconductor device 101 to heat sink 103. Heat is then carried away by air flow 109 passing across heat sink 103.
  • Figure 1 B illustrates the removal of heat from a wire bonded semiconductor die 131 during silicon debug.
  • semiconductor die 131 is packaged in a wire bond package 141 that is mounted on a circuit board 145.
  • Probe tool 143 is part of an electron beam (e-beam) system used to debug semiconductor die 131 while operating in a vacuum chamber. With direct unobstructed access to semiconductor die 131 , probe tool 143 may be used to obtain information from semiconductor die 131 while operating.
  • e-beam electron beam
  • a cooling technique commonly used in present day e-beam probing systems employs the use of a cooling block 149, which is thermally coupled to a bottom surface 147 of package 141. Heat generated by semiconductor die 131 is transferred through package 141 to cooling block 149. Coolant 151 is circulated through cooling block 149 to regulate the temperature of cooling block 149, and thus regulate the temperature of semiconductor die 131.
  • FIG. 2 illustrates heat being dissipated from a C4 packaged semiconductor die 201.
  • Heat is removed from a back side surface 205 of semiconductor die 201 by passing an air flow 209 over a finned heat sink 203 that is thermally coupled to back side surface 205.
  • heat is dissipated from semiconductor die 201 by attaching a thermally conductive heat slug (not shown) to back side surface 205 and then thermally coupling the heat slug to a heat sink (not shown).
  • the heat slug is thermally coupled to a metal plate having a large thermal mass and a large heat transfer area.
  • the heat slug may be thermally coupled to a heat spreading plate by heat pipe or some other low resistance thermal path.
  • heat is generally not dissipated through package 207 as solder bumps 211 are generally not considered to be good thermal conductors.
  • package 207 may be an organic package, and therefore have the characteristics of a thermal insulator.
  • a heat sink 203 is normally utilized in C4 packaging to remove heat from semiconductor die 201. If heat sink 203 is removed from semiconductor die 201 for debug purposes, continuous operation of the integrated circuit during analysis may damage the circuits of semiconductor die 201. In addition, if C4 mounted semiconductor die 201 is operated in a vacuum chamber of an e-beam probing system, the normal cooling mechanisms such as conduction are not available. Without the ability to regulate the temperature of semiconductor die 201 , sustained operation of semiconductor die 201 at full operating speeds may result in circuit degradation and/or damage.
  • a method and an apparatus for cooling a semiconductor die is disclosed.
  • a cooling plate having an opening is disposed over a first surface of the semiconductor die such that the cooling plate is thermally coupled to the semiconductor die. Heat is transferred from the semiconductor die to the cooling plate.
  • the opening of the cooling plate is disposed over an exposed portion of the semiconductor die such that unobstructed access to the exposed portion of the semiconductor die is provided.
  • Figure 1A illustrates a wire bond packaged semiconductor device having a finned heat sink attached to the back side of the package.
  • Figure 1 B illustrates a wire bond packaged semiconductor device being probed during debug and cooled with a cooling block attached to the back side of the package.
  • Figure 2 illustrates a C4 packaged semiconductor device having a finned heat sink attached to the back side of the semiconductor substrate.
  • Figure 3 illustrates a C4 packaged semiconductor device having a cooling plate thermally coupled to a semiconductor die while being probed with a probe tool in accordance with the teachings of the present invention.
  • Figure 4A is a top view illustration of a cooling plate having an opening disposed over a semiconductor die in accordance with the teachings of the present invention.
  • Figure 4B is a top view illustration of another embodiment of a cooling plate having an opening disposed over a semiconductor die in accordance with the teachings of the present invention.
  • Figure 4C is an illustration of yet another embodiment of a cooling plate having more than opening disposed over the semiconductor dies of a multi-chip module in accordance with the teachings of the present invention.
  • Figure 5 is an illustration of a C4 packaged semiconductor device thermally coupled to a cooling plate that is thermally coupled to a cooling block through a heat transfer conduit in accordance with the teachings of the present invention.
  • One embodiment of the present invention provides a method and an apparatus for controlling the temperature of a flip-chip or C4 packaged integrated circuit in a vacuum system without significantly obscuring the exposed circuit substrate.
  • the embodiment enables probing of a C4 packaged integrated circuit during silicon debug and fault isolation.
  • Temperature control of the semiconductor die of the C4 packaged integrated circuit is realized with one embodiment of the present invention without relying upon thermal conduction through the package and without significantly obscuring the exposed circuit substrate. Temperature control is accomplished in one embodiment by making direct thermal contact with a cooling plate to the exposed substrate of the C4 mounted integrated circuit in such a manner that the thermal conduction of the package does not effect the efficiency of the temperature controlling system.
  • FIG. 3 is a side view illustration of a semiconductor die 301 packaged in a C4 package 303.
  • C4 package 303 is mounted in a socket 305 to operate on a circuit board 307.
  • a probe tool 309 is used to extract information from an exposed back side surface 311 of semiconductor die 301 as shown in Figure 3.
  • semiconductor die 301 is configured to operate at full intended operating speeds in the vacuum chamber of an e-beam probing system. It is recognized, however, that the present invention is not limited for use in e-beam probing systems and may therefore also be useful in other debugging systems such as for example laser based testing systems, mechanical probing systems, or the like.
  • a cooling plate 313 having an opening 315 is placed in direct contact with the exposed substrate of semiconductor die 301 as shown in Figure 3. With cooling plate 313 in direct contact with the exposed substrate of semiconductor die 301 , heat is transferred from semiconductor die 301 to cooling plate 313 through the thermal coupling at the interface between semiconductor die 301 and cooling plate 313. With opening 315, probe tool 309 has direct unobstructed access to the back side surface 311 of semiconductor die 301 for silicon debug and fault isolation purposes.
  • the interface contact surfaces between semiconductor die 301 and cooling plate 313 may not be planar.
  • the thermal coupling between cooling plate 313 and semiconductor die 301 would consist only of point contacts.
  • the thermal conductivity between semiconductor die 301 and cooling plate 313 is reduced thereby increasing the thermal resistance between semiconductor die 301 and cooling plate 313.
  • the efficiency of the presently described temperature controlling system is reduced.
  • a malleable or pliable thermal conductor is disposed at the interface between semiconductor die 301 and cooling plate 313 to increase the thermal conductivity between semiconductor die 301 and cooling plate 313.
  • indium, or an indium alloy is utilized as the malleable thermal conductor so as to provide a conformable thermal interface so as to increase the thermal conductivity and reduce the thermal resistance between cooling plate 313 and semiconductor die 301.
  • Indium is particularly useful for this aspect of the present invention due to its high thermal conductivity, malleable characteristics and low melting temperature.
  • indium is vacuum compatible, which makes it well suited for use in the vacuum chambers of e-beam probing systems.
  • a thin layer of indium 317 is disposed around the edges of the back side surface 311 of semiconductor die 301 at locations where cooling plate 313 will eventually be in contact with semiconductor die 301.
  • indium 317 is an indium foil- After the indium 317 is placed at the edges of semiconductor die 301 , it is melted and cooling plate 313 is then pressed against semiconductor die 301 such that a very conformable coating of indium 317 is formed between semiconductor die 301 and cooling plate 313. In another embodiment, indium 317 is not melted before cooling plate 313 is pressed against semiconductor die 301. Thus, a conformable thermal interface with increased thermal conductivity is formed between semiconductor die 301 and cooling plate 313.
  • thermal conductors may be used in place of indium in accordance with the teachings of the present invention so long as a conformable thermal contact is formed between semiconductor die 301 and cooling plate 313.
  • a thermal paste may be used instead of indium 317 to improve the thermal coupling between semiconductor die 301 and cooling plate 313. It is recognized, however, that some thermal pastes are not particularly well suited for use in vacuums due to their out gas properties.
  • the portion of cooling plate 313 disposed above semiconductor die 301 is thinned to approximately 1 mm. In doing so, probe tool 309 is provided increased access and maneuverability to extract information the back side surface 311 of semiconductor die 301 during debug testing or fault isolation.
  • coolant 319 is circulated through cooling plate 313 in order to regulate the temperature of cooling plate 313.
  • the heat generated by semiconductor die 301 may be transferred to cooling plate 313 and then out of cooling plate 313 through coolant 319 to an external cooler (not shown) in accordance with teachings of the present invention.
  • Figure 4A is a top view illustration of a cooling plate 413 having an opening 415 disposed over and thermally coupled to a semiconductor die 401 in accordance with the teachings of the present invention.
  • the dimensions of opening 415 are smaller than the outer dimensions of the edges of semiconductor die 401 such that semiconductor die 401 is thermally coupled to cooling plate 413 at an interface contact region 417 located on the back side surface of semiconductor die 401.
  • a malleable thermal conductor such as indium is disposed between cooling plate 413 and semiconductor die 401 in interface contact region 417 to increase the thermal coupling between semiconductor die 401 and cooling plate 413.
  • probing tools such as an e-beam probe or a laser based testing system have direct unobstructed access to the exposed circuit substrate on the back side of semiconductor die 401 through opening 415.
  • FIG 4B is a top view illustration of another embodiment of the present invention in which a cooling plate 433 having an opening 435 is disposed over and thermally coupled to a semiconductor die 431. As shown in Figure 4B, opening 435 is configured to expose an entire corner of semiconductor die 431. In the embodiment illustrated, semiconductor die 431 is thermally coupled to cooling plate 433 in an interface contact region 437. It is appreciated that in the embodiment shown in 4B, direct unobstructed access is provided to the entire exposed corner of semiconductor die 431 , including the edges of the exposed corner of semiconductor die 431 for probing purposes.
  • a malleable thermal conductor may be disposed between cooling plate 433 and semiconductor die 431 in the interface contact region 437. In doing so, the thermal conductivity between semiconductor die 431 and cooling plate 433 is increased, thus increasing the thermal coupling between semiconductor die 431 and cooling plate 433. By increasing the thermal coupling, the temperature gradient across semiconductor die 431 may be reduced.
  • FIG. 4C is a top view illustration of yet another embodiment of the present invention with a cooling plate 473 having openings 475A-D.
  • each opening 475A-D is configured to be disposed over a corresponding back side surface of semiconductor dies 471 A-D.
  • semiconductor dies 471 A-D are included in a multi-chip module (MCM) unit.
  • MCM multi-chip module
  • Each semiconductor die 471 A-D is thermally coupled to cooling plate 473 such that heat is transferred from each respective semiconductor die 471 A-D to a cooling plate 473.
  • Each opening 475A-D is disposed over a corresponding semiconductor die 471 A-D such that direct unobstructed access is provided to an exposed portion of the back side of each semiconductor die 471 A-D. Accordingly, probing may be performed in the exposed portion of each semiconductor die 471 A-D for silicon debug in fault isolation purposes.
  • heat is transferred from silicon die 471 A to cooling plate 473 through an interface contact region 477A.
  • Heat is transferred from semiconductor die 471 B to cooling plate 473 through an interface contact region 477B.
  • Heat is transferred from semiconductor die 471 C to cooling plate 473 through an interface contact region 477C.
  • Heat is transferred from semiconductor die 471 D to cooling plate 473 through an interface contact region 477D.
  • a malleable thermal conductor such as indium is disposed between semiconductor dies 471 A-D and cooling plate 473 in interface contact regions 477A-D to increase the thermal coupling between cooling plate 473 and each respective semiconductor die 471 A- D.
  • the present invention is not limited to cooling plates having only the shapes and openings described with respect to Figures 4A-C and that cooling plates and openings having other shapes may therefore be used so long as the semiconductor dies are cooled with significantly obscuring the exposed semiconductor die in accordance with the teachings of the present invention.
  • FIG. 5 is an illustration of another embodiment of a method and apparatus for cooling a semiconductor die in accordance with the teachings of the present invention.
  • a semiconductor die 501 is packaged in a C4 package 503, which is mounted in a socket 505 mounted on a circuit board 507. Similar to the system described with respect to Figure 1 B, semiconductor die 501 may be operated in the vacuum chamber of an e-beam probing system for silicon debug and fault isolation purposes.
  • a cooling plate 513 having an opening 515 is disposed over and thermally coupled to semiconductor die 501. Opening 515 is disposed over a back side surface 511 of semiconductor die 501 thus providing direct and unobstructed access for a probe tool 509 to the exposed portion of the back side surface 511 of semiconductor die 501.
  • a malleable thermal conductor such as indium 517 is disposed between semiconductor die 501 and cooling plate 513 in the interface contact region to provide a conformable thermal contact between semiconductor die 501 and cooling plate 513 such that the thermal coupling between semiconductor die 501 and cooling plate 513 is increased. Therefore, the heat generated by semiconductor die 501 while operating at full intended operating speeds is transferred to cooling plate 513 through indium 517.
  • the present invention may be compatible with the temperature control systems of present day e-beam probing systems in which a cooling block 519 is disposed on the opposite side of circuit board 507.
  • probe tool 509 probes semiconductor die 501 , which is mounted on circuit board 507.
  • cooling block 519 is located on the opposite side of circuit board 507 as is the case with many existing e-beam probing systems that are configured to probe wire bond packaged integrated circuits.
  • cooling plate 513 is thermally coupled to cooling block 519 through heat transfer conduits 523A and 523B.
  • heat transfer conduits 523A-B include thermal screws that extend from cooling plate 513 through openings 525A and 525B respectively in circuit board 507 to cooling block 519.
  • cooling block 519 includes threaded holes 529A and 529B configured to receive the threads 527A and 527B of heat transfer conduits 523A and 523B respectively.
  • heat transfer conduits 523A and 523B thermally couple cooling plate 513 to cooling block 519 such that heat is transferred from semiconductor die 501 through cooling plate 513, through heat transfer conduits 523A-B to cooling block 519.
  • the thermal screws of heat transfer conduits 523A and 523B include oversized heads 531 A and 531 B respectively as well as oversized threads 527A and 527B respectively.
  • the thermal screws of heat transfer conduits 523A and 523B include oversized heads 531 A and 531 B respectively as well as oversized threads 527A and 527B respectively.
  • cooling plate 513 includes features 533A and 533B located on circuit board 507 side of cooling plate 513 such that features 533A and 533B tend to push C4 package 503 into socket 505 of circuit board 507 when the thermal screws of heat transfer conduits 523A and 523B are tightened. As such, it is more likely that C4 package 503 is properly seated in socket 505 after thermal screws of heat transfer conduits 523A and 523B are tightened.
  • the thermal screws of heat transfer conduits 523A and 523B also allow adjusting of the plane of cooling plate 513 to the plane of the back side surface 511 of semiconductor die 501 so as to further increase thermal contact through indium 517.
  • cooling plate 513 includes copper with a nickel coating.
  • the thermal screws of heat transfer conduits 523A and 523B are also made of copper. It is recognized that copper is particularly well suited for the present application since copper is a good thermal conductor. It is noted however that the present invention is not limited to a cooling plate 513 and heat transfer conduits 523A and 523B that are made of copper and that other materials may therefore be used so long as cooling plate 513 and heat transfer conduits 523A and 523B have sufficient thermal conductivity to cool semiconductor die 501 in accordance with the teachings of the present invention.
  • coolant 521 is circulated through cooling block 519 to further facilitate the removal of heat from semiconductor die 501.
  • C4 mounted integrated circuits or MCM units may be operated in a vacuum chamber of an e-beam probing system for a silicon debug and fault isolation.
  • the presently described cooling method and apparatus also provide cooling to C4 mounted integrated circuits or MCM units operated outside a vacuum chamber during laser based tests or mechanical probing.
  • the presently apparatus and method cool the semiconductor die without relying upon thermal conduction through package and without significantly obscuring the exposed circuit substrate of the C4 or MCM units.
  • the present invention is compatible with existing temperature control systems in present day e- beam probing systems typically configured to cool the semiconductor dies through their respective packages.

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)
PCT/US1998/007490 1997-05-14 1998-04-14 Method and apparatus for cooling a semiconductor die Ceased WO1998052223A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU69718/98A AU6971898A (en) 1997-05-14 1998-04-14 Method and apparatus for cooling a semiconductor die
JP54923498A JP4040695B2 (ja) 1997-05-14 1998-04-14 半導体ダイを冷却する装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/856,267 US5923086A (en) 1997-05-14 1997-05-14 Apparatus for cooling a semiconductor die
US08/856,267 1997-05-14

Publications (1)

Publication Number Publication Date
WO1998052223A1 true WO1998052223A1 (en) 1998-11-19

Family

ID=25323202

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/007490 Ceased WO1998052223A1 (en) 1997-05-14 1998-04-14 Method and apparatus for cooling a semiconductor die

Country Status (7)

Country Link
US (1) US5923086A (https=)
JP (1) JP4040695B2 (https=)
KR (1) KR100381431B1 (https=)
CN (1) CN1154180C (https=)
AU (1) AU6971898A (https=)
MY (1) MY114590A (https=)
WO (1) WO1998052223A1 (https=)

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JP2001526838A (ja) 2001-12-18
MY114590A (en) 2002-11-30
JP4040695B2 (ja) 2008-01-30
CN1263638A (zh) 2000-08-16
AU6971898A (en) 1998-12-08
CN1154180C (zh) 2004-06-16
KR20010012569A (ko) 2001-02-15
KR100381431B1 (ko) 2003-04-23
US5923086A (en) 1999-07-13

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