WO1998048355A2 - Procede pour transferer un systeme d'exploitation dans des installations informatiques - Google Patents

Procede pour transferer un systeme d'exploitation dans des installations informatiques Download PDF

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Publication number
WO1998048355A2
WO1998048355A2 PCT/DE1998/001071 DE9801071W WO9848355A2 WO 1998048355 A2 WO1998048355 A2 WO 1998048355A2 DE 9801071 W DE9801071 W DE 9801071W WO 9848355 A2 WO9848355 A2 WO 9848355A2
Authority
WO
WIPO (PCT)
Prior art keywords
addresses
operating system
target hardware
reserved
hardware
Prior art date
Application number
PCT/DE1998/001071
Other languages
German (de)
English (en)
Other versions
WO1998048355A3 (fr
Inventor
Alfred Isele
Original Assignee
Siemens Nixdorf Informationssysteme Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Nixdorf Informationssysteme Ag filed Critical Siemens Nixdorf Informationssysteme Ag
Priority to JP10544720A priority Critical patent/JP2000513128A/ja
Priority to EP98931931A priority patent/EP0978042A2/fr
Publication of WO1998048355A2 publication Critical patent/WO1998048355A2/fr
Publication of WO1998048355A3 publication Critical patent/WO1998048355A3/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/109—Address translation for multiple virtual address spaces, e.g. segmentation

Definitions

  • the invention relates to a method for data processing systems for controlling the transmission of an operating system for original hardware that supports a real addressing mode to target hardware that processes only virtual addresses.
  • microprocessors in mainframe computer systems e.g. B. in IBM / 390 systems, differentiate in the addressing of the main memory between a "real" and a "virtual" addressing mode.
  • real mode the entire main memory available to the operating system can be addressed directly and independently of the process. This is e.g. B. required when booting the system, interrupt handling and communication with the input / output processors.
  • processors e.g. B. RISC processors R4000 from MIPS
  • memory addressing takes place at least in part via so-called “virtual” addresses which (usually with the aid of conversion tables) are mapped to physical memory addresses. This mapping is often dependent on the process currently running on the system.
  • FIG. 1 shows a schematic illustration to explain the address assignments and FIG. 2 shows an associated mapping diagram
  • FIG. 1 shows the schematic representation of the main memory HS1 of an original hardware Ml in the left part of the figure and the main memory HS2 of a target hardware M2 in the right part of the figure, PSA denoting the address space of the physical memory and DAR the superimposed real address space for the original hardware Ml.
  • the latter is also the start address of the operating system OS1 to be ported with the addresses EV1 for accepting exceptional conditions.
  • the address space for the operating system OSl extends to the address Bl-1, and the address Bl is z.
  • the start addresses EV2 for accepting the exception bindings at the beginning of the address space PSA for the physical memory are provided with a separate control Program GSP coupled, which forms a bridge to the porting operating system 0S2 so that it can react to the exceptional conditions of the M2 system.
  • the scope of the separate control program GSP depends, among other things, on the configuration of the target hardware M2, so that the start of the address space available to the operating system in physical memory cannot be determined from the outset.
  • FIG 2 illustrates this relationship.
  • the reserved address space RADR with real addressing is shown along the abscissa axis and the address space PSA for the physical memory along the ordinate axis.
  • the real address space corresponds to 0 to B2-A2 for the ported
  • Operating system OS2 with the physical address space A2 is B2. The same applies to the ported user program AWP2.
  • one of the virtual address spaces is reserved for the real addressing mode.
  • the currently valid address space identifier shows which addressing mode applies, and the control for address management and translation as well as for the reloading processes can react accordingly.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Ce procédé permet l'utilisation d'un système d'exploitation (OS1), destiné à un matériel source (M1) supportant un mode d'adressage réel, sur un matériel cible (M2) supportant uniquement un mode d'adressage virtuel, tout en maintenant l'adressage de la mémoire principale qui est indépendant de la configuration et du processus. A cet effet, un des espaces adresse virtuels pour l'adressage, indépendant du processus, de la mémoire principale (HS2) est réservé et, conformément au mode d'adressage réel, est utilisé sur le matériel source (ME2). Un programme de commande séparé (GSP) situé en aval permet au système d'exploitation transféré (OS2) de réagir à des conditions exceptionnelles (EV2) du matériel cible (M2), et les adresses réelles du système d'exploitation à transférer sont imagées, dans l'espace adresse réservé, sur des adresses libres de la mémoire physique qui ne sont pas occupées par le programme de commande séparé (GSP).
PCT/DE1998/001071 1997-04-23 1998-04-16 Procede pour transferer un systeme d'exploitation dans des installations informatiques WO1998048355A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP10544720A JP2000513128A (ja) 1997-04-23 1998-04-16 データ処理装置におけるオペレーティングシステムの転送方法
EP98931931A EP0978042A2 (fr) 1997-04-23 1998-04-16 Procede pour transferer un systeme d'exploitation dans des installations informatiques

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19717102.8 1997-04-23
DE19717102A DE19717102A1 (de) 1997-04-23 1997-04-23 Verfahren zur Übertragung eines Betriebssystems in Datenverarbeitungsanlagen

Publications (2)

Publication Number Publication Date
WO1998048355A2 true WO1998048355A2 (fr) 1998-10-29
WO1998048355A3 WO1998048355A3 (fr) 1999-01-28

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1998/001071 WO1998048355A2 (fr) 1997-04-23 1998-04-16 Procede pour transferer un systeme d'exploitation dans des installations informatiques

Country Status (4)

Country Link
EP (1) EP0978042A2 (fr)
JP (1) JP2000513128A (fr)
DE (1) DE19717102A1 (fr)
WO (1) WO1998048355A2 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5038281A (en) * 1986-09-19 1991-08-06 International Business Machines Corporation Acceleration of system interrupts between operating systems in guest-host relationship
EP0645701A2 (fr) * 1993-09-28 1995-03-29 Bull HN Information Systems Inc. Emulation des fonctions mémoire d'un premier système sur un deuxième
US5479631A (en) * 1992-11-19 1995-12-26 International Business Machines Corporation System for designating real main storage addresses in instructions while dynamic address translation is on

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58102380A (ja) * 1981-12-11 1983-06-17 Hitachi Ltd 仮想記憶管理方法
JP2510605B2 (ja) * 1987-07-24 1996-06-26 株式会社日立製作所 仮想計算機システム
JP2839201B2 (ja) * 1990-07-30 1998-12-16 株式会社日立製作所 仮想計算機システム

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5038281A (en) * 1986-09-19 1991-08-06 International Business Machines Corporation Acceleration of system interrupts between operating systems in guest-host relationship
US5479631A (en) * 1992-11-19 1995-12-26 International Business Machines Corporation System for designating real main storage addresses in instructions while dynamic address translation is on
EP0645701A2 (fr) * 1993-09-28 1995-03-29 Bull HN Information Systems Inc. Emulation des fonctions mémoire d'un premier système sur un deuxième

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SHANG RONG TSAI ET AL: "ON THE ARCHITECTURAL SUPPORT FOR LOGICAL MACHINE SYSTEMS" MICROPROCESSING AND MICROPROGRAMMING, Bd. 22, Nr. 2, 1. Februar 1988, Seiten 81-96, XP000284881 *

Also Published As

Publication number Publication date
EP0978042A2 (fr) 2000-02-09
DE19717102A1 (de) 1998-10-29
WO1998048355A3 (fr) 1999-01-28
JP2000513128A (ja) 2000-10-03

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