WO1998028789A1 - Dispositif memoire a semi-conducteur et procede de fabrication associe - Google Patents

Dispositif memoire a semi-conducteur et procede de fabrication associe Download PDF

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Publication number
WO1998028789A1
WO1998028789A1 PCT/JP1996/003735 JP9603735W WO9828789A1 WO 1998028789 A1 WO1998028789 A1 WO 1998028789A1 JP 9603735 W JP9603735 W JP 9603735W WO 9828789 A1 WO9828789 A1 WO 9828789A1
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WIPO (PCT)
Prior art keywords
insulating film
electrode
region
film
capacitor
Prior art date
Application number
PCT/JP1996/003735
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English (en)
Japanese (ja)
Inventor
Toshiaki Yamanaka
Shinichiro Kimura
Hideyuki Matsuoka
Hideo Sunami
Kiyoo Itoh
Tomonori Sekiguchi
Takeshi Sakata
Masayuki Miyazaki
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1996/003735 priority Critical patent/WO1998028789A1/fr
Priority to TW086110894A priority patent/TW351853B/zh
Publication of WO1998028789A1 publication Critical patent/WO1998028789A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

Definitions

  • the present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory having a three-dimensional structure suitable for high integration.
  • a dynamic random access memory (hereinafter, abbreviated as dynamic RAM) is a unit of a memory cell to which a charge storage capacitor for storing information and a switch transistor for writing and reading the capacitance are connected. It was done. As described above, since one memory cell has a small number of constituent elements, it is widely and generally used as a main storage device of a computer device requiring a large capacity.
  • FIG. 46 shows a partial cross-sectional view of a conventional dynamic RAM * IC.
  • the MISFET of a memory cell group called a memory array includes a gate insulating film 103, a gate electrode 104, and a high-concentration n-type impurity region 105.
  • the gate electrode 104 of this MISFET constitutes a word line.
  • the wiring electrode 107 forms a data line, and is electrically connected to an n-type high-concentration impurity region 105 through an opening provided in a silicon oxide film 106 (interlayer insulating film). It is connected.
  • the n-type high-concentration impurity region 105 is connected to a lower electrode (storage electrode) 112 of a crown-shaped capacitor formed of polycrystalline silicon above the word line and the data line.
  • a capacitor dielectric film 113 is deposited, and on the upper part, a plate electrode 114 is provided.
  • the lower electrode 1 1 and 2 is formed in a cylindrical shape, and the effective area of the capacity is increased by using not only a plane portion but also an inner surface (inner wall) and an outer surface (outer wall) of a vertical portion.
  • the so-called C ⁇ B (Capacitor On Bit) structure in which storage electrodes are provided on data lines (bit lines) maximizes the effective area of capacity.
  • the memory cell can be miniaturized, and the storage capacity of the capacity can be easily increased. be able to.
  • a field oxide film 102 for insulating and isolating elements is grown on a single crystal silicon substrate 101, and a gate oxide film 103 of MISFET is grown.
  • the gate oxide film 103 is formed to a desired thickness by thermally oxidizing the surface of the substrate 101.
  • a polycrystalline silicon film containing impurities at a high concentration is deposited, and the polycrystalline silicon film is patterned. Thereafter, an n-type high-concentration impurity region 105 serving as a source / drain region of the MISFET self-aligned with the gate electrode 104 is formed in the single-crystal silicon substrate 101 by ion implantation. Formed.
  • a silicon oxide film 106 After depositing a silicon oxide film 106, an opening (not shown) is formed in the high-concentration impurity region 105 of the MISFET in the memory cell region. Then, a polycrystalline silicon film and a tungsten silicide film containing impurities at a high concentration are sequentially deposited as wiring electrodes, and these laminated films are patterned.
  • a silicon oxide film 108 After depositing a silicon oxide film 108, an opening is formed on the high concentration n-type impurity region 105 of the source or drain of the MISFET in the memory cell region.
  • a polycrystalline silicon film and a thick silicon oxide film are deposited successively. Then, after these are simultaneously patterned, a polycrystalline silicon film is further deposited, and the polycrystalline silicon film having a flat portion exposed by anisotropic dry etching is etched, thereby forming the silicon oxide film. The polycrystalline silicon film is left on the side wall. Further, by removing the silicon oxide film, a crown-shaped storage electrode 112 is formed.
  • a capacitor dielectric film 113 After depositing a capacitor dielectric film 113, a polycrystalline silicon film to be a plate electrode 114 is deposited and patterned.
  • aluminum wiring is formed as the silicon oxide film 115 of the interlayer insulating film and the metal wiring 119, and the MISFET of the peripheral circuit and the memory cell are manufactured.
  • the adoption of a capacity having three-dimensional storage electrodes has made it possible to increase the storage capacity. As a result, it is possible to secure a sufficient storage capacity for the operation and reliability of the memory cell even with a fine memory cell.
  • the elevation of the memory cell group is relatively high, and the elevation of the peripheral circuit is relatively low, and a large elevation difference is generated between the memory cell group and the peripheral circuit.
  • the difference in elevation between the memory cell group region and the region where the peripheral circuit is formed is significantly different after the formation of the capacitance, for example, the metal wiring 11 from the memory cell group region above the capacitance to the peripheral circuit region 9 and the photolithography process for forming metal wiring in each area becomes extremely difficult. That is, generally, in a reduction projection exposure apparatus used for manufacturing a semiconductor memory device, the resolution and the depth of focus are in inverse proportion. Because of this, If a high-resolution stepper is used to form fine dimensions, the depth of focus becomes shallower, and the necessity to make the element surface flatter has arisen.
  • An object of the present invention is to provide a novel semiconductor memory device manufacturing method capable of forming a fine wiring between a memory cell region with a high density and an increased storage capacity and a peripheral circuit region in one semiconductor substrate.
  • Another object of the present invention is to provide a memory cell having a three-dimensionally structured capacity and a method of manufacturing a dynamic RAM in which fine wiring can be provided above the capacity.
  • Still another object of the present invention is to provide a novel semiconductor memory device suitable for gigabit or more.
  • a lower electrode for capacitance, a dielectric film for capacitance, and an upper electrode for capacitance are sequentially deposited on a second insulating film formed in a memory cell region of a semiconductor substrate.
  • the height at which the three-dimensional capacity is formed is equal to the height of the wiring layer in the peripheral circuit region. There is no difference in elevation, and a flat insulating film can be formed on the upper part of the capacity. For this reason, finer wiring can be formed on the capacity in the memory cell portion and on the common insulating film on the peripheral circuit portion.
  • FIG. 1 relates to a first embodiment of the present invention, and is a partial cross-sectional view showing a semiconductor memory device in which a dynamic RAM is configured.
  • FIG. 2 shows a semiconductor memory device according to the first embodiment of the present invention.
  • FIG. 2 is a plan view showing a part of a memory cell array section of the semiconductor memory device.
  • 3 to 14 relate to the first embodiment of the present invention and are cross-sectional views showing the steps of manufacturing a semiconductor memory device.
  • FIG. 15 relates to the first embodiment of the present invention and is a cross-sectional view showing a capacity power supply section of a semiconductor memory device.
  • FIG. 16 relates to the second embodiment of the present invention and is a cross-sectional view showing a semiconductor memory device having a dynamic RAM.
  • FIGS. 17 to 30 are cross-sectional views illustrating a manufacturing process of the semiconductor memory device having the dynamic RAM according to the third embodiment of the present invention.
  • FIG. 31 relates to a fourth embodiment of the present invention and is a partial cross-sectional view showing a semiconductor memory device having a dynamic RAM.
  • FIGS. 32 to 35 relate to the fourth embodiment of the present invention and are cross-sectional views showing the steps of manufacturing the semiconductor memory device.
  • FIG. 36 relates to a fifth embodiment of the present invention, and is a partial cross-sectional view showing a semiconductor memory device having a dynamic RAM.
  • FIGS. 37 to 41 relate to the fifth embodiment of the present invention and are cross-sectional views showing the steps of manufacturing the semiconductor memory device.
  • FIG. 42 relates to a sixth embodiment of the present invention and is a partial cross-sectional view showing a semiconductor memory device having a dynamic RAM.
  • FIG. 43 relates to a seventh embodiment of the present invention and is a partial cross-sectional view showing a semiconductor memory device having a dynamic RAM.
  • FIG. 44 is a plan view showing a chip layout of an embodiment in a dynamic RAM according to the present invention.
  • FIG. 45 is a plan view showing a chip layout of another embodiment in the dynamic RAM according to the present invention.
  • FIG. 46 is a partial cross-sectional view showing a semiconductor memory device in which a dynamic RAM conceived prior to the present invention is configured.
  • FIG. 1 shows a cross-sectional view of a memory cell and a cross-sectional view of a MISFET portion of a peripheral circuit adjacent thereto on the same drawing.
  • FIG. 2 is a plan view of the memory cell.
  • the cross-sectional view of the memory cell portion in FIG. 1 is a part of the cross section taken along line XX ′ in FIG.
  • MISFETs in a memory cell region (first region) and a peripheral circuit region (second region) have a gate insulating film 3, a gate electrode 4, It consists of high-concentration n-type impurity regions 5 that constitute the source and drain.
  • MISFET only one MISFET is displayed in the peripheral circuit area, but usually, a plurality of MISFETs constitute, for example, an input / output circuit, a decoder circuit, and an address circuit. More specifically, these peripheral circuits are constituted by a CMOS circuit composed of an n-channel MISFET and a p-channel MISFET.
  • a wiring electrode 7 as a data line (bit line) is connected to the high-concentration impurity region 5 of the MISFET in the memory cell.
  • a crown-shaped Stacked Capacitor is provided at the top.
  • the crown-shaped capacitor has a lower electrode (storage electrode) 12 electrically connected to the high-concentration n-type impurity region 5 through a silicon plug 9, a capacitor dielectric film 13, and an upper electrode. (Plate electrode) It has a 14-layer structure.
  • the wiring electrodes 17 in the peripheral circuit region are composed of the silicon oxide film 15, the upper electrode 14 of the capacitor, and the capacitor.
  • Each of the insulating films 13 is formed in a region where it has been removed.
  • the height of the wiring electrode 17 is substantially equal to the height of the memory cell region (specifically, the position where the height of the upper electrode 14 is high).
  • An insulating film (silicon oxide film) 18 is formed on the wiring electrode 17 and the upper part of the capacitor region by a CVD method, and the unevenness of the wiring is flattened.
  • the metal wiring 19 of the road is formed.
  • FIG. 2 is a plan view of a memory cell region in which a plurality of memory cells are arranged to make it easy to understand the positional relationship between adjacent memory cells, and shows a mask pattern.
  • the active region 33 has a T-shaped pattern.
  • the word line 34 (the gate electrode 4 in FIG. 1) crosses a part of the active region 33 in the Y direction
  • the data line 36 (the wiring electrode 7 in FIG. 1) in the X direction. are arranged.
  • the lower electrode 12 of the crown-shaped capacitor is formed in an elliptical cylindrical shape above the word line 34 and the data line 36.
  • the lower electrode 12 of this capacitor is formed with an opening 3 2 above the active region 33 (the high-concentration n-type impurity region 5 in FIG. 1) between the word line 34 and the data line 36. Connected through.
  • the data line 36 is electrically connected via the opening 35.
  • a field oxide film (LOCOS oxide film) 2 is formed on a crystalline silicon substrate 1 using a known selective oxidation method.
  • This field oxide 2 An MISFET is formed on the active region (eg, active region 33 shown in FIG. 2) by a known method.
  • the polarity of the MISFET of the memory cell is n-channel, but may be p-channel.
  • LDD Lightly Doped
  • Drain structure can also be used. Further, in order to use a known self-aligned connection, an insulating film such as a silicon nitride may be formed on a side wall or an upper portion of the gate electrode 4.
  • a silicon oxide film (BPSG) 6 containing boron and phosphorus is deposited by a known chemical vapor deposition method (hereinafter abbreviated as CVD method). Then, annealing is performed at a temperature of about 800 ° C. to smooth the surface of the silicon oxide film 6. It should be noted that the silicon oxide film 6 can be made flat by another method using a non-doped silicon oxide film without using boron (P) or phosphorus (B) added to phosphorus. Specifically, a known CMP method can be considered. Next, a silicon oxide film is formed in the opening 35 by photolithography and dry etching. Then, a conductor layer having a thickness of about 100 nm to become the data line 36 is deposited. Thereafter, the conductor layer is patterned by photolithography and dry etching to form the wiring electrode 7.
  • CVD method chemical vapor deposition method
  • a composite film of a silicide film of a high melting point metal such as tantalum and a polycrystalline silicon film, or a high melting point metal film of tungsten or the like can be preferably used.
  • a high melting point metal such as tungsten
  • reaction with the silicon substrate (silicon semiconductor region) is prevented.
  • a barrier metal film such as titanium nitride in the lower layer for the purpose of stopping.
  • a silicon oxide film (BPSG) 8 containing boron and phosphorus with a thickness of about 20 Onm is deposited by the CVD method. Then, annealing is performed at a temperature of about 800 ° C. to smooth the surface of the silicon oxide film 8. Next, an opening 32 is formed in the silicon oxide films 6 and 8 on the high-concentration n-type impurity region 5 serving as a source or drain of the MISFET by photolithography and dry etching.
  • a polycrystalline silicon film having a thickness of about 200 nm in which an impurity (for example, phosphorus) of the same conductivity type as the high-concentration n-type impurity region 5 is added at a high concentration is deposited by the LPCVD method. Then, the silicon plug 9 is formed by etching back the polycrystalline silicon film by anisotropic dry etching.
  • an impurity for example, phosphorus
  • a silicon plug was directly formed on the high-concentration n-type impurity region 5 (5a).
  • a method using a polycrystalline silicon film pad is conceivable.
  • the gate electrode 4 and the silicon plug 9 can be insulated by self-alignment, which is effective for reducing the memory cell area. That is, at the stage of forming the opening 35 shown in FIG. 4, a self-alignment is also performed on the high-concentration n-type impurity region (5a) using a silicon nitride film (not shown) as a mask. Then, a pad for the storage electrode is formed together with the pad for the data line. Then, an opening 32 is formed in the data line 36 and the silicon oxide film 8, and the silicon comp. Form lug 9.
  • a silicon nitride film 10 having a thickness of about 10 Onm is deposited on the silicon oxide film 8 by the LPCVD method. The reason for depositing the silicon nitride film 10 will be described later.
  • contact holes (CH) are formed in the silicon oxide films 6, 8 and the silicon nitride film 10 on the high-concentration n-type impurity region 5 in the peripheral circuit region.
  • a high-melting point metal such as tungsten with a thickness of about 20 O nm is deposited by a known sputtering method or a CVD method, and then etched back by dry etching to contact the peripheral circuit area.
  • a tungsten metal plug 11 is formed in the hole (CH).
  • the peripheral circuit area is composed of a CMOS circuit, an electrical connection between the high-concentration n-type impurity region and the high-concentration p-type impurity region is required on the circuit.
  • tungsten is used as a wiring material for connection to these impurity regions, interdiffusion of tungsten and silicon may occur between the two regions. Therefore, it is preferable to select titanium nitride (TiN) as a base material for the metal plug 11.
  • a silicon oxide film 20 having a thickness of about 700 nm is deposited at a temperature of about 400 ° C. by a known CVD method using TEOS (tetra 'ethoxy' silane) gas. Thereafter, an opening 25 is formed by selectively removing the silicon oxide film 20 where the lower electrode of the capacitor is to be formed by photolithography and dry etching.
  • TEOS tetra 'ethoxy' silane
  • the silicon oxide film 20 is used as an etching mask. Then, the silicon nitride film 10 exposed at the bottom of the opening 25 is removed by dry etching. Thereafter, the lower electrode 12 is formed along the opening 25. That is, a polycrystalline silicon film (lower electrode 12 in FIG. 7) to which an n-type impurity having a thickness of about 50 nm is added at a high concentration is deposited by a known LPCVD method. At this time, the silicon plug 9 and the polycrystalline silicon film are connected at the bottom of the opening 25. Next, a 500 nm thick silicon oxide film 21 is deposited by a CVD method. Then, the silicon oxide film 21 is etched back by dry etching.
  • the silicon oxide film 21 is buried in the opening 25. Further, by etching the polycrystalline silicon film in the portion of the silicon oxide film 21 exposed by the dry etching by dry etching, the lower electrode 12 of the capacity is formed in the opening 25. The remaining polycrystalline silicon remains.
  • the silicon oxide films 21 and 20 are removed by etching in a hydrofluoric acid aqueous solution to expose the lower electrode 12 of the crown-shaped capacitor. At this time, even if the over-etching is performed, the silicon nitride film 10 serves as an etching stopper, and there is no influence on the MISFET formed in the lower layer.
  • a dielectric film 13 having a higher dielectric constant than the silicon oxide film is deposited.
  • a CVD method having good step coverage is preferable.
  • the equivalent oxide thickness of the dielectric dielectric film is as large as 1 gigabit class. In the capacity dynamic RAM, it is preferable to set it to 3 nm or less.
  • an upper electrode 14 of about 50 nm such as tungsten or titanium nitride is deposited.
  • a polycrystalline silicon film is used for the lower electrode 12, but a refractory metal film such as a tungsten or titanium nitride film may be used.
  • a refractory metal film such as a tungsten or titanium nitride film
  • the influence of the natural oxide film on the surface of the polycrystalline silicon film can be eliminated, and the equivalent oxide film thickness of the capacitor dielectric film can be reduced.
  • a ferroelectric film such as a known high dielectric film and the PZT film may also be used, such as.
  • platinum (Pt) having high oxidation resistance is preferable as an electrode material.
  • a silicon oxide film 15 having a thickness of 70 nm is deposited so as to bury the irregularities of the capacity.
  • deposition method as in the case of the silicon oxide film 20 described above, deposition is performed at a temperature of about 400 ° C. by a known CVD method using TEOS gas. Then, the surface of the silicon oxide film 15 is made substantially flat by polishing using an etchback or CMP (Chemical-Mechanical-Polishing).
  • the silicon oxide film 15 and the upper electrode 14 of the capacitor and the capacitor dielectric film 13 were formed into the pattern of the upper electrode of the capacitor. Etch.
  • the pattern of the upper electrode 14 is, for example, a memory cell array portion (shown by oblique lines) 2 16 shown in FIGS. 44 and 45. Match.
  • the depth at which the silicon oxide film 15 is removed in other words, the thickness of the silicon oxide film is equal to the thickness of the metal layer Ml (wiring electrode 17) to be covered in a step described later. Is set. However, the depth at which the silicon oxide film 15 is removed may be within a range of about 0.3 im deeper than the film thickness of the wiring electrode 17. That is, the silicon oxide film 15 may be deposited to a thickness of about 1 Xm. This difference in film thickness is taken into consideration depending on the processing dimension (line width) of the metal wiring 17. As described above, the memory cell region has a crown-shaped capacity covered with the silicon oxide film 15, and the peripheral circuit region has a dynamic structure not covered with the silicon oxide film 15. A semiconductor body (wafer) is manufactured at the intermediate stage of the block RAM.
  • a metal layer M 1 as a conductive film is deposited to a thickness of about 700 nm (0.1 n) equivalent to that of the silicon oxide film 15 using a well-known sputter. .
  • the deposited metal layer M1 may be broken at a high step formed at the boundary between the memory cell region and the peripheral circuit region.
  • the metal layer Ml is preferably a low-resistance metal such as aluminum (A1), but may be a high-melting metal such as tungsten (W). If necessary, a barrier metal such as a titanium nitride (TiN) film or the like can be formed below the metal wiring 17.
  • the peripheral circuit from which the metal layer M l has been removed and the silicon oxide film 15 has been removed has been removed from the portion of the memory cell region having a high elevation difference.
  • the metal layer M 1 is left in the region.
  • a known CMP method is preferable. Specifically, A 1 2 0 3 and a slurry containing abrasive grains and H 2 0 2 of any oxidizing agent such as, using a polishing Pas head consisting of foamed polyurethane or the like, the metal layer M 1 in the portion of high altitude difference Only selective removal. At this time, the metal layer remaining in the peripheral circuit area having a low elevation difference may be cut off. To prevent this, a strip film using a material whose polishing rate is relatively smaller than the wiring metal may be formed in advance on the metal layer in the peripheral circuit area.
  • a flattening technique using a grindstone in which abrasive grains are combined with a resin instead of the polishing pad and the slurry may be used.
  • the flattening performance of the grindstone is good, so that it is not always necessary to use the stopper film.
  • an etchback combining a photoresist and dry etching can be used as a method of leaving the metal layer M 1 in the peripheral circuit region.
  • This step eliminates the difference in elevation between the memory cell region and the peripheral circuit region, and the surfaces of both regions are kept flat.
  • the metal layer M 1 in the peripheral circuit region is patterned by using photolithography and dry etching to form a metal wiring 17.
  • this step only the metal layer M1 in the remaining peripheral circuit area is patterned, so that fine wiring can be easily added by photolithography using a commonly used reduced projection exposure apparatus.
  • the surface of the silicon oxide film 15 in the memory cell region is photo-etched so that the surface is not damaged by etching. It is advisable to design the pattern so that it is protected by the register.
  • a silicon oxide film 18 having a thickness of about 200 nm is deposited as an interlayer insulating film by a CVD method, and thereafter, a reflow process is performed.
  • a reflow process is performed.
  • the surface of the silicon oxide film 18 in the memory cell region and the peripheral circuit region is almost flattened. That is, the difference in elevation between the surfaces of the silicon oxide film 18 in both regions is reduced.
  • the metal wiring 19 is preferably a low-resistance metal such as aluminum, and as shown in FIG. Therefore, it can be used as a signal line connected to a data line or as a word bus.
  • a well-known Bragg technique or CMP method can be applied to flatten the interlayer insulating film 18.
  • the surface of the polycrystalline silicon film of the capacitor lower electrode 12 concave and convex, the surface area of the storage electrode can be increased, and a larger storage capacity can be obtained.
  • the surface forming method can be achieved by using disilane gas at the time of forming polycrystalline silicon.
  • the dynamic RAM IC of the present invention shown in FIG. 1 is completed.
  • the silicon oxide film 15 in the peripheral circuit region was removed using the formation pattern (register) of the upper electrode 14 of the capacitor as a mask, and the silicon oxide film 15 was removed.
  • a metal layer M 1 is embedded in the region.
  • the metal layer M 1 in the peripheral circuit area is patterned (the first layer). Since the photolithography is performed, the difference in elevation between the memory cell area and the peripheral circuit area can be eliminated without increasing the number of masks. Fine wiring patterning can be performed simultaneously. That is, at the time of exposure, the resolution can be made the same in the memory cell area and the peripheral circuit area, and the problem of causing poor resolution in one of the areas can be solved.
  • the metal wiring 19 is the MIS F of the peripheral circuit region.
  • the silicon oxide films 15 and 18 used in the present embodiment may be insulating films having good flatness other than the silicon oxide films.
  • a spin-on-glass (SOG) film can be considered.
  • the present embodiment relates to a method of supplying power to the capacity in the dynamic RAM of the first embodiment, and the configuration is shown in FIG. Figure 15 shows a cross-sectional view of the connection between the end of the memory cell array and the wiring electrode.
  • openings are provided in the silicon oxide films 15 and 18 on the upper electrode 14 of the capacity, and the metal wiring 19 is connected.
  • the lower electrode 12 of the capacitor is disposed below the upper electrode 14, and the upper electrode 1 is placed in the gap between the crown-shaped lower electrode 12 by adjusting the thickness of the upper electrode 14. Since 4 is embedded, there is no problem if an opening is formed in this portion.
  • the opening for supplying power to the capacitor can be provided above the step of the capacitor, the aspect ratio of the opening can be reduced, and the metal wiring 1 9 can be easily connected to the upper electrode 14 of the capacitor.
  • FIG. 16 is a cross-sectional view of the memory cell region and the peripheral circuit region, similarly to FIG.
  • the silicon oxide film 15 covering the upper electrode 14 of the capacity in the memory cell region is partially removed at a portion where the step of the lower electrode 12 is high.
  • a known method such as etch back can be used.
  • the upper electrode 14 of the capacitor is used as a common plate electrode for the capacitors of a plurality of memory cells, and is almost entirely covered in the memory cell region.
  • a plate electrode 16 serving as a power supply wiring to the capacitor is formed on the exposed upper electrode 14 of the capacitor.
  • an opening (contact hole) CH is formed in the silicon oxide film 18 on the plate electrode 16.
  • a metal wiring 19 (Vp) is formed on the silicon oxide film 18 and is connected to the plate electrode 16 of the capacitor via the opening CH.
  • the opening CH for feeding the capacity can be provided above the step of the capacity, so that the aspect ratio of the opening is reduced. can do. Therefore, the metal wiring 19 (Vp) can be easily connected to the upper electrode 14 of the capacitor.
  • the wiring electrode 7 used for the memory cell data line is used as the first wiring layer of the peripheral circuit region.
  • This embodiment will be described with reference to the process sectional views shown in FIGS.
  • the steps shown in FIGS. 17 to 19 are exactly the same as the steps shown in FIGS. 3 to 5 of the first embodiment except that the wiring electrode 7 is formed in the peripheral circuit region.
  • a silicon oxide film 8 containing boron and phosphorus and having a thickness of about 20 O nm is deposited by a CVD method as shown in FIG.
  • the silicon oxide film 8 is annealed at a temperature of about 800 ° C. to smooth the surface.
  • openings 32 are formed in the silicon oxide films 6 and 8 on the high-concentration n-type impurity region 5 serving as the source or drain of the MISFET by photolithography and dry etching.
  • a polycrystalline silicon film with a thickness of about 200 nm doped with an impurity of the same conductivity type as the high-concentration n-type impurity 5 at a high concentration is deposited by LPCVD. Silicon plug by etching back with anisotropic dry etching Form 9.
  • a silicon nitride sulfide film 10 having a thickness of about 10 Om is deposited by the LPCVD method.
  • the silicon nitride film 10 is formed for the same reason as described in the first embodiment.
  • a silicon oxide film 22 is deposited on the silicon nitride film 10 by a known CVD method using a TEOS gas, and is then formed by photolithography and dry etching.
  • the oxide film 22, silicon nitride film 10 and silicon oxide film 8 are sequentially etched to form an opening (contact hole) CH, and a metal plug 23 is formed in the opening CH by a known method.
  • a metal plug 23 is formed in the opening CH by a known method.
  • a material of the metal plug a high melting point metal material, for example, tungsten is desirable.
  • a silicon nitride sulfide film 24 having a thickness of about 50 Onm is deposited by a known plasma CVD method. Then, an opening 26 is formed by selectively etching the silicon nitride film 24 and the silicon oxide film 22 at a portion where a capacity is to be formed by photolithography and dry etching.
  • a polycrystalline silicon is left in the opening 26 as the lower electrode 12 of the capacitor in the same manner as in the first embodiment.
  • the silicon nitride film 24 is etched by dry etching. Further, the silicon oxide films 21 and 22 in the memory cell region are etched by photolithography and jet etching to form a lower electrode 12 of a crown-shaped capacitor. The lower electrode 12 of the capacitor was left in the opening.
  • a photoresist can be used as an etching mask.
  • Capacitor dielectric film 1 3 consists of T a 2 0 5 in the same manner as in Example 1.
  • the step of forming a flat silicon oxide film 15 by TEOS is the same as that in the first embodiment.
  • the silicon oxide film 15 and the upper electrode 14 of the capacitor and the dielectric film 13 of the capacitor were patterned by photolithography and dry etching. Etch.
  • a metal layer Ml having a thickness of about 700 nm is deposited by using a known sputtering device.
  • the metal layer Ml is left in the peripheral circuit region where the silicon oxide film 15 has been removed. This step employs the same means as in the first embodiment.
  • the metal wiring 17 in the peripheral circuit region is formed by patterning the metal layer Ml using photolithography and dry etching in the same manner as in the first embodiment. .
  • a silicon oxide film 18 having a thickness of about 200 nm is deposited as an interlayer insulating film. Then, after an opening (through hole) CH is formed in the silicon oxide film 18 on the metal wiring 17 in the peripheral circuit region, a metal wiring 19 is formed, and the dynamic RAM of the present embodiment is formed. Complete.
  • the bit lines in the memory cell area and the pattern By using the first-layer wiring electrode 7 of the formed peripheral circuit region as a local wiring, the required area of the peripheral circuit region can be reduced.
  • the depth of the metal plug 23 can be reduced, the production of the metal plug 23 can be facilitated and the yield can be improved.
  • FIG. 31 is a diagram showing a cross-sectional structure of a memory cell region and a peripheral circuit region of a dynamic RAM according to the present embodiment.
  • the lower electrode 27 of the capacitor is made of a thick polycrystalline silicon having a thickness of 500 nm.
  • the embodiment is the same as the manufacturing process of the embodiment 1 shown in FIGS. 10 to 14 except that the structure of the lower electrode 27 of the capacitor is different.
  • the lower electrode (storage electrode) 27 of the capacitor is patterned to have a predetermined film thickness.
  • the upper surface and the side wall of the lower electrode 27 are covered with a capacitor dielectric film 13.
  • an upper electrode (plate electrode) 14 of the capacitor is formed on the dielectric film 13.
  • the silicon oxide film 15 is used to flatten the steps in the capacity.
  • the silicon oxide film 15 in the peripheral circuit region is etched.
  • the mask pattern at the time of this etching is also the pattern of the upper electrode of the capacitor.
  • a metal layer Ml is buried in the peripheral circuit region where the silicon oxide film 14 has been etched.
  • the metal layer Ml is patterned by photolithography and dry etching to form a metal wiring 17.
  • a silicon oxide film 18 is deposited by the CVD method to reduce the level difference between the memory cell area and the peripheral circuit area.
  • a method of supplying a plate potential to the upper electrode in the capacity is not shown, but an opening for supplying power is formed in the relatively thin silicon oxide film 15 located on the thick lower electrode 27. In other words, an opening is formed at a position where the step of the capacitor is high. This makes it possible to reduce the aspect ratio of the opening, thereby facilitating the formation of the opening.
  • the storage capacitance can be increased only by increasing the thickness of the lower electrode 27 in the capacity.
  • the present embodiment is another embodiment of the electrode for the capacitance in the dynamic RAM of the first embodiment, and the configuration is shown in FIG. Fig. 36 shows the memory cell part and its surroundings of the dynamic RAM according to the present embodiment.
  • FIG. 3 is a diagram illustrating a cross-sectional structure of a circuit unit.
  • the lower electrode 28 of the capacitor is made of a 50 nm-thick polycrystalline silicon film embedded in the opening formed in the silicon oxide film 15. Further, the lower electrode 28 is connected to the silicon plug 9 at the bottom of the opening.
  • the capacitance of the storage electrode can be increased by increasing the thickness of the silicon oxide film 15, that is, by increasing the depth of the opening.
  • FIG. 37 first, a field oxide film 2 is selectively formed on a silicon substrate 1 by a known L0C0S technique. Then, MISFET is formed in a region where the field oxide film 2 is not formed (a portion called an active region). Next, a silicon plug 9 and a metal plug 11 are formed. Then, the main surface on the semiconductor substrate on which the Ml SFET is formed with the silicon oxide film 15 is planarized. That is, the altitude difference between the memory cell area and the peripheral circuit area is reduced.
  • an opening 29 is formed by photolithography and dry etching at a position of the silicon oxide film 15 where the capacity electrode is to be formed.
  • the steps so far are exactly the same as in Example 1.
  • a 50-nm-thick polycrystalline silicon film doped with n-type impurities at a high concentration is deposited, and the photoresist and etch-back are combined to form the opening.
  • the polycrystalline silicon film is left in the portion 29 to form the lower electrode 28 of the capacitor.
  • the lower electrode 28 of this capacitor has a silicon capacitor at the bottom of the opening 29. Connected to lug 9.
  • a capacitor dielectric film 13 is deposited, and a titanium nitride film having a thickness of lOO nm is deposited on the dielectric dielectric film 13 as an upper electrode 14 of the capacitor. .
  • the titanium nitride film 14, the capacitor dielectric film 13, and the silicon oxide film 15 were formed by photolithography and dry etching with the upper electrode pattern of the capacitor. Etching.
  • the metal layer Ml made of aluminum is left in the peripheral circuit region as in the first embodiment.
  • a metal wiring 17 is formed by patterning the metal layer Ml.
  • the present embodiment is a further embodiment of the electrode for the capacitance in the dynamic RAM of the first embodiment.
  • the configuration is shown in FIG. FIG. 42 is a diagram showing a cross-sectional structure of a memory cell portion and a peripheral circuit portion of the dynamic RAM according to the present embodiment.
  • the present embodiment is characterized in that the lower electrode 30 of the capacitor is of a fin type.
  • the storage capacity can be increased by increasing the number of fins of the lower electrode 30 of the capacity.
  • FIG. 43 is a diagram showing a cross-sectional structure of a memory cell region and a peripheral circuit region of the dynamic RAM according to the present embodiment.
  • a crown-shaped capacitor composed of a lower electrode 12, a dielectric film 13, and an upper electrode 14 is formed in the memory cell region.
  • the first-layer metal wiring 17 in the peripheral circuit region is formed in a region where the silicon oxide film 15 is removed as in the first embodiment.
  • a silicon oxide film 31 is formed on the metal wiring 17, and the height of the metal wiring 17 and the height of the silicon oxide film 15 deposited on the capacity of the memory cell region are adjusted. I have. That is, the film thickness (total film thickness) of the metal wiring 17 and the silicon oxide film 31 is equal to the film thickness of the silicon oxide film 15. In this embodiment, as in the first embodiment, even if the depth (thickness) of removing the silicon oxide film 15 is within a range of about 0.3 m deeper than the total film thickness. Good.
  • the elevation difference between the memory cell region and the peripheral circuit region can be made substantially equal.
  • dry etching is facilitated, and a fine pattern can be formed.
  • FIG. 44 shows an embodiment of the planar layout of the dynamic RAM chip according to the present invention.
  • a peripheral circuit part 218 is arranged in a cross shape so as to surround the part 216.
  • the MISFET in the memory cell part 216 is of an n-channel type.
  • a CMOS circuit constitutes an input / output circuit / decoder circuit and an address circuit.
  • an interlayer insulating film 2 17 (first or second interlayer insulating film) is formed so as to penetrate the peripheral circuit section 2 18.
  • a bonding pad BP is linearly provided on the main surface of the peripheral circuit portion 218 located at the longitudinal center of the chip 201.
  • FIG. 45 shows another embodiment of the planar layout of the dynamic RAM chip according to the present invention.
  • the dynamic RAM chip shown in Fig. 45 constitutes a large-capacity DRAM of 1 gigabit or more.
  • a plurality of memory cell array portions 2 16 are surrounded by a peripheral circuit portion 2 18 on the outer periphery of the chip and a peripheral circuit portion 2 18 in the X1, X2 and Yl, ⁇ 2 directions.
  • the peripheral circuit section 218 has an interlayer insulating film 217 (second interlayer insulating film) formed so as to penetrate the memory cell array section 216.
  • the MISFET in the memory cell part 216 is of an n-channel type.
  • a CMOS circuit constitutes an input / output circuit, a decoder circuit and an address circuit.
  • the bonding pads BP are arranged in a row (X1 or X2) or two rows (one row) on the peripheral circuit part 218 main surface located in the longitudinal direction X1, X2 direction of the chip 201. 2) is provided linearly.
  • the DRAM chip described in the present embodiment can be used for SOJ (Small Outline J-leaded Package), SOP (Small Outline Package), It can be incorporated into small packages such as TSOP (Thin-SOP) and even CSP (Chip Size Package).
  • the memory cell region is, for example, a single transfer MISFET and a charge storage capacitor (capacitance) as a unit memory cell, and a plurality of memory cells are regularly arranged in one semiconductor chip. It refers to the area where it is located.
  • the memory cell area can be referred to as a memory cell group or a memory array section.
  • the memory cell array also includes a plurality of dummy cells.
  • the peripheral circuit region means a portion arranged around the memory cell region (memory cell array), for example, an addressless decoder, an input / output buffer, and the like.
  • the present invention is applied to a dynamic RAM.
  • a wiring layer of a logic part can be formed at a height where a capacity is formed.
  • the use of a low-resistance metal material such as copper as the wiring layer formed on the memory cell region and the wiring layer formed on the peripheral circuit region enables a higher-speed operation.
  • a low-resistance metal material such as copper
  • the wiring layer formed on the peripheral circuit region enables a higher-speed operation.
  • Is possible half Conductor storage device can also be provided

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  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

Afin d'augmenter la capacité de stockage d'un condensateur, ce dernier est constitué d'une structure tridimensionnelle allongée, composée d'une électrode inférieure (12), d'une couche diélectrique (13) et d'une électrode supérieure (14). Afin d'atténuer la différence de hauteur entre la zone de la cellule mémoire dans laquelle est placé le condensateur et sa zone de circuit périphérique, on dépose une couche isolante (15) sur lesdites zones et on l'enlève uniquement de la zone du circuit périphérique, puis on enfouit une couche métallique (M1) uniquement dans la zone dont on a enlevé la couche isolante (15). Une fois la couche métallique (M1) enfouie, on forme un câblage métallique (17) en dessinant un motif dans la couche métallique (17) par photolithographie et gravure à sec.
PCT/JP1996/003735 1996-12-20 1996-12-20 Dispositif memoire a semi-conducteur et procede de fabrication associe WO1998028789A1 (fr)

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PCT/JP1996/003735 WO1998028789A1 (fr) 1996-12-20 1996-12-20 Dispositif memoire a semi-conducteur et procede de fabrication associe
TW086110894A TW351853B (en) 1996-12-20 1997-07-30 Method and apparatus for making semiconductor device

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PCT/JP1996/003735 WO1998028789A1 (fr) 1996-12-20 1996-12-20 Dispositif memoire a semi-conducteur et procede de fabrication associe

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9076678B2 (en) 2011-07-14 2015-07-07 Ps4 Luxco S.A.R.L. Semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02162763A (ja) * 1988-12-15 1990-06-22 Fujitsu Ltd 半導体装置及びその製造方法
JPH07142597A (ja) * 1993-11-12 1995-06-02 Mitsubishi Electric Corp 半導体記憶装置およびその製造方法
JPH07508136A (ja) * 1992-06-30 1995-09-07 シーメンス アクチエンゲゼルシヤフト 深皿形コンデンサの製造方法
JPH0855968A (ja) * 1994-08-10 1996-02-27 Hitachi Ltd 半導体集積回路装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02162763A (ja) * 1988-12-15 1990-06-22 Fujitsu Ltd 半導体装置及びその製造方法
JPH07508136A (ja) * 1992-06-30 1995-09-07 シーメンス アクチエンゲゼルシヤフト 深皿形コンデンサの製造方法
JPH07142597A (ja) * 1993-11-12 1995-06-02 Mitsubishi Electric Corp 半導体記憶装置およびその製造方法
JPH0855968A (ja) * 1994-08-10 1996-02-27 Hitachi Ltd 半導体集積回路装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9076678B2 (en) 2011-07-14 2015-07-07 Ps4 Luxco S.A.R.L. Semiconductor device

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