WO1997035226A1 - Dispositif d'affichage a cristaux liquides - Google Patents

Dispositif d'affichage a cristaux liquides Download PDF

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Publication number
WO1997035226A1
WO1997035226A1 PCT/JP1996/000683 JP9600683W WO9735226A1 WO 1997035226 A1 WO1997035226 A1 WO 1997035226A1 JP 9600683 W JP9600683 W JP 9600683W WO 9735226 A1 WO9735226 A1 WO 9735226A1
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WIPO (PCT)
Prior art keywords
gate line
line
gate
drain
layer
Prior art date
Application number
PCT/JP1996/000683
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English (en)
Japanese (ja)
Inventor
Nobuyuki Suzuki
Yoshiaki Nakayoshi
Kikuo Ono
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1996/000683 priority Critical patent/WO1997035226A1/fr
Publication of WO1997035226A1 publication Critical patent/WO1997035226A1/fr

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present invention relates to an active matrix liquid crystal display device using a thin film transistor.
  • FIG. 2 shows an example of a conventional active matrix substrate
  • FIG. 25 is a sectional view of an active matrix liquid crystal display device.
  • the active matrix substrate shown in Fig. 2 has gate lines (GL1, GL2) and drain lines (DL) formed vertically and horizontally on a transparent insulating substrate, and gate lines (GL1, GL2).
  • a pixel electrode (PE) is formed in a region surrounded by the gate electrode and the drain line (DL).
  • the pixel electrode (PE) is applied to the drain line via a thin-film transistor (hereinafter abbreviated as TFT) near the intersection of the gate line (GL1, GL2) and the drain line (DL).
  • TFT thin-film transistor
  • the gate line (GL 1) of the first layer is composed of, for example, A1
  • the gate line (GL 2) of the second layer and the gate electrode (GE) integrated therewith are, for example, C r It consists of.
  • the pixel electrode (PE) is made of amorphous ITO or the like.
  • the gate electrode (GE)-and part of the pixel electrode (PE), a gate insulating film made of SiNx or the like is formed on the gate lines (GL1, GL2), the gate electrode (GE)-and part of the pixel electrode (PE), a gate insulating film made of SiNx or the like is formed.
  • An i-type semiconductor layer (AS) made of amorphous silicon or the like is formed on the gate electrode (GE) so as to overlap the drain electrode (DE) and the source electrode (SE). ⁇ N-type semiconductor and Cr etc. to overlap the semiconductor layer (AS)
  • the TFT is formed by the gate electrode (GE), the gate insulating film, the i-type semiconductor layer (AS), the drain electrode (DE), and the source electrode (SE).
  • the drain electrode (DE) is electrically connected to the drain line [DL] formed integrally therewith, and the source electrode (SE) is electrically connected to the pixel electrode (PE).
  • An additional capacitance electrode (Cadd) is formed on the gate line using the same material as the drain line (DL :), which is located across the gate lines (GL1, GL2). Of the two pixel electrodes (PE), the pixel electrode (PE) to which the TFT is not connected is electrically connected to form an additional capacitance.
  • the gate lines (GL1, GL2), the drain line (DL), part of the pixel electrode (PE), and the TFT are covered with a protective film (PAS) formed thereon.
  • an opposing transparent substrate (COMSUB) is provided so as to oppose the active matrix substrate (TFTSUB) configured as described above.
  • This opposing transparent substrate is provided so as to oppose the active matrix substrate (TFTSUB) configured as described above.
  • the counter electrode (CE) is formed on the C OMS UB, and the alignment film (AL) force is applied to the surface of each substrate facing each other ⁇
  • liquid crystal (LC) is sealed between the active matrix substrate (TFTSUB) and the transparent counter substrate (COM SUB) to form an active matrix liquid crystal display device.
  • Active matrix liquid crystal display devices are currently used in portable information terminals such as notebook personal computers, and in recent years, monitors for personal computers with a diagonal dimension of 30 cm or more, and a direct-view height of 50 cm in the diagonal dimension. Applications to high-definition televisions are being considered, and increasing the screen size is urgently needed.
  • the problem at that time is that the active matrix substrate This is to reduce the resistance of the gate line. At this time, since there is a demand from the market to reduce the wiring area on the active matrix substrate at the same time, it is essential to select a material with low specific resistance as the gate line material.
  • the gate voltage of the TFT is set to the threshold value Vth or more, and conduction between the source and drain is performed.
  • the gradation voltage was written from the line to the corresponding pixel electrode.
  • the gate drive waveform of the TFT at the end opposite to the gate terminal is distorted as shown in FIG. 26b due to the influence of the gate wiring resistance and the wiring capacitance of the gate wiring.
  • gate wiring As a method of reducing the gate wiring resistance, as disclosed in JP-A-61-93488, JP-A-61-29820 and JP-A-62-274747, gate wiring is disclosed. Has a two-layer structure.
  • the first layer gate line (GL 1) and the second layer gate line (GL 2) When misalignment occurs, the drain line (D line) is determined by the fact that the edge on one side of the gate line (GL 1) of the first layer and the gate line (GL 2) of the second layer substantially coincide with each other. ), The step over the gate lines (GL1, GL2) increases, and the drain line (DL) breaks. Therefore, in order to prevent the disconnection failure of the drain line (DL :), the width of the gate line (GL2) of the second layer should be larger than the width of the gate line (GL1 :) of the first layer. It is necessary to keep it considerably wide, and there is a problem that the wiring area increases.
  • the present invention reduces the width of the first-layer gate line (GL 1 only at the intersection with the drain line (DL) on the active matrix substrate to form a large active matrix substrate. It is intended to improve the yield when manufacturing a liquid crystal display device industrially and to improve the image quality of a large active matrix liquid crystal display device.
  • the width of the gate line (GL 1) of the second layer is small near the intersection with the drain line (DL), so that the gate line (GL 2) of the second layer is small.
  • the edge on one side of the second-layer gate line (GL 2) substantially coincides, and the step formed by the two-layer gate line does not increase.
  • the gate insulating film (GI) formed on (GL 2) does not cause deposition failure.
  • the width of the first-layer gate line (GL1) is increased at portions other than the vicinity of the intersection with the drain line (D) so that the gate line formed on the active matrix substrate can be formed. Can be reduced.
  • the drain line (DL) formed thereon is Deposition over the gate line (GL 1) And the disconnection of the drain line (DL) can be reduced.
  • FIG. 1 is a top view of an active matrix substrate according to a first embodiment of the present invention.
  • FIG. 2 is a plan view of a conventional active matrix substrate.
  • FIG. 3 is a cross-sectional view of the intersection of the drain line and the gate line of the active matrix substrate according to the first and second embodiments of the present invention, and corresponds to the cross section taken along the line AA ′ in FIGS. I do.
  • FIG. 4 is a cross-sectional view of the TFT part of the active matrix substrate according to the first embodiment of the present invention, and corresponds to a cross section BB ′ of FIG.
  • FIG. 5 is a sectional view of an additional capacity portion of the active matrix substrate according to the first embodiment of the present invention, and corresponds to a section taken along line CC ′ of FIG.
  • FIG. 6 shows a cross section of a drain line and a gate line of an active matrix substrate in which a self-oxidized film is formed on the surface of a second-layer gate line in the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of a portion, which corresponds to a cross section taken along line AA ′ of FIG.
  • FIG. 7 is a cross-sectional view of a TFT portion of an active matrix substrate having a self-oxidized film formed on the surface of a second-layer gate line according to the first embodiment of the present invention. And it corresponds to the cross section B-B 'in FIG.
  • FIG. 8 is a cross-sectional view of an additional capacitance portion of an active matrix substrate in which a self-oxidized film is formed on the surface of a second-layer gate line in the first embodiment of the present invention. Corresponds to the C-C 'section of 1.
  • FIG. 9 is a plan view of a gate terminal portion of the active matrix substrate according to the first embodiment of the present invention.
  • FIG. 10 is a sectional view of a gate terminal portion of the active matrix substrate according to the first embodiment of the present invention, and corresponds to a section taken along line DD ′ of FIG. G
  • FIG. 11 is a plan view of a drain terminal portion of the active matrix substrate according to the first embodiment of the present invention.
  • FIG. 12 is a cross-sectional view of the drain end-f portion of the active matrix substrate according to the first embodiment of the present invention, and corresponds to a cross section taken along line EE ′ of FIG.
  • FIG. 13 is a plan view of an active matrix substrate according to a second embodiment of the present invention.
  • FIG. 14 is a cross-sectional view of the TFT part of the active matrix substrate according to the second embodiment of the present invention, and corresponds to a cross section taken along line BB ′ of FIG.
  • FIG. 15 is a cross-sectional view of the additional capacitance portion according to the second embodiment of the present invention, and corresponds to a cross section taken along line CC ′ of FIG.
  • FIG. 16 is a cross-sectional view of a TFT portion of an active matrix substrate in which a self-oxidized film is formed on a second-layer gate line surface in the second embodiment of the present invention. Corresponds to B-B 'section.
  • FIG. 17 is a cross-sectional view of an additional capacitance portion of an active matrix substrate in which a self-oxidized film is formed on the surface of a second-layer gate line in the second embodiment of the present invention. This corresponds to the C 1 -C ′ section of 13.
  • FIG. 18 is a plan view of a gate terminal portion according to the second embodiment of the present invention.
  • FIG. 19 is a sectional view of a gate terminal portion according to the second embodiment of the present invention, and corresponds to a section taken along line DD ′ of FIG.
  • FIG. 20 is a plan view of a drain terminal portion according to a second embodiment of the present invention.
  • FIG. 21 is a cross-sectional view of the drain terminal portion in the second embodiment of the present invention, and corresponds to a cross section taken along line E--E 'of FIG.
  • [3 ⁇ 422 denotes an active matrix substrate according to the third embodiment of the present invention.
  • FIG. 23 is a diagram showing a state in which a second-layer gate line (GL2) is deposited on a first-layer gate line (GL1).
  • FIG. 24 is a plan view of an active matrix substrate according to a fourth embodiment of the present invention.
  • FIG. 25 is a sectional view of a conventional active matrix liquid crystal display device.
  • FIG. 26a is a diagram showing a drive voltage waveform applied to the gate of the TFT on the gate terminal side.
  • FIG. 26B is a diagram showing a drive voltage waveform applied to the TFT gate on the opposite side of the gate terminal.
  • FIG. 1 is a plan view showing a configuration example of the active matrix substrate of the first embodiment.
  • FIG. 3 is a sectional view taken along the line A--A of FIG. 1
  • FIG. 4 is a sectional view taken along the line B--B ', and FIG. It is sectional drawing along.
  • the substrate (SUB) is made of glass.
  • a first-layer gate line (GL1) is formed on this substrate (SUB).
  • the gate line (GL1) of the first layer may be, for example, a force of A1 having a film thickness of about 300 nm, a compound of A1 and Ti or Ta, or the like.
  • the gate line (GL 1) of the first layer may be a material having a low resistivity, and may be Au, Ag, or Cu.
  • the gate line (GL 2) of the second layer may be, for example, a metal composed of Cr with a thickness of about 60 nm and a metal having a melting point of 1000 ° C. or more, such as Cr, o, W, Ta or These compounds may be used.
  • the pixel electrode (PE) is formed on the transparent insulating substrate (SUB).
  • This pixel electrode (PE) is formed by forming an amorphous ITO with a film thickness of about 150 nm at a substrate temperature of 200 ° C. or more. It may be a polycrystalline ITO formed as a film.
  • the gate insulating film is made of S i Nx film thickness, for example about 300 nm, or a stacked structure of S i 0 2 film Ya 3 i Nx film and S i 0 2 film.
  • a second-layer gate line (GL 2) is formed of Ta, and as shown in FIG. 6, the surface of the second-layer gate line (GL 2) is formed by means of anodic oxidation or the like.
  • an oxide film (A 0 F) is formed, the interlayer insulating film of the second-layer gate line (GL 2) and drain line (DL) is changed to a gate insulating film (GI ) And a self-oxidized film (AOF) of the second-layer gate line.
  • GI gate insulating film
  • OAF self-oxidized film
  • the cross section BB ′ of FIG. 1 is formed by the gate electrode (GE :) as shown in FIG. And the gate electrode (GE) and the source electrode (SE), and the gate insulating film (GI) and the gate electrode self-oxidation film (AOF). It becomes a laminated film, and a gate insulating film (GI has minute defects such as pinholes) ;)
  • the gate electrode (GE) and the drain electrode (DE) and the gate electrode (GE) and the source electrode (SE) are not electrically short-circuited. Also, when the misalignment of the pixel electrode (PE) and the gate electrode (GE occurs and the gate electrode (GE) and the pixel electrode (PE) overlap, the self-oxidation film (AOF ) Does not cause an electrical short circuit between the pixel electrode (PE :) and the gate electrode (GE), which makes it possible to form a large pixel electrode (PE.).
  • the cross section taken along the line CC ′ in FIG. 1 also has a structure as shown in FIG.
  • the body also becomes a laminated film of the gate insulating film (GI) and the self-oxidized film (AOF) of the second gate line. If the gate insulating film (GI) has minute defects such as pinholes In this case, the additional capacitance electrode (C add) and the gate line (GL 2) of the second layer are not electrically short-circuited, and the pixel electrode (PE) and the gate line of the second layer (GL 2) are not electrically shorted.
  • the GL 2) is insulated by the self-oxidizing film (AOF) of the second layer gate line, the alignment of the pixel electrode (PE) and the second layer gate line (GL 2) Even when the displacement occurs and the gate line (GL 2) of the second layer and the pixel electrode (PE) overlap, the pixel electrode (PE) and the gate line (GL 2) of the second layer are electrically connected. Large pixel electrode (PE) Rukoto is possible.
  • Ta is used for the second-layer gate line (GL2), and a self-oxidized film is formed on the surface thereof, so that the transparent insulating substrate (PE) of the pixel electrode (PE) is formed.
  • SUB can be increased. This makes it possible to provide a liquid crystal display device having a high transmittance.
  • an i-type semiconductor layer (AS) is formed on the gate insulating film so as to cover the above-mentioned gate electrode (GE).
  • a force composed of an amorphous silicon film having a thickness of about 150 nm ⁇ a polycrystalline silicon film may be used.
  • a drain electrode (DE) and a source electrode (SE) are formed so as to overlap the i-type semiconductor layer (AS).
  • the drain electrode (DE) and the source electrode (SE) have a film thickness of, for example, about 200 :! ! ! Mo or a compound of Cr and Mo may be used in place of the force ⁇ C r composed of r, and A 1 2 in which Cr and Si are mixed in order from the side closer to the i-type semiconductor layer. It may have a layered structure.
  • the drain electrode (DE) and the source electrode (SE) may be Ti, Ta, or a laminated film thereof instead of Cr. Also, when a laminated film in which Ta is laminated on Nb is used, Ta becomes Ta, which has the effect of lowering the resistance of the drain electrode (DE) and the source electrode (SE).
  • i-type semiconductor layer AS
  • DE drain electrode
  • the metal-semiconductor contact layer (N +) is formed between the i-type semiconductor layer (AS), the drain electrode (DE), and the source electrode (SE) in the overlapping portion of (SE). .
  • amorphous silicon film which has the property of an N-type semiconductor by adding 20 nm of P, but may be made of an additive such as As.
  • the TFT shown in Fig. 4 is formed by the gate electrode (GE;), i-type semiconductor layer (AS), drain electrode (DE), and source electrode (SE) created as described above.
  • source electrode (SE) and the above-mentioned pixel electrode (PE) are electrically connected.
  • the drain line (DL) may have a three-layer structure of, for example, a Cr ⁇ -type semiconductor layer, an N-type semiconductor layer, and Cr having a thickness of about 200 nm. Also, instead of Cr, Mo and Cr A Mo compound or a laminate of Cr and A 1 Si may be used.
  • the drain line (DL) may be Ti, Ta, or a laminated film thereof instead of Cr.
  • Ta becomes Ta, which has the effect of lowering the resistance of the drain line (DL).
  • the drain line (DL) and the drain electrode (DE) are electrically connected by integrally forming a part made of the metal and the metal compound.
  • the additional capacitance electrode (C ad d) may be, for example, a Cr-force of about 200 nm in thickness, a compound of Cr and Mo, or a laminate of Cr and A 1 Si.
  • the additional capacitance electrode (C a d d) may be Ti, Ta or a laminated film thereof instead of Cr. When a laminated film in which Ta is laminated on Nb is used, Ta becomes ⁇ Ta, and the resistance of the additional capacitance electrode (C a d d) can be reduced. As shown in Fig.
  • this additional capacitance electrode (Cadd) is connected to the gate electrode (GL1, GL2) between the two pixel electrodes (PE) that are not connected to the TFT. It is electrically connected to the pixel electrode (PE) and forms an additional capacitance with the gate lines (GL1, GL2).
  • This type of liquid crystal display device that forms additional capacitance between the pixel electrode (PE) and the gate lines (GL1, GL2) (hereinafter abbreviated as “additional capacitance type”) does not require wiring dedicated to additional capacitance.
  • the gate line of the liquid crystal display device of the additional capacitance type has the two-layer structure of the gate line (GL 1) of the first layer and the gate line (GL 2) of the second layer shown in FIG. By doing so, the problem of the distortion of the gate drive waveform is improved and the transmittance is high. A liquid crystal display device without display unevenness can be provided.
  • A1 for the gate line (GL1) of the first layer it is possible to further reduce the distortion of the gate drive waveform.
  • metals such as A1 whose melting point is close to the film formation temperature in CVD equipment (hereinafter, metals with a melting point of 1000 ° C or less are called low-melting metals, and metals with a melting point of 100 ° C or more are called high-melting metals :) It is known that when a film is formed on a CVD apparatus, columnar crystal abnormalities called hillock-Heuss force occur in the metal. This is due to the difference in the diffusion coefficient of the metal and the stress between the metal and the film formed thereon.
  • the height of this columnar crystal anomaly often reaches several; m, causing a short circuit between the gate line and the drain line, a short circuit between the gate line and the additional capacitance electrode, and a short circuit between the gate line and the counter electrode.
  • the short circuit between the gate line and the counter electrode can be corrected by burning off the columnar crystal anomaly with a laser beam.
  • the short circuit between the gate line and the drain line and the short circuit between the gate line and the additional capacitance electrode are the same. Since it occurs on the substrate, it is difficult to correct it, which is one of the causes of a decrease in the yield when manufacturing the active matrix substrate industrially.
  • the gate line has a two-layer structure as shown in FIG. Covering with the second layer gate line (GL 2) suppresses the growth of columnar crystal abnormalities.
  • a 1 having a low specific resistance can be used as a material for the gate wiring, and the gate line and the drain line, and the gate line and the additional capacitance electrode are not short-circuited.
  • This protective film (PAS) is made of, for example, a SiNx film having a thickness of about 300 nm.
  • the liquid crystal layer is arranged in a certain direction on the protective film (PAS).
  • the orientation film to be oriented is formed so that the orientation film is not shown in FIGS. 3, 4, and 5.
  • the gate line (GL) and the drain line (DL) are connected to the surface element electrode (PE) at the periphery of the transparent insulating substrate (SUB).
  • the gate terminal (GTM) and the drain terminal (DTM) are formed of the same ITO as the pixel electrode (PE). Since ITO is resistant to corrosion, the gate terminal (GTM) and drain terminal (DTM) do not corrode.
  • a protective film made of SiNx
  • the gate line (GL 1) of the first layer is covered with not only the protective film (PAS) and the gate insulating film (GI) but also the gate wiring (GL 2) of the second layer. It does not come into contact with the outside air and corrode.
  • the width of the first-layer gate line (GL 1) is smaller at the intersection with the drain line (DL) than at other points, and the first-layer gate line (GL 1 and the second Even if there is misalignment between the gate line (GL 2) of the first layer and the edge of one side of the gate line (GL 1) of the first layer and the gate line (GL 2) of the second layer, As a result, the step formed by the gate line of the second layer does not become large, so that the gate formed on the gate line (GL 2) of the second layer can be prevented.
  • Insulation film (GI) Does not cause deposition failure, and the drain line (DL) formed on the gate line (GL 2) of the second layer does not cause deposition failure. Is not disconnected.
  • the first-layer gate line (GL 1) also has a drain. Near the intersection with the line (DL), it is completely covered by the second-layer gate line (GL2). This can prevent a short circuit between the gate line and the drain line due to the columnar heterocrystal of the first-layer gate line (GL1).
  • the width of the first-layer gate line (GL1) is wider than the vicinity of the intersection with the drain line (DL) than at the vicinity of the intersection, so that the resistance of the gate line is reduced. Can be achieved. Specifically, in the case of a vertical stripe type active matrix liquid crystal display device having a diagonal of 26 cm and a pixel count of 800 x 600, the width of the first-layer gate line (GL1) is set to the drain line (DL).
  • the width of the gate line of the first layer (GL 1) is the width of the gate line (GL 1) of the first layer Even outside the vicinity, the width can be reduced to about 3/5 compared to the case where the width is the same as the width near the intersection.
  • the wiring resistance was calculated assuming that the first-layer gate line (GL 1) was formed of 200 nm thick A1 and the second-layer gate line (GL 2) was formed of 60 nm thick Cr. did.
  • FIG. 13 is a plan view showing a configuration example of the active matrix substrate according to the second embodiment.
  • FIG. 3 is a line AA ′ of FIG. 13
  • FIG. 14 is a line BB ′
  • FIG. 'Is a sectional view along the line.
  • Fig. 13 and Fig. 1 The difference between Fig. 13 and Fig. 1 is that the pixel electrode (; PE) is not on a transparent insulating substrate (SUB), but on a protective film (PAS.).
  • the electrical contact between the pixel electrode (PE) and the source electrode (SE) is made by the protective film (PAS) on a part of the area where the pixel electrode (PE) and the source electrode (SE) overlap on a plane.
  • the contact is completed by providing a non-existent part (TH).
  • a source electrode is formed, a portion which is in electrical contact with the pixel electrode (PE) is formed so as not to use A1 or its compound.
  • the drain line (DL) and the pixel electrode (PE) are connected to the protective film (PAS).
  • the drain line (DL) and the pixel electrode (PE) are not electrically short-circuited due to misalignment.
  • the area occupied by the pixel electrode (PE) on the transparent insulating substrate (SUB) can be increased, and the transmittance of the liquid crystal display device can be increased.
  • the dielectric of the additional capacitance is a laminated film of the gate insulating film (GI) and the protective film (PAS), so that the additional capacitance electrode C add and the gate line (GL 2) are formed of the protective film ( PAS) ⁇
  • PAS protective film
  • a gate line (GL 2) of the second layer is formed of Ta, and as shown in FIGS. 16 and 17, the gate line (GL 2) of the second layer and the gate electrode (GE) are formed.
  • the second layer gate line (GL 2) and the drain line (DL), and the second layer gate line (GL 2) are added. It is possible to prevent an electrical short circuit between the capacitor electrode (C add), the gate electrode (GE) of the TFT, and the source electrode (SE) or the drain electrode (DE).
  • the gate insulating film (GI) is formed on the transparent insulating substrate (SUB) surface, and as shown in FIGS. 18 and 19, the peripheral portion of the transparent insulating substrate (SUB) is formed. Same as the second layer gate line (GL 2) and pixel electrode (PE) IB
  • the protective film (PAS) and the gate insulating film (GI) are processed at once to form the protective film (GN). Remove the PAS) and gate insulating film (GI ') and make electrical contact.
  • the terminal extraction part of the drain line (DL) is connected to the pixel electrode by the connection part (DCN) provided on the protective film (PAS) in the periphery of the transparent insulating substrate (SUB). It is electrically connected to the drain terminal (DTM) made of the same material as (PE).
  • the gate terminal (GTM) and the drain terminal (DTM) are formed of the same material as the pixel electrode (PE), ITO, the terminal is corroded. None.
  • the additional capacitance electrode (Cadd) may be, for example, a polycrystalline ITO made of an amorphous ITO having a thickness of about 150 nm. It is formed integrally with the pixel electrode (PE).
  • FIG. 22 is a plan view showing a configuration example of the active matrix substrate of the third embodiment.
  • FIG. 22 The difference between FIG. 22 and FIG. 1 is that the intersection of the first-layer gate line (GL 1) with the drain line (D-shaped) has a crank-like bent shape. .
  • the width of the gate line (GL 1) of the first layer is narrower near the intersection with the drain line (DL) than in other portions.
  • the intersection of the first-layer gate line (GL) and the drain line (DL) is bent like a crank so that the drain line (DL) is formed. ) Is longer than the gate line (GL 1) of the first layer.
  • the first layer It is possible to reduce stacking faults at the portion that goes over the gate line (GL 1), and it is possible to reduce disconnection faults at the drain line (D side).
  • the gate line (GL 1) of the first layer into a crank shape, the direction of the side wall of the gate line (GL 1) of the first layer becomes plural, The second-layer gate line (GL 2) formed thereon does not cause disconnection due to poor deposition at the step of the first-layer gate line (GL 1).
  • FIG. 23 is a diagram showing a state where the gate line (GL2) of the second layer is deposited.
  • the second-layer gate line (GL2) is formed by evaporating a metal such as Cr using a sputtering apparatus or the like. Therefore, the metal film deposits well on the side wall (A) of the first layer gate line (GL1) in the direction in which the metal particles PAT fly off, but the side wall (B) that becomes shadowy is deposited. Hard to do.
  • the gate line (GL 1) of the first layer is formed in a crank shape by forming the gate line (GL 1) of the first layer in the step of forming the drain line (DL).
  • Etching liquid penetrates from the side wall and drain line (DL) There is no problem to break the wire.
  • the gate line (GL 1) of the first layer in a crank shape, the effect of relaxing the stress acting between the drain line (DL) and the gate line (GL 1) of the first layer can be reduced.
  • the drain line (DL) is formed of Cr, disconnection of the drain line (DL) due to the tensile stress of Cr can be prevented.
  • FIG. 24 is a plan view showing a configuration example of the active matrix substrate of the fourth embodiment.
  • FIG. 24 is a modified example of FIG. 22.
  • the crank-like bent shape provided at the intersection of the first-layer gate line (GL 1) with the drain line (DL) shown in the third embodiment. 24 intersects with the drain line at 0 degrees ⁇ S ⁇ 90 degrees indicated by 0 in FIG.
  • crank-like bent shape provided at the intersection of the first-layer gate line (GL 1) with the drain line (DL) is smaller than that of the third embodiment.
  • the area occupied by the gate lines (GL1, GL2) on the active matrix substrate can be made smaller than in the third embodiment.
  • the width of the first-layer gate line (GL1) is changed to another part near the intersection with the drain line (DL).
  • the first layer The edge of one side of the gate line (GL 1) does not coincide with the gate line (GL 2) of the second layer.
  • the gate insulating film (GI) formed on the second-layer gate line (GL2) does not cause deposition failure, and the drain line (DL) Disconnection can be prevented.
  • the gate line (GL 1) of the first layer is completely covered by the gate line (GL 2) of the second layer near the intersection with the drain line (DL).
  • the gate line (GL1) of the columnar heterocrystal is formed on the gate line (GL1), the growth is suppressed by the gate line (GL2) of the second layer, and the gate line (GL1) of the columnar heterocrystal is formed.
  • GL 1 and GL 2) and the drain line (DL) can be prevented from being short-circuited.
  • the width of the gate line (GL 1) formed of a low-resistance metal of the first layer is made wider at portions other than the vicinity of the intersection with the drain line (DL) than at the vicinity of the intersection.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)

Abstract

On améliore le rendement d'un dispositif d'affichage à cristaux liquides en empêchant qu'une ligne de porte (GL1) de première couche ne chevauche une ligne de porte (GL2) de seconde couche et en réduisant le gradin d'une ligne de drain (DL) traversant la ligne de porte (GL1), et ensuite en empêchant la déconnexion par augmentation du degré de la marge d'alignement entre les lignes de porte (GL1, GL2) en rendant la largeur de la ligne de porte (GL1) de première couche, près des intersections avec les lignes de drain (DL), plus étroite que l'autre partie de la ligne (GL1). De plus, on empêche les court-circuits entre les lignes de porte (GL1 et GL2) ainsi que les lignes de drain (DL) provoqués par des cristaux colonnaire anormaux à l'aide de la ligne de porte (GL2) supprimant le tirage de cristaux colonnaire anormaux dans la ligne de porte (GL1). En outre, on empêche la déconnexion des lignes de drain (DL) par réduction du gradin de la ligne de porte (GL1) traversant les lignes de drain (DL) du fait des intersections coudées entre les lignes de drain (DL) et la ligne de porte (GL1).
PCT/JP1996/000683 1996-03-15 1996-03-15 Dispositif d'affichage a cristaux liquides WO1997035226A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP1996/000683 WO1997035226A1 (fr) 1996-03-15 1996-03-15 Dispositif d'affichage a cristaux liquides

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1996/000683 WO1997035226A1 (fr) 1996-03-15 1996-03-15 Dispositif d'affichage a cristaux liquides

Publications (1)

Publication Number Publication Date
WO1997035226A1 true WO1997035226A1 (fr) 1997-09-25

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1996/000683 WO1997035226A1 (fr) 1996-03-15 1996-03-15 Dispositif d'affichage a cristaux liquides

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Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11520198B2 (en) 2020-10-27 2022-12-06 Seiko Epson Corporation Electro-optical device and electronic apparatus

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62280890A (ja) * 1986-05-30 1987-12-05 松下電器産業株式会社 アクテイブマトリツクスアレイ
JPH02245738A (ja) * 1989-03-20 1990-10-01 Hitachi Ltd 液晶表示装置
JPH03137622A (ja) * 1989-10-23 1991-06-12 Sharp Corp アクティブマトリクス基板

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62280890A (ja) * 1986-05-30 1987-12-05 松下電器産業株式会社 アクテイブマトリツクスアレイ
JPH02245738A (ja) * 1989-03-20 1990-10-01 Hitachi Ltd 液晶表示装置
JPH03137622A (ja) * 1989-10-23 1991-06-12 Sharp Corp アクティブマトリクス基板

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11520198B2 (en) 2020-10-27 2022-12-06 Seiko Epson Corporation Electro-optical device and electronic apparatus

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