WO1997023906A1 - Dispositif de stockage a semi-conducteurs et son procede de fabrication - Google Patents

Dispositif de stockage a semi-conducteurs et son procede de fabrication Download PDF

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Publication number
WO1997023906A1
WO1997023906A1 PCT/JP1996/003803 JP9603803W WO9723906A1 WO 1997023906 A1 WO1997023906 A1 WO 1997023906A1 JP 9603803 W JP9603803 W JP 9603803W WO 9723906 A1 WO9723906 A1 WO 9723906A1
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Prior art keywords
transistor
diffusion region
transistors
polycrystalline silicon
memory device
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PCT/JP1996/003803
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English (en)
Japanese (ja)
Inventor
Mitoshi Umeki
Nobufumi Inada
Masahiko Daimatsu
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Nkk Corporation
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Publication date
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Publication of WO1997023906A1 publication Critical patent/WO1997023906A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices

Definitions

  • the present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a semiconductor memory device including two driver transistors, two transistor transistors, and two high-resistance elements or two thin-film transistors.
  • the present invention relates to a semiconductor memory device having a basic memory cell structure as described above and used as a static random access memory (SRAM) and a method of manufacturing the same.
  • SRAM static random access memory
  • Figure 1 shows an equivalent circuit of one memory cell that constitutes a conventional high-resistance load type SRAM, which consists of four transistors Q1 to Q4 and two high-resistance elements R1 and R2. A circuit diagram of a memory cell is shown.
  • Q 1 and Q 2 are driver transistors for driving (also referred to as bull down transistors), and Q 3 and Q 4 are transistor gate transistors (or pass gate transistors). ).
  • R 1 and R 2 are high The resistance cable, WL is the lead wire, and BL and BL are the bit line.
  • S1 and S2 are nodes, Vec is a positive power supply voltage, for example, 5 volts, and Vss is a negative power supply voltage, which is grounded to zero volts.
  • the positive power supply voltage V " is set to 5 V
  • the negative power supply voltage Vss is set to 0 V
  • the transistor Q 2 is turned off. It is assumed that the transistor Q1 is in the off state.
  • the memory cell shown in Fig. 1 forms one bit in a high resistance load type flip-flop structure.
  • the drain which is the output of the transistor Q 1
  • the drain which is the output of the other transistor Q 2
  • the drain which is the output of the other transistor Q 2
  • a node S2 of a certain drain is connected to the gate of one transistor Q1, and this is called coupling.
  • the above-mentioned inverter output portion corresponds to the drain ( ⁇ ⁇ diffusion region) portion of one driver transistor, and the wiring portion corresponds to the driver transistor portion.
  • the N + diffusion region and the gate must be connected as short as possible. There is a need to.
  • FIG. 2A and 2B show an example of this method.
  • a part of the gate oxide film 3 formed on the surface of the P-type well 2 formed on the N-type silicon substrate 1 is removed, and the film is removed from the exposed surface.
  • a gate electrode 12 of one driver transistor made of polycrystalline silicon is formed on the oxide film 6.
  • the channel stop is formed under the field oxide film 6. It is.
  • a phosphorus glass film (not shown) is deposited on the formed gate electrode 12 and the gate oxide film 3, and further heat treatment is performed to diffuse the phosphorus into the P-well 2. As shown in FIG. 2B, an N ′ diffusion region 29 serving as a drain of the other drain transistor is formed.
  • the gate electrode 12 of one driver transistor Q1 shown in FIG. 1 is directly connected to the ⁇ ⁇ diffusion region 29 serving as the drain of the other driver transistor Q2. Can be installed.
  • the phosphorus is diffused into the P-well 2 by thermal diffusion.Therefore, the diffusion region 29 of the phosphorus is as large as 0.5 to 1.2, so that it cannot be applied to a submicron device. Atsuta.
  • a gate made of a first-layer polycrystalline silicon is formed.
  • the electrode 9 is formed.
  • an N + type diffusion layer 31 is formed on the surface of the P well 2 using the gate electrode 9 as a mask, and then an oxide film 32 is formed on the entire surface.
  • the oxide film 32 is selectively removed by etching to expose the upper surface of the gate electrode 9 corresponding to the polysilicon contact portion, and to remove the oxide film 32 from the bonding portion.
  • the corresponding diffusion layer 31 is exposed.
  • a second polycrystalline silicon layer is formed on the upper surface exposed portion of the gate electrode 9 and the exposed portion of the diffusion layer 31 and then patterned and bonded.
  • the wiring 33 connected to the diffusion layer 31 in the padding portion and the gate electrode 9 in the polysilicon contact portion is formed.
  • the first-layer polycrystalline silicon is connected through the second-layer polycrystalline silicon wiring 33 in order to reduce the size.
  • a method of connecting the gate electrode 9 made of GaN and the diffusion layer 31 to reduce the chip area by a vertically laminated structure is adopted.
  • a second layer of polycrystalline silicon is required to route the wiring 33, and when considering the polycrystalline silicon wiring to be configured as SRAM, a total of three layers is used. Polycrystalline silicon is required. This means an increase in the number of masking steps in the manufacturing process.
  • the cell pattern becomes asymmetric due to the miniaturization of the memory cell, resulting in an imbalance in the stray capacitance between the wirings inside the cell, and the data retention characteristics become unstable due to this. There is.
  • an object of the present invention may be achieved miniaturization of LSI and simplification of the manufacturing process at the same time, and is and provide child stable operation can be realized a semiconductor memory device and a manufacturing method thereof structure (SUMMARY OF THE INVENTION
  • the present invention relates to a first and a second transfer transistor.
  • the present invention includes a memory cell having first and second transistor transistors, first and second driver transistors, and first and second resistance cables.
  • a semiconductor memory device having a flip-flop structure formed by cross-cutting using a second transistor transistor and first and second resistance wires, and formed in the surface of the semiconductor substrate.
  • a buried diffusion region formed in the buried contact opening of the diffusion region of the first driver transistor and having the same conductivity type as the diffusion region; and a second buried diffusion region connected to a surface of the buried diffusion region via a conductor.
  • a wiring layer made of polycrystalline silicon connected to the gate of the driver transistor.
  • the present invention has first and second transistor transistors, first and second driver transistors, and first and second thin-film transistors functioning as resistance loads.
  • a wiring layer of polycrystalline silicon connected to the surface of the region and connected to the gate of the second transistor.
  • the present invention includes a pair of transistor transistors, a pair of driver transistors, and a memory cell having a pair of resistor wires, and a pair of transistor transistors. And a method of manufacturing a semiconductor memory device having a flip-up structure by cross-clamping using a pair of resistive stubs. Implanting impurity ions to form a buried diffusion region of the same conductivity type as the diffusion region; and connecting a wiring made of polycrystalline silicon to the buried diffusion region. And BRIEF DESCRIPTION OF THE FIGURES
  • FIG. 1 is an equivalent circuit diagram of a high resistance load type SRAM according to the present invention.
  • FIG. 2A is a process diagram of a conventional SRAM manufacturing method, in which a gate electrode is formed in a drain formation region on the surface of a silicon substrate. »
  • FIG. 1 A first figure.
  • FIG. 2B is an explanatory view of a step of forming a drain on the surface of the silicon substrate after the step of FIG. 2A.
  • FIG. 3A is a process diagram of a conventional method of manufacturing an SRAM having another different structure, and is an explanatory view of a process of forming a diffusion layer serving as a drain of each pull-down transistor on the surface of a silicon substrate.
  • FIG. 3B is an explanatory view of the step of exposing the surfaces of the gate and drain of the first and second pull-down transistors to be connected to each other after the step of FIG. 3A by etching.
  • FIG. 3C is an explanatory view from the step of FIG. 3B to the formation of a second-layer polysilicon and connection of the gate and drain of the first and second pull-down transistors.
  • FIG. 4A is a process drawing of a method for manufacturing an SRAM memory cell according to one embodiment of the present invention, and is an explanatory view up to ion implantation of boron into the surface of a silicon substrate.
  • FIG. 4B is a process drawing following FIG. 4A, and is an explanatory view up to forming a field oxide film on the surface of the silicon substrate.
  • FIG. 4C is a process drawing following FIG. 4B and is an explanatory view up to formation of a gate oxide film in the active region of the silicon substrate.
  • FIG. 4D is a process drawing following FIG. 4C, and is an explanatory view up to forming an N-type buried diffusion layer in a part of the active region of the silicon substrate.
  • FIG. 4E is a process drawing following FIG. 4D and is an explanatory view up to formation of a polycrystalline silicon layer to be a polysilicon wiring.
  • FIG. 4F is a process drawing following FIG. 4E, and is an explanatory diagram up to formation of a source / drain region having an LDD structure.
  • FIG. 4G is a process drawing following FIG. 4F, and is an explanatory diagram up to the time of removing the resist pattern.
  • FIG. 4H is a process drawing following FIG. 4G and is an explanatory view up to formation of a second-layer polysilicon layer.
  • FIG. 4I is a cross-sectional view of the final step of the method for manufacturing an SRAM according to the embodiment.
  • Fig. 5 is a diagram showing the diffusion profile of impurity ions along the line VV in Fig. 4F.
  • FIG. 6 is a plan view of the intermediate product in the step of FIG. 4E.
  • FIG. 7 is a plan view of the intermediate product in the step of FIG. 4H.
  • Fig. 8 is a plan view of the product in the final step of Fig. 4I.
  • FIG. 9 shows an S R according to another embodiment of the present invention corresponding to FIG. 4E.
  • FIG. 4 is a process chart of an AM manufacturing method, illustrating a process up to the formation of an oxide film on the surface of a polycrystalline silicon layer to be a polysilicon wiring.
  • FIG. 10 is a process drawing following FIG. 9 and is an explanatory view up to formation of a source / drain region having an LDD structure.
  • FIG. 11 is a process drawing following FIG. 10 and is an explanatory view up to selective etching of the oxide film on the surface of the polycrystalline silicon layer.
  • FIG. 12 is a process drawing following FIG. 11 and is an explanatory view up to forming a titanium silicide layer on the entire surface.
  • FIG. 13 is a process drawing following FIG.
  • FIG. 6 is a sectional view of the final step in the method for manufacturing RAM.
  • FIG. 14 is a plan view of the intermediate product in the step of FIG.
  • FIG. 15 is a process diagram of the manufacturing method according to this embodiment, in which BF 2 ⁇ is ion-implanted into a power supply line forming portion to form a power supply line.
  • FIG. 16 is a plan view of the product in the final step of FIG.
  • FIG. 17 is an equivalent circuit diagram of a TFT type SRAM using the thin film transistor according to the present invention as a high resistance load.
  • FIG. 18 is an explanatory view up to the formation of an oxide film on the surface of a polycrystalline silicon layer serving as a polysilicon wiring corresponding to the manufacturing process of the embodiment shown in FIG.
  • Fig. 19 is an explanatory view of the steps following Fig. 18 up to the formation of the source and drain regions of the LDD structure.
  • FIG. 20 is a process drawing following FIG. 19, and is an explanatory diagram showing a state before the resist pattern is removed.
  • FIG. 21 is a process drawing following FIG. 20, and is an explanatory diagram up to formation of a second-layer polysilicon layer.
  • FIG. 22 is a sectional view of the final step of the method for manufacturing an SRAM according to the embodiment.
  • FIG. 23 is a plan view of the intermediate product in the step of FIG.
  • FIG. 24 is a plan view of the intermediate product in the step of FIG. 21.
  • FIG. 25 is a plan view of the product in the final step of FIG. 22.
  • a P-type resistor 52 is formed on the surface of an N-type silicon substrate 51, a silicon oxide film 53 is formed, and then a resist 54 is used. As oxidation resistant film A pattern 55 of a silicon film (Si 3 N 4 ) is formed.
  • a field oxide film 56 having a thickness of 600 nm is formed on the surface of the P-well 52 by a selective thermal oxide film formation method (LOCOS method) using the resist 54 as a mask.
  • LOC method selective thermal oxide film formation method
  • reference numeral 57 in the figure is a channel stopper layer of P +.
  • the surface of the P-well layer 52 exposed by the thermal oxidation method has a thickness of 18 nm.
  • a gate oxide film 58 is formed.
  • a resist pattern 59 is formed on the entire surface of the substrate 1 except for a portion where the active region is to be exposed. Thereafter, using the resist pattern 59 as a mask, the gate oxide film 58 is selectively removed by wet etching with a hydrofluoric acid solution to form a buried contact hole 60.
  • As (arsenic) is ion-implanted as an N-type impurity under the conditions of an acceleration voltage of 100 KeV and a dose of 4 ⁇ 10 15 cm 2 , and an N-type with a depth of about 0.2 m.
  • FIG. 6 shows a plan view of FIG. 4E
  • FIG. 4E is a cross-sectional view taken along line 4E-4E of FIG. 6 and viewed in the direction of the arrow.
  • the N + region 65 is formed relatively deep, and the source region and the drain region having the LDD structure are formed.
  • the buried diffusion region 61 into which As (arsenic) is implanted is electrically connected to the source and drain regions.
  • the line 64 is connected to the buried diffusion region 61.
  • an example of the profile of the diffused ions inside the substrate along the line 5-5 in Fig. 4F is a graph as shown in Fig. 5.
  • the vertical axis in Fig. 5 indicates the ion concentration of each impurity. shows, shows a value of 1 0 14 to 1 0 2 (1. the vertical axis shows the diffusion depth from the surface of the sheet re co down substrate 1, shows a value ranging from 0 to 1. 2 m.
  • Figure 4 is a diffusion by F of the buried diffusion region 6 1 Wahisaku (A s), 0 ⁇ 0. 1 of very high concentration to a depth of about 2 m 0 18 ⁇ becomes 1 0 20 ions / cm 3 I have.
  • N 'region 6 5 is formed relatively deep, 0.2 to 0 4 as the value range on the concentration of the m 1 0 15 ⁇ :.
  • the ions forming the P-well 52 are diffused at a substantially constant concentration in the range of 0.6 to 1.2 m at a deeper position.
  • a first polycrystalline silicon film (not shown) having a thickness of 300 nm (not shown) is formed by applying a CVD method.
  • a P 0 C 13 gas phase diffusion method phosphorus is introduced to form an N + concentration region, thereby lowering the resistance of the first polycrystalline silicon film.
  • a gate electrode 64 is formed.
  • the gate electrode 64 is connected to a transistor transistor and a drive transistor. It corresponds to the gate electrode of the electrode.
  • an insulating oxide film 65 having a thickness of 100 nm is formed on the entire surface of the silicon substrate 1 by applying the CVD method, as shown in FIG. 4H.
  • the resist patterning in the photolithography technique and the reactive ion etching method of a CHF and ZHe gas system are applied to form a polyisohole 70.
  • a second polycrystalline silicon layer 66 having a thickness of 10 nm is applied by applying the CVD method. Subsequently, by a registry patterning and (] C 1 4/0 2 apply child reactive ion etching of the gas system in the off O Application Benefits lithography technology, patterning of the second polycrystalline Shi Li co down layer 66 I do.
  • a 140-nm-thick insulating oxide film (not shown) and a 700-nm-thick insulating film 67 of boron-lined glass are formed on the entire surface as shown in Fig. 4I by applying the CVD method. I do. Subsequently, a heat treatment for reflowing and flattening the insulating film 67 is performed.
  • contact holes are formed in the insulating film 67 and the insulating oxide film by applying resist polishing in a photolithography technique and a reactive ion etching method using a CH 3 / He gas system. Furthermore, after a 400 nm thick aluminum film was formed by applying the sputtering method, this was applied to the resist patterning in the usual photolithography technology, as shown in FIG.
  • the bit line 69 is formed as described above.
  • the SRAM formed as described above is provided with a diffusion layer 61 by ion implantation in a contact region on the surface of the semiconductor substrate 51, and the diffusion layer 61
  • the diffusion layer 61 By connecting the wiring 64 of the first layer silicon of the driver transistor on the side opposite the flip-flop with the flip-flop directly to the diffusion layer 61, the input / output coupling of the flip-flop configuration is realized. Is performed. Therefore, unlike the case of the conventional direct contact, the impurity diffusion region does not become unnecessarily large, and the pattern can be miniaturized.
  • the contact can be performed without using the second polycrystalline silicon, the process is simplified, and the size of the contact portion is reduced. Can also be reduced.
  • the semiconductor memory device is described as an example of SRAM coupling.
  • the present invention is not limited to this, and any device that can forcely couple a diffusion region of a semiconductor substrate and a conductive wiring can be used. It is possible.
  • polycrystalline silicon is used as the material of the conductive wiring, the present invention is not limited to this, and other materials such as silicide and amorphous silicon may be used.
  • FIGS. 9 to 16 show the SRAM of another embodiment of the present invention. The structure is shown together with its manufacturing method.
  • the step of FIG. 9 corresponds to the step of FIG. 4E of the above embodiment, and the preceding step is the same as that of FIGS. 4A to 4D, so that the detailed description is omitted, and the reference numerals correspond. The parts are the same.
  • the first polycrystalline silicon layer 62 nm having a thickness of 300 nm is entirely formed by a chemical vapor deposition (CVD) method.
  • CVD chemical vapor deposition
  • a phosphorus glass layer (not shown) is formed on the polycrystalline silicon layer 62 to diffuse phosphorus into the polycrystalline silicon layer 62, and then the phosphorus glass layer is removed.
  • the polycrystalline silicon The oxide layer 63 is grown on the surface of the polycrystalline silicon layer 62 as shown in FIG.
  • FIG. 14 shows a plan view of the apparatus of FIG. 9, and a section taken along line 9-9 in FIG. 14 results in a cross section of FIG.
  • Reference numeral 81 in FIG. 14 denotes the Vss supply line in FIG. 1, and reference numeral 82 denotes the word line WL.
  • the N_ layer (not shown) forming a part of the LDD structure region is made shallow by doping the portion where the wiring 65 is not formed with low-concentration phosphorus as an N-type impurity. Form.
  • the phosphorus was applied to the substrate 51 under the conditions of an acceleration voltage of 80 KeV and a dose amount of S xlo Z cm 2. Implant ions.
  • the N ′ region 66 is formed relatively deep, and the source region and the drain region having the LDD structure are formed.
  • the polysilicon wiring 65 is connected to the buried diffusion region 60. That is what we do.
  • the resist pattern 64 the resist pattern 64
  • a new resist pattern 67 having an opening 67 ′ in a portion corresponding to the N + region 66 and a part of the oxide film 63 was formed by photolithography.
  • the oxide film 58 was selectively etched away.
  • the polycrystalline silicon layer is patterned to perform back contact.
  • a conductive wiring 69 made of polycrystalline silicon connected to the N-type buried diffusion layer 60 via the titanium silicide layer 68 is formed.
  • BF 2 + is deposited on the second polycrystalline silicon layer 84 to be a V cc power source line by resist turning and ion implantation by photolithography. Ion is implanted under the conditions of an acceleration voltage of 30 to 50 KeV and a dose of 1 ⁇ 10 15 cm 2 to form a Vcc line 83.
  • the width W of the Vcc line 83 may be larger than or equal to the width W0 of the second polycrystalline silicon layer 84, but is not limited to the SRAM cell.
  • the width cannot be made large enough to reduce the resistance value of the high-resistance polysilicon layer as the high-resistance element used.
  • an oxide film (NSG film) 70 having a thickness of about 140 nm is deposited by the CVD method, and then a boron-lin glass film 71 of about 70 nm is deposited.
  • planarization is performed by reflowing at about 850 to 875 ° C.
  • an aluminum film of about 4 O Onm is deposited by a sputtering method, and a bit line 72 is formed by the same photolithographic Z etching method.
  • an ion implantation (A s) is implanted into the P-module 52 under predetermined conditions. Then, an N-type buried diffusion layer 60 is formed, and as shown in FIG. 10, a poly-silicon interconnection 62 made of the first layer of polycrystalline silicon is formed, as shown in FIG. A titanium silicide layer 68 is formed on the entire surface, and a conductive wiring 69 made of a second layer of polycrystalline silicon is arbitrarily patterned through the titanium silicide layer 68 to form a diffusion layer 60 on the surface of the P-cell 52. Manufactured by connecting.
  • the impurity diffusion region does not become unnecessarily large, and thus it is possible to follow a fine pattern. Further, the diffusion layer 60 on the surface of the P-module 52 and the conductive wiring 69 can be cut without complicating the process. Furthermore, the size of the contact part is also reduced.
  • the patterns shown in FIGS. 14 to 16 are also point-symmetric as in the first embodiment, and have excellent data retention characteristics because of the regularity of the patterns.
  • node S! Tiger Njisuta Q j is O off state and the resistance value of the tiger Njisuta is sufficiently large when the potential 5 V compared to the resistance of the on state of the Q 5 tiger Njisuta held in.
  • nodes S 2 is tiger Njisuta Q 2 Gao down state and the resistance value when there is sufficiently low potential 0 V compared to the resistance value of the off state of the tiger Njisuta Q 6 is maintained.
  • the first polycrystalline silicon layer having a thickness of 300 nm is entirely formed by a chemical vapor deposition (CVD) method. 6 2, followed by a glass layer on top of this polycrystalline silicon layer 6 2
  • FIG. 23 is a plan view of FIG. 18, and a cross-sectional structure as shown in FIG. 18 is obtained by cutting along the line 18—18 in FIG.
  • reference numeral 81 indicates a Vss supply line
  • reference numeral 82 indicates a lead line
  • reference numeral 83 indicates a gate of a TFT transistor.
  • a CC 1 A / 2 gas-based reactive ion etching method is applied.
  • the polycrystalline silicon layer 62 is patterned to form a polysilicon line 65 made of polycrystalline silicon.
  • the N-type impurity is applied to the part where the wiring 65 is not formed.
  • the N_ layer (not shown), which forms part of the LDD structure region, is formed shallow by lightly doping the phosphorus as a material.
  • the silicon substrate 5 was accelerated under the conditions of an acceleration voltage of 80 KeV and a dose of 3 ⁇ 10 15 Z cm 2.
  • the Re c this ion implantation to 1 N + region 66 is relatively deeply formed, a source region of the L DD structure, drain region is formed. Since the buried diffusion region 61 into which arsenic (A s) is implanted is electrically connected to the source and drain regions, the polysilicon wiring 65 is connected to the buried diffusion region 61. Is connected.
  • the first polycrystalline silicon layer having a thickness of 200 nm is formed by applying a chemical vapor deposition (CVD) method.
  • CVD chemical vapor deposition
  • the POC 1 3 vapor phase diffusion method By adapting the POC 1 3 vapor phase diffusion method, the N + doped region forming the introduction of the re-emission Te row summer, to reduce the resistance of the first polycrystalline silicon layer.
  • This gate electrode corresponds to the gate electrodes of the transistor and the drive transistor.
  • arsenic (A s) is ion-implanted into the substrate 51 under the conditions of an acceleration voltage of 40 KeV and a dose of 3 ⁇ 10 15 cm 2 , and the N + type source region S ⁇ , A drain region Dn is formed.
  • the CVD method by applying the CVD method, the thickness shown in Fig. 21 is obtained.
  • An insulating oxide film 67 having a thickness of 100 nm is formed.
  • polyisohols 68 are formed by applying resist patterning in the photolithography technique and reactive ion etching of a CHF 3 / He gas system.
  • a second polycrystalline silicon layer 69 having a thickness of 200 nm is formed by applying the CVD method.
  • Ri by the applying registry patterning and CC 1 4/0 2 gas based reactive ion etching method in the off O Application Benefits lithography technique, patterning the second polycrystalline silicon layer 69.
  • resist etching and ion implantation in photolithography boron fluoride (BF) was accelerated under the conditions of an acceleration voltage of 30 KeV and a dose of lxl 0 16 Z cm 2 . Inject it into the supply line 84 of the power supply voltage V shown in Fig. 24 and the portion to be the source side of the TFT transistor.
  • BF boron fluoride
  • FIG. 24 shows a plan view of FIG.
  • an insulating oxide film (not shown) having a thickness of 14 ° nm and an insulating film ⁇ 0 made of boron-lin glass having a thickness of 700 nm are formed on the entire surface shown in FIG. .
  • a heat treatment is performed to flatten the insulating film 70 by reflex opening. This was followed by the registration of photolithography technology.
  • Contact holes are formed in the insulating film 70 and the insulating oxide film by applying a reactive ion etching method of a CHF 3 / He gas system to the insulating film.
  • FIG. 25 shows a plan view of FIG.
  • the TFT type SRAM according to the above-described embodiment is provided with a diffusion layer 62 by ion implantation in a contact region on the surface of the semiconductor substrate 51, and the diffusion layer 61 and the diffusion layer 61 are formed.
  • the impurity diffusion region is not unnecessarily widened, so that the mask process at the time of manufacturing is reduced, the cell size is not increased, and the easiness of manufacturing and the manufacturing are improved. The yield can be improved.
  • the pattern is point-symmetric, and the improvement of the symmetry has the effect of improving the data retention characteristics. Further, since the polyiso and the buried contact are provided at one location, a margin for mask alignment can be created.
  • the coupling of the SRAM has been described as an example of the semiconductor memory device.
  • the present invention is not limited to this. It can be applied as long as it can force-couple the diffusion region and the conductive wiring.
  • polycrystalline silicon was used as the material of the conductive wiring, the present invention is not limited to this, and other materials such as silicon and amorphous silicon may be used.
  • a diffusion layer formed by ion implantation is provided in a contact region on the surface of a semiconductor substrate, and the first layer of the pull-down transistor on the side to be compared with this diffusion layer by a flip-flop is provided.
  • the process of conducting the input / output coupling of the flip-flop configuration is not complicated, and the diffusion region of the semiconductor substrate can be connected to the conductive layer. It is possible to provide a TFT-type semiconductor memory device that can apply flexible wiring and is excellent in the mask process, manufacturing yield, data retention characteristics, and miniaturization during manufacturing.
  • a buried diffusion region of the same conductivity type as the diffusion region formed by implanting ion species through the buried contact opening of the diffusion region in the surface of the semiconductor substrate By providing a wiring made of polycrystalline silicon connected to the buried diffusion region, the impurity diffusion region does not become unnecessarily wide unlike the case of the conventional direct con- It is possible to provide a semiconductor memory device capable of power-supplying a diffusion region and a conductive wiring of a semiconductor substrate without causing complication.

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Abstract

L'invention porte sur un dispositif de stockage à semi-conducteurs fait d'une cellule mémoire comportant des transistors à porte de transfert, une paire de transistors de commande, une paire d'éléments résistants ou de transistors à couche mince, et une structure bistable interconnectée utilisant une charge de la paire de transistors à porte de transfert et la paire d'éléments résistants ou les transistors à couche mince. Une couche de diffusion (61) est prévue dans une zone de contact de la surface du substrat de semi-conducteur (51), tandis que le câblage (65) de polysilicium de la première couche du transistor de commande faisant face à la couche de diffusion (61) dans la structure bistable est directement relié à la couche de diffusion (61).
PCT/JP1996/003803 1995-12-26 1996-12-26 Dispositif de stockage a semi-conducteurs et son procede de fabrication WO1997023906A1 (fr)

Applications Claiming Priority (6)

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JP33874895 1995-12-26
JP7/338748 1995-12-26
JP8/20059 1996-02-06
JP8/20058 1996-02-06
JP2005896 1996-02-06
JP2005996 1996-02-06

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH043465A (ja) * 1990-04-20 1992-01-08 Toshiba Corp 半導体スタティックメモリ装置の製造方法
JPH05251665A (ja) * 1992-03-04 1993-09-28 Nec Corp 半導体装置の製造方法
JPH05291535A (ja) * 1992-04-15 1993-11-05 Nec Corp 半導体記憶装置
JPH07176633A (ja) * 1993-12-20 1995-07-14 Nec Corp Ｃｍｏｓ型スタティックメモリ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH043465A (ja) * 1990-04-20 1992-01-08 Toshiba Corp 半導体スタティックメモリ装置の製造方法
JPH05251665A (ja) * 1992-03-04 1993-09-28 Nec Corp 半導体装置の製造方法
JPH05291535A (ja) * 1992-04-15 1993-11-05 Nec Corp 半導体記憶装置
JPH07176633A (ja) * 1993-12-20 1995-07-14 Nec Corp Ｃｍｏｓ型スタティックメモリ

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