Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
  • H03F3/602—Combinations of several amplifiers
  • H03F3/604—Combinations of several amplifiers using FET's
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
  • H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
  • H03F1/3223—Modifications of amplifiers to reduce non-linear distortion using feed-forward
  • H03F1/3229—Modifications of amplifiers to reduce non-linear distortion using feed-forward using a loop for error extraction and another loop for error subtraction

Definitions

• the present invention relates generally to amplifier circuits, and more particularly to Doherty type amplifier circuits.
• the present invention provides an improved amplifier circuit and a method of tuning a Doherty type amplifier circuit.
• the amplifier circuit comprises a first amplifier having a carrier amplifier and a peak amplifier configured in a Doherty arrangement, a second amplifier having a carrier amplifier and a peak amplifier configured in a Doherty arrangement, and a combination circuit responsive to the first and second amplifier
• the first amplifier produces a substantially linear first output signal over a first frequency bandwidth.
• the second amplifier produces a substantially linear second output signal over a second bandwidth.
• the combination circuit is responsive to the first and second output signal and produces a third output signal that is substantially linear over a third frequency bandwidth. The third frequency bandwidth is greater then either the first or second frequency bandwidths.
• the amplifier circuit comprises a carrier amplifier producing a carrier amplifier output signal, a peaking amplifier coupled to the carrier amplifier in a Doherty configuration, and a combination circuit responsive to the carrier amplifier and the peaking amplifier.
• the peaking amplifier is voltage biased to produce an adjusted intermodulation product signal
• the combination circuit combines the adjusted modulation product signal with the carrier amplifier output signal to produce a substantially linearized amplifier circuit output signal.
• the method of tuning a Doherty type amplifier circuit includes the steps of providing a Doherty type amplifier, measuring intermodulation performance of the Doherty type amplifier as a function of peaking amplifier bias voltage, and selecting a peaking amplifier bias voltage based on the measured intermodulation performance.
• FIG. 1 is a circuit schematic of a Doherty type amplifier circuit.
• FIG 2 is a graph of intermodulation products for the Doherty type amplifier of FIG. 1.
• FIG. 3 is a circuit diagram of a feedforward amplifier using the
• FIG. 4 is a block diagram illustrating a parallel Doherty type amplifier arrangement.
• FIG. 5 is a flow chart of a method of tuning a Doherty tpe amplifier.
• FIG. 6 is a particular embodiment of a matching circuit. Detailed Description
• an amplifier circuit 20 including a carrier amplifier 24 and a peaking amplifier 26 configured in a Doherty arrangement is illustrated.
• the amplifiers 24 and 26 each receive a bias voltage.
• the amplifier circuit 20 has an input 22 and an output 38
• the amplifier circuit includes a delay line 28, preferably providing a 90 degree delay, and a transformer line 30.
• the carrier amplifier 24 produces an output signal that is transmitted over a phasing line 32 and over the transformer line 30.
• the peaking amplifier 26 provides an output signal that is transmitted over a second phasing line 34.
• the output signals from the carrier and peaking amplifiers 24 and 26 are joined in a combination circuit 35 such as a common node, transmitted over a transformer line 36, and finally outputted at the amplifier circuit output 38.
• the carrier amplifier 24 preferably a metal oxide semiconductor field effect transistor (MOSFET) type amplifier, such as a MRF183 Series amplifier available from Motorola operating in a class AB mode.
• the peaking amplifier 26 is preferably a MOSFET type amplifier such as a MRF183 Series amplifier available from Motorola operating in a class C mode
• the MRF 183 Series amplifiers are available from Motorola at 5008 E. McDowell Road, Phoneix, Arizona, 85008
• the delay line 28 is preferably implemented with microst ⁇ p or st ⁇ pline technology in a manner known to those of ordinary skill.
• the transformer line 30 has an impedance of about fifty ohms and is a quarter wavelength.
• the transformer line 36 is also quarter wavelength and has an impedance of about thirty five ohms.
• the peaking amplifier 26 is responsive to the delay line 28 and is coupled to the phasing line 34.
• the transformer line 30 is responsive to the carrier amplifier 24 and interconnects the outputs from the carrier and peaking amplifiers 24 and 26 During operation, the carrier amplifier 24 is voltage biased for linear operation while the peaking amplifier 26 is voltage biased for nonlinear operation Over a predetermined frequency range, the peaking amplifier 26 produces intermodulation products such as third order intermodulation products, that destructively combine with intermodulation products from the carrier amplifier 24 such that the entire amplifier circuit 20 operates substantially linearly. However, due to fluctuations in individual amplifiers, the amplifier circuit 20 should be tuned to improve linearity of performance over the desired frequency range.
• a preferred method of tuning the amplifier circuit 20 to be substantially linear over a certain frequency range will now be described.
• the amplifier circuit 150 includes first 154, a second 156, and a third 158 Doherty type amplifiers that are preferably in a parallel arrangement.
• Each of the amplifiers 154, 156, and 158 is responsive to a driver amplifier 152 that receives an input signal 164 and produces a driver signal 160.
• the driver signal 160 is fed into the input of each of the amplifiers 154, 156, and 158.
• Each of the amplifiers 154, 156, and 158 produces an amplified output that is joined at a common node 162 and sent to an output 166 of the amplifier circuit 150.
• Each of the Doherty type amplifiers 154, 156, and 158 is preferably substantially similar in construction to the amplifier 20 illustrated in FIG. 1 and tuned to operate substantially linearly as described by the preferred tuning method set forth above.
• each of the amplifiers 154, 156, and 158 are designed to operate in a substantially linear mode over a different frequency band.
• the first amplifier 154 may be designed to operate substantially linearly between about 865 MHz and about 875 MHz
• the second amplifier 156 may be designed to operate substantially linearly between about 875 and about 885 MHz
• the third amplifier 158 may be designed to operate substantially linearly from about 885 MHz to about 895 MHz.
• the first amplifier 154 has a center frequency of about 870 MHz
• the second amplifier 156 has a center frequency of about 880 MHz
• the third amplifier 158 has a center frequency of about 890 MHz.
• a Doherty type amplifier may be tuned to operate substantially linearly over a narrow frequency range.
• the specific frequency bandwidth of linear operation may be determined by adjusting a matching circuit within the Doherty amplifier, by adjusting the lengths of phasing lines, such as phasing lines 32 and 34 in amplifier 20, or by adjusting bias voltages of the carrier or peaking amplifiers 24 and 26.
• each of the amplifiers 154, 156, and 158 may be operating at a different transition voltage leading to varying frequency bands of linearity.
• the Doherty amplifier architecture has an intrinsic bandwidth limitation.
• the limitation is due to circuit loading of the carrier amplifier by the peaking amplifier.
• the degree of circuit loading is determined by the peaking amplifier output matching circuit reactance, as well as the intrinsic reactance of the device, and the associated parasitic reactance of the device package.
• Feedforward amplifiers generally require broadband main amplifiers to minimize time delays through active devices and to facilitate broadband carrier cancellation.
• the intrinsic bandwidth limitation can be overcome by using a tuning methodology which extends Doherty amplifier bandwidth and substantially maintains intermodulation performance, gain flatness, and high efficiency.
• the tuning methodology to achieve a total system bandwidth of X MHz consists of several parts.
• Each carrier amplifier and peaking amplifier stage (for N total Doherty stages in parallel) are matched for a desired intermodulation, efficiency, and gam flatness over a bandwidth of X/N MHz.
• Matching circuits are composed of conventional discrete reactive elements such as capacitors, inductors and/or distributed transmission lines, in both series and parallel configurations for RF circuits.
• An example of a tuned matching circuit is shown in FIG. 6.
• Each carrier amplifier and peaking amplifier in a Doherty circuit is preferably coupled to provide proper power combining between the amplifiers. This coupling is often achieved using a transmission line of approximately ⁇ /4 wavelengths. Since the transmission line (or phasing line) is frequency sensitive, desirable coupling of the carrier and peaking amplifier for maximum power combining occurs at a single frequency. Therefore, Doherty efficiency (dependent on peaking amplifier circuit loading) and intermodulation performance (dependent on carrier amplifier output loading) are enhanced when phasing line optimization is performed over a X/N MHz bandwidth, rather than the entire X MHz bandwidth.
• the tuning methodology thus provides that the phasing line length of each N Doherty amplifier uses a phasing line matched for a different X/N MHz fractional bandwidth.
• three different phasing line lengths would be used.
• the 840-850 MHz Doherty stage would have ⁇ /4 phasing line length of ⁇ 845 MHz'' 4 .
• the 850-860 MHz Doherty stage would have a ⁇ JA phasing line length of ⁇ 855 MHz- 74 .
• the 860-870 MHz Doherty stage would have a ⁇ /4 phasing line length of ⁇ 865 MHz/ 4 .
• each Doherty amplifier achieves improved gain flatness and intermodulation performance with an adjustment to the peaking amplifier bias. Therefore, each Doherty amplifier of bandwidth X/N MHz has its bias set for a desired gain flatness and intermodulation performance. However, some parasitic loading effects due to module paralleling may occur, perturbing the parallel configuration intermodulation and/or gain flatness
• the preferred embodiment for the paralleled Doherty configuration includes a final adjustment of each Doherty amplifier's peaking amplifier bias voltage to simultaneously adjust the Doherty main amplifier intermodulation performance, efficiency, and gain flatness. Since the bias adjustment involves the simultaneous optimization of three parameters (gain, flatness, IM, efficiency), a bias adjustment algorithm is typically used. The bias adjustment algorithm is best described in terms of a flow chart.
• Doherty amplifier performance is realized when IM performance, bandwidth, gain, efficiency, and group delay targets are all met substantially simultaneously.
• the amphfier circuit 150 may operate substantially linearly over a greater frequency band then any of the individual Doherty amplifiers.
• the amplifier circuit 150 operates substantially linearly over the frequency band of about 865 MHz to about 895 MHz. Accordingly, the amplifier circuit 150 has the benefit of operating efficiently by using Doherty type amplifiers and advantageously operates substantially linearly over a relatively wide bandwidth.
• the group delay through a Doherty amplifier will be higher than in a conventional amplifier due to the inherent bandlimited nature of the Doherty circuit
• the preferred embodiment reduces the group delay through the Doherty amplifier.
• a phase offset (randomization) is introduced between intermodulation products generated in each of the parallel Doherty stages. The phase offset occurs because each Doherty stage has a unique matching structure, a unique phasing line length, and a unique peaking amplifier bias set point.
• the multicarner intermodulation products add vectonally to a peak value less often than in a conventional parallel amplifier design, producing a lower average intermodulation level.
• the preferred X/N MHz design method increases the bandwidth of an inherently bandlimited Doherty amplifier, which substantially reduced impact on gam, efficiency and intermodulation performance
• FIG 4 illustrates a preferred embodiment of a feedforward amplifier circuit 100.
• the amplifier circuit 100 includes a main amplifier 106 and an error amplifier 1 14
• the amplifier circuit 100 includes an input 102, a first coupler 104, a second coupler 108, a third coupler 1 12, and a fourth coupler 1 16
• the amplifier circuit 100 further includes a first delay line 1 10 and a second delay line 116.
• the first coupler 104 samples an RF input signal received at the input 102 and produces a clean signal that is delayed by delay line 1 10.
• the second coupler 108 samples the output 120 of the main amplifier 106.
• the third coupler 1 12 receives the sampled output signal from coupler 108 and combines the output signal from the output 120 of mam amplifier 106 with the delayed version of the input signal sampled by the first coupler 104.
• the output of the third coupler is preferably an error signal that is amplified by error amplifier 1 14 to produce an amplified error signal 118.
• the amplified error signal 118 is combined by the fourth coupler 1 16 with a delayed output signal 122 that is produced by the second delay line 1 16. By combining the delayed output signal 122 with the amplified error signal 1 16, the resulting output 1 18 has a reduced level of error relative to the output signal 120.
• the mam amplifier 106 is a Doherty type amplifier, such as the amplifier circuit 20 illustrated in FIG. 1 , that has been tuned according to the above-described tuning method.
• the Doherty configured main amplifier 106 provides a significant increase in direct current (DC) to RF conversion efficiency in the feedforward amplifier circuit 100.
• the efficiency improvement over conventional feed forward amplifier circuits may be about 40%, far exceeding other conventional efficiency enhancement techniques such as harmonic termination.
• the Doherty configured main amplifier 106 may also improve intermodulation performance.
• Doherty configured mam amplifiers may be employed with large fractional bandwidths.

Landscapes

• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Nonlinear Science (AREA)
• Amplifiers (AREA)
• Microwave Amplifiers (AREA)

Priority Applications (6)

Applications Claiming Priority (2)

Publications (1)

Family

ID=24256136

Family Applications (1)

Country Status (10)

Cited By (19)

Families Citing this family (7)

Citations (3)

Family Cites Families (1)

• 1996
  • 1996-09-04 CA CA002204409A patent/CA2204409A1/en not_active Abandoned
  • 1996-09-04 DE DE19681072T patent/DE19681072T1/de not_active Withdrawn
  • 1996-09-04 AU AU71546/96A patent/AU7154696A/en not_active Abandoned
  • 1996-09-04 FI FI972345A patent/FI972345A0/fi not_active Application Discontinuation
  • 1996-09-04 WO PCT/US1996/014269 patent/WO1997020385A1/en not_active Application Discontinuation
  • 1996-09-04 JP JP9520453A patent/JPH10513631A/ja active Pending
  • 1996-09-04 KR KR1019970705201A patent/KR19980701804A/ko not_active Ceased
  • 1996-09-04 GB GB9713888A patent/GB2313009A/en not_active Withdrawn
  • 1996-09-12 TW TW085111159A patent/TW322657B/zh active
• 1997
  • 1997-04-24 SE SE9701538A patent/SE9701538L/ not_active Application Discontinuation

Patent Citations (3)

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events