WO1996030944A2 - Trägermodul - Google Patents

Trägermodul Download PDF

Info

Publication number
WO1996030944A2
WO1996030944A2 PCT/DE1996/000549 DE9600549W WO9630944A2 WO 1996030944 A2 WO1996030944 A2 WO 1996030944A2 DE 9600549 W DE9600549 W DE 9600549W WO 9630944 A2 WO9630944 A2 WO 9630944A2
Authority
WO
WIPO (PCT)
Prior art keywords
carrier module
module according
semiconductor chips
carrier
semiconductor chip
Prior art date
Application number
PCT/DE1996/000549
Other languages
English (en)
French (fr)
Other versions
WO1996030944A3 (de
Inventor
Martin Gruber
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Priority to JP8528785A priority Critical patent/JPH10505959A/ja
Priority to EP96907301A priority patent/EP0818023A2/de
Publication of WO1996030944A2 publication Critical patent/WO1996030944A2/de
Publication of WO1996030944A3 publication Critical patent/WO1996030944A3/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/10—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means together with a coded signal, e.g. in the form of personal identification information, like personal identification number [PIN] or biometric data
    • G07F7/1008—Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/072—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising a plurality of integrated circuit chips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07372—Means for preventing undesired reading or writing from or onto record carriers by detecting tampering with the circuit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/34—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
    • G06Q20/341—Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/0806—Details of the card
    • G07F7/0813—Specific details related to card security
    • G07F7/082—Features insuring the integrity of the data on or in the card
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the invention relates to a carrier module, in particular for installation in a card-shaped data carrier, with a carrier element having contact elements and with at least two semiconductor chips which are arranged on the carrier element and can be electrically connected to the contact elements.
  • a carrier module is known for example from EP 0 193 856 B1.
  • a number of contact elements are arranged on a substrate, which are electrically connected via a line network to semiconductor chips arranged in recesses in the substrate.
  • the semiconductor chips are also electrically connected to one another by this line network.
  • Non-volatile memories such as EEPROMs and a logic circuit controlling them or processing the data read from the memory
  • EEPROMs electrically erasable programmable read-only memory
  • a usage correction check is usually carried out using a secret code.
  • the circuits required for the test can have a structure to be kept secret. For this reason, the semiconductor chips must be protected from being examined.
  • the data stored in the non-volatile memory areas can be protected against direct detection of the stored charge states by technological measures, but it is still possible to use the charge states to access the lines connecting the memory to the logic circuit when accessing the memory content to infer the data stored there. To do this, however, the logic circuit must be functional.
  • the object of the invention is therefore to provide a carrier module in which an examination of secret components is prevented.
  • the object is achieved in that at least one semiconductor chip is arranged on another semiconductor chip and is electrically connected to the latter in such a way that a proper function of the circuit (s) implemented on the semiconductor chip is only given when this connection is present.
  • circuit components to be kept secret such as the memories or only the memory areas in which, for example, secret codes are located and logic parts to be kept secret, such as pseudo random generators for encrypting data, are implemented in the lower semiconductor chip, these cannot be recognized, since the upper one Chip covered them. If, however, the upper chip is removed, the connection between the chips is interrupted, so that the lower chip is no longer functional and therefore no charge patterns to be examined can arise on its lines.
  • the upper chip with the surface on which the circuit is implemented is arranged on the corresponding surface of the lower chip which has the circuit and is arranged on the latter. In this way, even the upper chip cannot be examined optically without separating the two chips from one another and thus interrupting their functionality.
  • the two chips in an oriented manner in the same direction and to create an electrical connection via bond wires. But these should then be so short, or be attached in such a way, for example point to at least two sides of the upper chip that they tear off when the upper chip is removed.
  • the carrier element can either be a metal-laminated plastic film or a lead frame.
  • a lead frame is to be understood here to mean that contact elements are connected in a conventional manner to a lead frame and project from the latter in the middle thereof. After fixing the first free ends of the contact elements by means of a housing, the contact elements are punched out of the lead frame or separated from it in some other way.
  • FIG. 1 shows a first variant of the carrier module according to the invention and FIG. 2 shows a second variant of the carrier module according to the invention.
  • a plastic film 1 is laminated on one side with a metal film, for example a copper film. Slots 8 are etched into the copper foil 2, so that contact elements which are electrically insulated from one another are produced.
  • the plastic film 1 has recesses, in the middle of which a first semiconductor chip 3 is arranged, for example glued. Bond wires 6 are connected both to this first semiconductor chip 3 and to the contact elements formed from the copper foil, these contact elements being accessible through the further recesses in the plastic film 1.
  • a second semiconductor chip 4 is arranged on the first semiconductor chip 3 and is electrically connected to the first semiconductor chip 1 via bond wires 5.
  • the second semiconductor chip 4 can be connected to the first semiconductor chip 3, for example, by means of an insulating adhesive.
  • the circuit areas of the first semiconductor chip 3 to be protected are shown in FIG Arranged according to the invention such that they are covered by the second semiconductor chip 4 and thus can not be examined optically. If the second semiconductor chip 4 were removed, the bond wires 5, 6 would tear off, so that the circuits realized on the semiconductor chips would no longer function and thus an examination of the charge potentials arising on lines would be prevented.
  • a stiffening ring 7, which can be made of metal, for example, is arranged on the plastic film 1 in such a way that it at least holds the
  • this stiffening ring 7 is filled with a plastic compound 8, for example a resin 9.
  • FIG. 2 shows a second variant of a carrier module according to the invention, in which the same parts are provided with the same reference numbers.
  • the two semiconductor chips 3, 4 are not electrically connected to one another via bond wires.
  • at least one of the two semiconductor chips 3, 4 has contact areas 10 protruding above the chip surface, which correspond in their spatial arrangement to corresponding contact areas on the respective other semiconductor chip.
  • the semiconductor chips 3, 4 are now connected to one another in such a way that their surfaces having the circuits are oriented toward one another. In this particularly advantageous manner, an optical examination is not possible with either of the two semiconductor chips 3, 4 as long as they are connected to one another. However, if they are separated from one another, neither of the two chips is functional and cannot be examined for this reason either.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Business, Economics & Management (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Accounting & Taxation (AREA)
  • Strategic Management (AREA)
  • General Business, Economics & Management (AREA)
  • Credit Cards Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)

Abstract

Zum Schutz vor einer optischen Analyse werden bei einem Trägermodul zwei Halbleiterchips aufeinander derart angeordnet, daß sie nur funktionsfähig sind, wenn sie elektrisch miteinander verbunden sind.

Description

Beschreibung
Trägermodul
Die Erfindung betrifft ein Trägermodul, insbesondere zum Ein¬ bau in einen kartenförmigen Datenträger, mit einem Kontakt- elemente aufweisenden Tragerelement und mit zumindest zwei Halbleiterchips, die auf dem Trägerelement angeordnet und elektrisch mit den Kontaktelementen verbindbar sind. Ein sol¬ ches Trägermodul ist beispielsweise aus der EP 0 193 856 Bl bekannt. Bei dem dortigen Trägermodul sind auf einem Substrat eine Anzahl Kontaktelemente angeordnet, die über ein Lei¬ tungsnetzwerk mit in Ausnehmungen des Substrats angeordneten Halbleiterchips elektrisch verbunden sind. Durch dieses Lei¬ tungsnetzwerk sind auch die Halbleiterchips untereinander elektrisch miteinander verbunden.
In Halbleiterchips für Anwendungen in kartenförmigen Daten- trägem, sogenannten Chipkarten, sind meistens nicht-flüch¬ tige Speicher, wie beispielsweise EEPROMs und eine diese steuernde oder die aus dem Speicher ausgelesenen Daten verar¬ beitende Logikschaltung realisiert. Da die abgespeicherten Daten oftmals einen Geldbetrag repräsentieren oder in anderer Weise einen Wert darstellen, findet meist eine Benutzungsbe- richtigungsprüfung statt, bei der ein geheimer Code benutzt wird. Außerdem können die für die Prüfung benötigten Schal¬ tungen einen geheim zu haltenden Aufbau haben. Aus diesem Grund müssen die Halbleiterchips vor einer Untersuchung ge- schützt werden. Die in den nicht-flüchtigen Speicherbereichen gespeicherten Daten können durch technologische Maßnahmen vor einem direkten Erkennen der gespeicherten Ladungszustände ge¬ schützt werden, jedoch ist es nach wie vor möglich, aus den Ladungszuständen auf den den Speicher mit der Logikschaltung verbindenden Leitungen beim Zugriff auf den Speicherinhalt auf die dort gespeicherten Daten zu schließen. Hierzu muß allerdings die Logikschaltung funktionsfähig sein. Die Aufgabe der Erfindung besteht somit darin, ein Trägermo¬ dul anzugeben, bei dem eine Untersuchung geheimer Bestand¬ teile verhindert ist.
Die Aufgabe wird bei einem gattungsgemäßen Trägermodul da¬ durch erreicht, daß zumindest ein Halbleiterchip auf einen anderen Halbleiterchip angeordnet und mit diesem elektrisch derart verbunden ist, daß eine bestimmungsgemäße Funktion der auf dem Halbleiterchip realisierten Schaltung(en) nur bei Vorhandensein dieser Verbindung gegeben ist.
Wenn hierbei die geheimzuhaltenden Schaltungsbestandteile wie die Speicher oder auch nur die Speicherbereiche, in denen beispielsweise Geheimcodes stehen und geheimzuhaltende Logik¬ teile, wie beispielsweise Pseudozufallsgeneratoren zum Ver¬ schlüsseln von Daten in dem unteren Halbleiterchip realisiert sind, lassen sich diese nicht erkennen, da der obere Chip sie verdeckt. Wenn jedoch der obere Chip entfernt wird, wird die Verbindung zwischen den Chips unterbrochen, so daß der untere Chip nicht mehr funktionsfähig ist und somit auf dessen Lei¬ tungen keine zu untersuchenden Ladungsmuster entstehen kön¬ nen.
In besonders vorteilhafter Weise wird der obere Chip mit der Oberfläche, auf der die Schaltung realisiert ist, zur ent¬ sprechenden, die Schaltung aufweisenden Oberfläche des unte¬ ren Chips hin orientiert auf diesem angeordnet. Auf diese Weise kann auch der obere Chip nicht optisch untersucht wer- den, ohne die beiden Chips voneinander zu trennen und somit deren Funktionsfähigkeit zu unterbrechen.
Es ist aber auch möglich, die beiden Chips in gleicher Rich¬ tung orientiert aufeinander anzuordnen und eine elektrische Verbindung über Bonddrähte zu schaffen. Diese sollten dann aber so kurz sein, oder derart angebracht sein, beispiels- weise auf zumindest zwei Seiten des oberen Chips, daß sie bei Entfernen des oberen Chips abreißen.
Das Trägerelement kann entweder eine metallaminierte Kunst- stoffolie oder ein Leadframe sein. Unter einem Leadframe soll hier verstanden werden, daß in üblicher Weise Kontaktelemente mit einem Leiterrahmen verbunden sind und von diesem in des¬ sen Mitte ragen. Nach einer Fixierung der zuerst freien Enden der Kontaktelemente mittels eines Gehäuses, werden die Kon- taktelemente aus dem Leiterrahmen ausgestanzt oder auf son¬ stige Weise von diesem getrennt .
Die Erfindung soll nachfolgend anhand eines Ausführungsbei- spiels mit Hilfe von Figuren näher erläutert werden. Dabei zeigt:
Figur 1 eine erste Variante des erfindungsgemäßen Trägermo¬ duls und Figur 2 eine zweite Variante des erfindungsgemäßen Trägermo- duls.
In Figur 1 ist eine Kunststoffolie 1 einseitig mit einer Me¬ tallfolie, beispielsweise einer Kupferfolie laminiert. In die Kupferfolie 2 sind Schlitze 8 geätzt, so daß elektrisch von- einander isolierte Kontaktelemente entstehen. Die Kunststoff- folie 1 weist Ausnehmungen auf, in deren mittlere ein erster Halbleiterchip 3 angeordnet, beispielsweise geklebt ist. Bonddrähte 6 sind sowohl mit diesem ersten Halbleiterchip 3 als auch mit den aus der Kupferfolie gebildeten Kontaktele- menten verbunden, wobei diese Kontaktelemente durch die wei¬ teren Ausnehmungen in der Kunststoffolie 1 zugänglich sind. Auf dem ersten Halbleiterchip 3 ist ein zweiter Halbleiter¬ chip 4 angeordnet und mit dem ersten Halbleiterchip 1 über Bonddrähte 5 elektrisch verbunden. Der zweite Halbleiterchip 4 kann beispielsweise mittels eines Isolierklebers mit dem ersten Halbleiterchip 3 verbunden sein. Die zu schützenden Schaltungsbereiche des ersten Halbleiterchips 3 sind in erfindungsgemäßer Weise derart angeordnet, daß sie durch den zweiten Halbleiterchip 4 verdeckt werden und somit nicht optisch untersucht werden können. Bei Entfernen des zweiten Halbleiterchips 4 würden die Bonddrähte 5, 6 abreißen, so daß die auf den Halbleiterchips realisierten Schaltungen nicht mehr funktionieren würden und somit eine Untersuchung der auf Leitungen entstehenden Ladungspotentiale verhindert wäre. Zum mechanischen Schutz der Halbleiterchips 3, 4 ist ein Verstei¬ fungsring 7, der beispielsweise aus Metall sein kann, auf der Kunststoffolie 1 derart angeordnet, daß er zumindest die
Halbleiterchips und die Bonddrähte umgibt. Das Innere dieses Versteifungsrings 7 ist mit einer Kunststoffmasse 8, bei¬ spielsweise einem Harz 9, aufgefüllt.
Figur 2 zeigt eine zweite Variante eines erfindungsgemäßen Trägermoduls, bei dem gleiche Teile mit gleichen Bezugszei¬ chen versehen sind. Im Unterschied zur ersten Variante sind hier die beiden Halbleiterchips 3, 4 nicht über Bonddrähte elektrisch miteinander verbunden. Hier weist zumindest einer der beiden Halbleiterchips 3, 4 über die Chipoberfläche ra¬ gende Kontaktflächen 10 auf, die in ihrer räumlichen Anord¬ nung mit entsprechenden Kontaktfl chen auf dem jeweils ande¬ ren Halbleiterchip korrespondieren. Die Halbleiterchips 3, 4 werden nun derart miteinander verbunden, daß ihre die Schal- tungen aufweisenden Oberflächen zueinander hin orientiert sind. Auf diese besonders vorteilhafte Weise ist eine opti¬ sche Untersuchung bei keinem der beiden Halbleiterchips 3, 4 möglich, solange sie miteinander verbunden sind. Werden sie jedoch voneinander getrennt, so ist keiner der beiden Chips funktionsfähig und kann auch aus diesem Grund nicht unter¬ sucht werden.

Claims

Patentansprüche
1. Trägermodul, insbesondere zum Einbau in einen kartenför¬ migen Datenträger, mit einem Kontaktelemente aufweisenden Trägerelement, mit zumindest zwei Halbleiterchips, die auf dem Trägerelement angeordnet und elektrisch mit den Kontaktelementen verbindbar sind, wobei zumindest ein Halbleiterchip auf einem anderen Halblei- terchip angeordnet und mit diesem elektrisch derart verbunden ist, daß eine bestimmungsgemäße Funktion der auf dem Halblei¬ terchip realisierten Schaltung(en) nur bei Vorhandensein die¬ ser Verbindung gegeben ist.
2. Trägermodul nach Anspruch 1, dadurch gekennzeichnet, daß das Trägerelement ein Leadframe ist.
3. Trägermodul nach Anspruch 1, dadurch gekennzeichnet, daß das Trägerelement eine metallaminierte, insbesondere kupfer- laminierte, Kunststoffolie ist, bei dem die Kontaktelemente durch aus dem Metallaminat geätzte Strukturen gebildet sind.
4. Trägermodul nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die elektrischen Verbindungen Bondverbindungen sind.
5. Trägermodul nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die Halbleiterchips derart auf¬ einander angeordnet sind, daß deren elektrische Verbindung bei Entfernen des oberen Halbleiterchips unterbrochen wird.
6. Trägermodul nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die Halbleiterchips derart mit¬ einander verbunden sind, daß ihre die Schaltungen aufweisen- den Oberflächen zueinander orientiert sind.
7. Trägermodul nach Anspruch 6, dadurch gekennzeichnet, daß die elektrische Verbindung der Halbleiterchips mittels bei zumindest einem der Halbleiterchips über die Chipoberfläche ragender, einander zugeordneter Kontaktflächen erfolgt.
PCT/DE1996/000549 1995-03-30 1996-03-29 Trägermodul WO1996030944A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP8528785A JPH10505959A (ja) 1995-03-30 1996-03-29 キャリア・モジュール
EP96907301A EP0818023A2 (de) 1995-03-30 1996-03-29 Trägermodul

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19511775.1 1995-03-30
DE19511775A DE19511775C1 (de) 1995-03-30 1995-03-30 Trägermodul, insb. zum Einbau in einen kartenförmigen Datenträger, mit Schutz gegen die Untersuchung geheimer Bestandteile

Publications (2)

Publication Number Publication Date
WO1996030944A2 true WO1996030944A2 (de) 1996-10-03
WO1996030944A3 WO1996030944A3 (de) 1996-11-28

Family

ID=7758224

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1996/000549 WO1996030944A2 (de) 1995-03-30 1996-03-29 Trägermodul

Country Status (5)

Country Link
EP (1) EP0818023A2 (de)
JP (1) JPH10505959A (de)
KR (1) KR19980703395A (de)
DE (1) DE19511775C1 (de)
WO (1) WO1996030944A2 (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19681689C2 (de) * 1995-12-20 2001-05-10 Intel Corp Verfahren zur Herstellung eines gesichertern Halbleiterbauelementes mit Analysierschutz
DE10065747A1 (de) * 2000-12-29 2002-07-11 Infineon Technologies Ag Schaltungsanordnung
US6422473B1 (en) 1996-12-27 2002-07-23 Rohm Co., Ltd. Circuit chip mounted card and circuit chip module
US8695881B2 (en) 2004-06-30 2014-04-15 Nxp B.V. Chip card for insertion into a holder

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19701165C1 (de) * 1997-01-15 1998-04-09 Siemens Ag Chipkartenmodul
FR2764403B1 (fr) * 1997-06-09 1999-09-10 Ckd Sa Procede pour la protection physique de l'echange de donnees confidentielles, ainsi qu'un equipement mettant en oeuvre ledit procede
DE19735170A1 (de) * 1997-08-13 1998-09-10 Siemens Ag Chipmodul, insbesondere für kontaktbehaftete Chipkarten, mit nebeneinander angeordneten Chips
DE19928733A1 (de) * 1999-06-23 2001-01-04 Giesecke & Devrient Gmbh Halbleiterspeicher-Chipmodul
FR2797075B1 (fr) * 1999-07-26 2001-10-12 Gemplus Card Int Procede de fabrication de dispositif portable a circuits integres, de type carte a puce de format reduit par rapport au format standard
EP1100058A1 (de) * 1999-11-12 2001-05-16 Infineon Technologies AG Elektronisches Bauelement und Verfahren zum Schützen einer in dem Bauelement enthaltenen integrierten Schaltung
WO2001052184A2 (de) * 2000-01-11 2001-07-19 Infineon Technologies Ag Chipkartenanordnung
EP1136941A1 (de) * 2000-03-24 2001-09-26 Infineon Technologies AG Tragbare Datenträgeranordnung
DE10139414A1 (de) * 2001-08-17 2003-02-27 Giesecke & Devrient Gmbh Halbleiterschaltungsanordnung mit biometrischem Sensor und Auswerteeinheit
DE10205208A1 (de) * 2002-02-08 2003-09-18 Conti Temic Microelectronic Schaltungsanordnung mit einer mit einem programmierbaren Speicherelement bestückten Leiterplatte

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0292658A2 (de) * 1987-05-23 1988-11-30 Motorola, Inc. Chipkarten
EP0414316A2 (de) * 1989-08-24 1991-02-27 Philips Patentverwaltung GmbH Integrierte Schaltung
EP0417648A2 (de) * 1989-09-09 1991-03-20 Mitsubishi Denki Kabushiki Kaisha Karte mit integrierter Schaltung
US5233505A (en) * 1991-12-30 1993-08-03 Yeng-Ming Chang Security device for protecting electronically-stored data

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0292658A2 (de) * 1987-05-23 1988-11-30 Motorola, Inc. Chipkarten
EP0414316A2 (de) * 1989-08-24 1991-02-27 Philips Patentverwaltung GmbH Integrierte Schaltung
EP0417648A2 (de) * 1989-09-09 1991-03-20 Mitsubishi Denki Kabushiki Kaisha Karte mit integrierter Schaltung
US5233505A (en) * 1991-12-30 1993-08-03 Yeng-Ming Chang Security device for protecting electronically-stored data

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19681689C2 (de) * 1995-12-20 2001-05-10 Intel Corp Verfahren zur Herstellung eines gesichertern Halbleiterbauelementes mit Analysierschutz
US6422473B1 (en) 1996-12-27 2002-07-23 Rohm Co., Ltd. Circuit chip mounted card and circuit chip module
DE10065747A1 (de) * 2000-12-29 2002-07-11 Infineon Technologies Ag Schaltungsanordnung
US8695881B2 (en) 2004-06-30 2014-04-15 Nxp B.V. Chip card for insertion into a holder

Also Published As

Publication number Publication date
EP0818023A2 (de) 1998-01-14
DE19511775C1 (de) 1996-10-17
WO1996030944A3 (de) 1996-11-28
JPH10505959A (ja) 1998-06-09
KR19980703395A (ko) 1998-10-15

Similar Documents

Publication Publication Date Title
EP0780005B1 (de) Trägerelement für integrierten schaltkreis
DE69504208T2 (de) Sicherheitsvorrichtung mit einem elektronischen speicher
DE69220613T2 (de) Gegossene optische Modulanordnung
EP0818023A2 (de) Trägermodul
DE4240897C2 (de) Schaltungsmodul
EP0735507A2 (de) Kontaktiereinheit für kartenförmige Trägerelemente
DE10147955A1 (de) Halbleitervorrichtung
WO1995024019A1 (de) Chipkarte mit mehreren mikrokontrollern
WO2005091366A2 (de) Halbleitermodul mit einem kopplungssubstrat und verfahren zur herstellung desselben
DE4034225A1 (de) Datentraeger fuer identifikationssysteme
DE69004581T2 (de) Plastikumhüllte Hybrid-Halbleiteranordnung.
DE69524724T2 (de) Elektronische schaltungspackung
WO1999005647A1 (de) Kontaktlos betreibbarer datenträger
EP0998724B1 (de) Verfahren zur herstellung eines chipmoduls
DE69933837T2 (de) Unterlage für elektrische schaltanordnung mit mitteln die entkoppeln vermeiden
EP1247250B1 (de) Chipkartenanordnung
DE60037717T2 (de) Datenträger mit integriertem schaltkreis und übertragungsspule
DE2415047C3 (de)
DE102004010299B4 (de) Infrarot-Empfänger-Chip
DE19609149C2 (de) Chipkarte
DE69209387T2 (de) Versiegelte Flip-Chip-Halbleiteranordnung
DE10005620A1 (de) Schaltungsanordnung
DE10142118B4 (de) Elektronisches Bauteil mit wenigstens zwei gestapelten Halbleiterchips sowie Verfahren zu seiner Herstellung
DE69211053T2 (de) Modul-Konstruktion einer Leistungsschaltungsanordnung von hoher Kompaktheit und Leistungsfähigkeit für Wärme-Zerstreuung
DE19721918C2 (de) Chipkarte und Verfahren zu deren Herstellung

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 96193024.1

Country of ref document: CN

AK Designated states

Kind code of ref document: A2

Designated state(s): CN JP KR RU UA US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

AK Designated states

Kind code of ref document: A3

Designated state(s): CN JP KR RU UA US

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1996907301

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 1019970706800

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 1996907301

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1019970706800

Country of ref document: KR

WWW Wipo information: withdrawn in national office

Ref document number: 1996907301

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 1019970706800

Country of ref document: KR