Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation

Definitions

• the present invention relates to a method for manufacturing an MS field effect semiconductor device, and more particularly, to a single or multilayer gate structure of a MS field effect semiconductor device in which an effective gate insulating film thickness changes according to a gate voltage.
• MIS-FET 'i IS-FET formed by the manufacturing method according to the present invention is a logic circuit., 5. RA! ⁇ Static random access memory '', etc., and a method of manufacturing an MIS-FET that can achieve an increase in the noise ratio at the time of low voltage operation with an increase in the / 5 ratio without increasing the chip size. It is.
• MOS-FET MOS-FET having an n-type channel (hereinafter referred to as NM ⁇ S, and in the case of having a p-type channel as PMOS), p ⁇ -ell (or p-type semiconductor substrate) is used.
• a field oxide film 2 is formed on the surface of 1 by a selective oxidation method to define an element region.
• a thermal oxide film 3 is formed in this element region, and a high impurity concentration polysilicon layer 4 serving as a gate electrode is deposited thereon (FIG. 21 (a)).
• phosphorus (P) is doped at a high concentration, and a low-resistance polysilicon layer 4 is formed by thermal diffusion.
• the polysilicon layer 4 and the thermal oxide film 3 are anisotropically etched through a photolithography process to form a gate insulating film 5 and a gate electrode 6. Thereafter, usually, n-type impurities are ion-implanted at a low dose using the gate electrode 6 as a mask (FIG. 21 (b)). Subsequently, after an oxide film is deposited on the entire surface by the CVD method, anisotropic etching is performed to form an insulating film 7 (hereinafter referred to as a spacer oxide film) on the side surface of the gate electrode 6. To achieve.
• the width of the spacer oxide film 7 later defines an n-type source and drain (hereinafter, abbreviated as S / D) region which gives an LDD (Lightly Doped Drain-Source) structure.
• S / D n-type source and drain
• LDD Lightly Doped Drain-Source
• the M 0 S—FET shown in Fig. 21 (e) is a typical structure suitable for super LS1, and the gate oxide film 5 'has a thickness of about 150 A and the gate electrode 6 has a thickness of 1 500 to 2000 A, and the gate electrode 6 is heavily doped with impurities so as not to be depleted even when the gate-source voltage V gs is large.
• Fig. 22 shows an inverter circuit which is a basic component of the mouthpiece circuit, where 33 is a bule-down transistor and 34 is a pull-up transistor.
• V IL V t D (1)
• Vout (V IH -V t D) (3)
• V OH Vdd- V t u (V OH) (5)
• V t D > V tu is the threshold voltage
• Vout is the output voltage
• Vdd is the power supply voltage
• k is a constant
• noisyzuma one Jin NM H of noisyzumajin NM L and High side Low side of I converter circuit is expressed by the following equation.
• Such an inverter circuit is used not only for various logic circuits but also for configuring an SRAM memory cell.
• Figure 24 shows a high-resistance type SRAM circuit. These are bit lines and anti-bit lines, and are connected to a power supply via a pull-up element (not shown).
• M ⁇ S transistors 3>> 38 are transfer transistors, their drains are connected to bit line 35 and anti-bit line 36, and their sources are drive transistors or burst elements M 0 S
• the drains of the transistors 39 and 40 are connected to one ends of the high resistances 41 and 42.
• the sources of the MOS transistors 39> 40 are connected to the ground Vss, and the other ends of the high resistances 41 and 42 are connected to the power supply voltage V.
• 4 3 and 4 4 are storage nodes.
• bit line 35 and the anti-bit line 36 are pre-charged to a certain level (V dd to V dd-V t), and 4 5 to High level (power supply voltage Vdd), reads out the write signal by amplifying a voltage difference between bit line 35 arising in the counter bit lines 3 6 by a sense amplifier c
• the circuit configuration of each of the MOS transistors 37 and 39 and the MOS transistors 38 and 40 corresponds to the inverter shown in FIG.
• the output voltages V 1 and V 2 of the respective inverters are the input voltages of the opposing inverters
• the noise margin can be evaluated based on the evaluation diagram shown in FIG.
• the triangles shown in the evaluation diagrams are used to evaluate the noise margin, and indicate that the larger the diameter, the larger the noise margin and the more stable the operation.
• a / 5 ratio of 4 means an increase in the chip size, that is, an increase in the chip size.
• the chip size is increased.
• the size of the package for storing the chips is also large.
• the transfer transistors 3 7 and 3 8 shown in FIG. A method has been proposed in which the oxide film is made thicker than the gate oxide films of the driving transistors 39 and 40 to eliminate the increase in chip size (O. Sakamoto: A Compact
• An object of the present invention is to provide a method of manufacturing an MIS-FET in which the value of Cox W / L) changes in accordance with a change in the gate-source voltage, and a more preferable manufacturing method thereof.
• the present invention provides a method of manufacturing an MIS-FET capable of changing the // ratio of an inverter formed with the same chip size used for a logic circuit, a SRAM circuit, or the like, and a more preferable manufacturing method thereof. It is intended to provide.
• the manufacturing method according to the present invention that achieves the above object basically provides an MIS-FET capable of positively changing an effective gate insulating film by a gate voltage. More specifically, the transistor controls a gate-source voltage.
• This is a method for manufacturing an MIS-FET having a gate electrode portion that generates a depletion layer in accordance with an increase in the absolute value of the gate-source voltage when applied in the ON direction. Specifically, it is as follows.
• the first manufacturing method includes the steps of: forming an insulating layer serving as a gate insulating film on a semiconductor substrate of the first conductivity type or on an element region provided in the semiconductor layer; When a gate-source voltage is applied in a direction in which the transistor is turned on, a layer serving as a gate electrode portion that generates a depletion layer in accordance with an increase in the absolute value of the gate-source voltage is formed, and then the gate electrode is formed.
• the source / drain diffusion layer is formed by selectively etching a layer to be a part and forming a source / drain diffusion layer by ion-implanting a second conductivity type impurity.
• An insulating layer serving as a gate insulating film is formed on a semiconductor substrate of the first conductivity type or an element region provided in the semiconductor layer, on or above the insulating layer, and a gate-source voltage is applied in a direction in which the transistor is turned on.
• a layer serving as a gate electrode portion that generates a depletion layer in accordance with an increase in the absolute value of the gate-source voltage is formed on the layer serving as the gate electrode portion.
• Melting point metal layer After forming a deposited layer with a melting point metal compound layer, a gate electrode portion and a high melting point metal portion or a laminated layer comprising a deposited layer composed of the refractory metal layer and a refractory metal compound layer or a refractory metal compound layer.
• the structure is formed by:!: Tuning, and further, ion implantation of impurities of the second conductivity type is performed to form a source / drain diffusion layer.
• the high melting point metal layer is formed on a layer including the gate electrode. Thereafter, the layer may be compounded, for example, silicified by heat treatment, or the refractory metal layer may be heat-treated in a nitrogen atmosphere to nitride and simultaneously compound (silicide) the layer.
• an insulating layer serving as a gate insulating film is provided on a semiconductor substrate of the first conductivity type or on an element region provided in the semiconductor layer, on or above the insulating layer, between a gate and a source.
• a first gate electrode portion that generates a depletion layer in accordance with an increase in the absolute value of the gate-source voltage is used as the first gate electrode portion.
• the source / drain diffusion layers are formed by ion-implanting conductive impurities.
• an insulating layer serving as a gate insulating film is formed on a semiconductor substrate of the first conductivity type or an element region provided in the semiconductor layer, and a gate insulating film is formed on or above the insulating layer.
• a source-to-source voltage is applied in a direction in which the transistor turns on, a layer serving as a first gate electrode portion that generates a depletion layer in accordance with an increase in the absolute value of the gate-to-source voltage is referred to as a first gate electrode.
• a high melting point metal layer or a high melting point metal compound layer or a deposited layer of a high melting point metal layer and a high melting point metal compound layer on or above the layer serving as the gate electrode portion of After forming a layer to be the second gate electrode part on the upper side, the first gate electrode part, the high melting point metal part or the high melting point metal compound part, or the deposition comprising the high melting point metal layer and the high melting point metal compound layer.
• the stacked structure including the layer portion and the second gate electrode portion is etched. Formed by ring, and forms a source over scan / drain diffusion layers and further Ion implanting second conductivity type impurity.
• an insulating layer serving as a gate insulating film is provided on a semiconductor substrate of the first conductivity type or on an element region provided in the semiconductor layer.
• a layer serving as a first gate electrode portion that generates a depletion layer in accordance with an increase in the absolute value of the gate-source voltage is referred to as the first gate electrode portion.
• Forming an impurity diffusion preventing layer on the first layer, and a layer serving as a second gate electrode portion on the impurity diffusion preventing layer forming a gate insulating film, a first gate electrode portion, an impurity diffusion preventing portion and a second layer.
• a stacked structure having the gate electrode portion is formed by etching, and a second conductivity type impurity is ion-implanted to form a source / drain drain diffusion layer.
• an insulating layer serving as a gate insulating film is provided on a semiconductor substrate of a first conductivity type or an element region provided in a semiconductor layer, and a gate source is provided on or above the insulating layer.
• the deposited layer consisting of the compound layer and the refractory metal layer and the second gate A source Z drain diffusion layer is formed by forming a laminated structure having a gate electrode portion by etching, and further ion-implanting a second conductivity type impurity using the second gate electrode portion as a mask. .
• an insulating layer serving as a gate insulating film is provided on an element region provided in a semiconductor substrate or a semiconductor layer of the first conductivity type, on a gate insulating film or above the gate insulating layer.
• a low-resistance compound layer and an impurity diffusion prevention layer are partially formed by heat treatment, and at least a gate insulating film, a low-resistance compound layer and an impurity diffusion prevention layer or a low-resistance compound layer, a high-melting metal layer and an impurity diffusion layer are formed.
• a layered structure including a deposited layer portion made of a prevention layer is formed by etching, and a source-drain diffusion layer is formed by ion-implanting an impurity of the second conductivity type.
• an insulating layer serving as a gate insulating film is formed on a semiconductor substrate of the first conductivity type or on an element region provided in the semiconductor layer, and a gate insulating film is formed on or above the insulating film.
• a layer to be a gate electrode portion that generates a depletion layer in accordance with an increase in the absolute value of the source-to-source voltage; etching the layer to be the gate electrode portion to form a gate electrode portion; Using the electrode portion as a mask, a second conductivity type impurity is ion-implanted to form a source-Z drain diffusion layer having a low impurity concentration, an insulating film is formed on a side surface of the gate electrode portion, and the gate electrode portion is formed.
• the ion implantation of the impurity of the second conductivity type using a mask is to form a source nodrain diffusion layer having a high impurity concentration.
• a layer serving as a gate electrode portion, a first gate electrode portion, or a second gate electrode portion is a semiconductor layer represented by polysilicon, and a second layer is formed on the semiconductor layer. It is preferable to form the conductive type impurity by ion implantation.
• a step of forming an LDD structure may be added. That is, a low-concentration impurity is ion-implanted using the gate electrode portion or the like as a mask, and then a high-concentration impurity is implanted using the spacer oxide film and the gate electrode or the like as a mask.
• the impurity is ion-implanted into the device region between the gate film and the source / drain diffusion layer, in other words, the device between the transistor channel region and the source Z drain diffusion layer.
• a source / drain diffusion layer having an impurity concentration lower than the impurity concentration of the source / drain diffusion layer can be formed.
• the source nodrain diffusion layer is formed in a self-aligned manner using the second gate electrode portion as a mask.
• the gate electrode portion or the first gate electrode portion is used. It is not necessary to form a refractory metal layer on the layer and then perform a heat treatment to compound the entire refractory metal layer. This compounding may be silicidation or nitriding. In this heat treatment, it is also preferable to heat-treat the refractory metal layer in a nitrogen atmosphere.
• This impurity diffusion preventing layer is preferably a refractory metal layer or a refractory metal compound layer (for example, a refractory metal nitride).
• a ninth manufacturing method is a method for manufacturing an MIS field-effect semiconductor device that is a pull-down transistor and a bull-up transistor that constitute an inverter. That is, when a gate-source voltage is applied on or above the gate insulating film of the pull-down transistor in a direction in which the pull-down transistor is turned on, a depletion layer is not generated even if the gate-source voltage increases.
• a gate electrode portion doped with a high impurity concentration is formed on the gate insulating film of a bull-up transistor or when a gate-source voltage is applied in a direction in which the transistor is turned on, the gate is turned on. Low concentration enough to create a depletion layer as the absolute value of the source-to-source voltage increases To form a gate electrode portion doped with impurities.
• a step of forming a second gate electrode portion made of a high melting point metal layer or a high melting point metal compound layer on or above the gate electrode portion of the pull-up transistor it is necessary to further add a step of forming a second gate electrode portion made of a high melting point metal layer or a high melting point metal compound layer on or above the gate electrode portion of the pull-up transistor. It is suitable. Another gate electrode is formed on or above the gate electrode portion of the pull-up transistor, which is composed of a semiconductor layer doped with impurities at such a high concentration that a depletion layer is not generated even if the gate-source voltage increases. A step of forming a portion may be further added, or an impurity diffusion layer or a low-resistance compound layer may be formed between another gate electrode portion. Further, when another gate electrode portion is provided on or above the gate electrode portion, ion implantation is performed by using this another gate electrode as a mask, and the source Z drain diffusion layer of the pull-up transistor is formed. It is also preferable to form
• a tenth manufacturing method is a method for manufacturing a MIS field-effect semiconductor device, which is a driving transistor and a transfer transistor constituting an SRAM cell. That is, when a gate-source voltage is applied on or above a gate insulating film of a transfer transistor in a direction in which the transistor turns on, a depletion layer is generated in accordance with an increase in the absolute value of the gate-source voltage.
• the gate electrode portion is formed so as to be doped with impurities at such a high concentration that a depletion layer is not generated even if the inter-voltage increases.
• a step of forming a second gate electrode portion made of a high melting point metal layer or a high melting point metal compound layer on or above the gate electrode portion of the transfer transistor is further added, or the gate of the transfer transistor is added.
• an impurity diffusion layer or a low-resistance compound layer may be formed between the another gate electrode portion and the gate electrode portion.
• another gate may be formed on or above the gate electrode portion.
• the expression “on or above” is often used as typified by “on or above the gate insulating film”, “on or above the gate electrode”, etc. Have been.
• This expression is intended to mean, for example, when taking a gate insulating film as an example, not only when the next layer is arranged directly above the gate insulating film, but also when the next layer is arranged via another layer. It was done.
• the MIS-FET according to the present invention is a MIS-FET provided with a gate electrode in which a depletion layer (Depletion) occurs, and this element is temporarily referred to as a DG (Depletion Gate) -FET.
• a depletion layer Depletion
• DG Depletion Gate
• the DG-FET is an MIS-FET with a single-layer gate electrode or a multi-layer gate electrode composed of a plurality of electrode parts, and the gate electrode on each gate insulating film is a source drain on both sides of the channel region. It has an electrode part (hereinafter referred to as a low concentration electrode part) doped with impurities of the same conductivity type as the conductive layer in the region at a low concentration.
• the position of the low-concentration electrode portion in the gate electrode may be immediately above the gate insulating film or through another layer above the gate insulating film.
• the thickness of the depletion layer means an effective increase in the thickness of the gate insulating film.
• the principle of DG-FET was to actively use the increase in the effective thickness of the gate insulating film in response to the increase in the absolute value of the gate-source voltage. The / 5 ratio of the transistor can be changed without changing the thickness.
• the gate electrode G has a low-concentration electrode portion directly above the gate insulating film G. Source and drain diffusion regions are formed on the substrates at both ends of the gate electrode, and the source electrode S and the drain electrode are formed. D has been pulled out respectively.
• the gate-source voltage is set to zero volts and the drain-source voltage is set to about 0.1 V, no depletion layer will occur in the low-concentration electrode section. ( Figure 16 (a)).
• the gate-source voltage is set to the power supply voltage Vdd (for example, 3 to 5 V)
• Vdd for example, 3 to 5 V
• FIG. 19 shows an example in which the low-concentration electrode portion is disposed above the gate insulating film. That is, the low-concentration electrode portion is arranged on the substrate via the gate insulating film and the intermediate electrode portion thereover. This intermediate electrode part is functionally distinguished from the low concentration electrode part.
• a semiconductor layer such as a polysilicon layer in which impurities of the same conductive layer as the conductive layers of the source and drain regions on both sides of the channel region are heavily doped can be given. Source and drain diffusion regions are formed in the substrate at both ends of such a kind of multilayer gate electrode, and a source electrode S and a drain electrode D are drawn out, respectively.
• a depletion layer is generated in the gate electrode so as to suppress the generation of the depletion layer on the drain side as shown in Fig. 19 (d). it can.
• a low-concentration depletion layer generated in the electrode portion is connected in series with the gate insulating film and contributes to a substantial increase in the thickness of the gate insulating film.
• the n-channel DG-FET has been described.
• the principle of the DG-FET is not limited to this type of conductive element.
• the gate-source voltage V gs is set to 0 V, for example, if the drain-source voltage V ds is set to ⁇ 0.1 V, no depletion layer is generated, but the negative By applying a voltage (eg, 13 to 15 V), a depletion layer can be generated in the gate electrode.
• the phenomenon that a depletion layer is generated by the application of a bias voltage is adopted for the gate electrode, and the effective increase in the thickness of the gate insulating film is actively performed without changing the actual thickness of the gate insulating film.
• the characteristics of the DG-FET that were used for the DG-FET were applied to various applications. With this DG-FET, it is possible to increase the stability of the circuit and increase the noise margin at the time of low-voltage operation in the logic circuit, SRAM, etc. without changing the chip size. DG-FET and its specific characteristics that appear in its application field will be described later.
• the intermediate electrode portion may be arranged between the low-concentration electrode layer and the gate insulating film in the 0-doped layer. Therefore, in this manufacturing method, before the step of forming the layer to be the low concentration electrode section, the step of forming the layer to be the intermediate electrode section may be performed before the step of forming the layer to be the low concentration electrode section. The fact that such a step of forming a layer serving as an intermediate electrode portion may be inserted can be said to be common to the following manufacturing methods.
• a multilayer gate including a low-concentration electrode portion as a first electrode portion and a high-melting-point metal layer, a high-melting-point metal compound layer, or a deposited layer thereof above the low-concentration electrode portion
• Electrode type DG-FET can be configured. With such a structure, the resistance of the gate electrode of the DG_FET can be reduced.
• the high-melting-point metal layer is heat-treated to form a low-resistance compound layer (a high-melting-point metal compound layer), for example, a silicide layer, the resistance of the gate electrode of the DG-FET is further reduced. be able to.
• a low-resistance refractory metal compound layer is formed, and at the same time, impurities are removed.
• a refractory metal nitride layer having a diffusion preventing function can be formed on the low concentration electrode portion.
• the refractory metal layer remaining unreacted also has an impurity diffusion preventing function.
• This refractory metal nitride is particularly effective in the case where the impurity concentration of the low-concentration electrode portion may fluctuate because impurities diffuse toward the low-concentration electrode portion from a layer above the low-concentration electrode portion. is there.
• the low resistance layer and the impurity diffusion preventing layer can be simultaneously and easily formed in the gate electrode of the DGFET. It is not necessary that all of the high melting point metal formed on the low concentration electrode portion be changed to the low resistance layer and the impurity diffusion preventing layer, and the unreacted high melting point metal may remain. In this case, a deposited layer portion of the refractory metal layer and the refractory metal compound layer is formed in the gate electrode. The remnants of this refractory metal are 0 ⁇ ? It does not hinder the low resistance of the £.
• a multilayer gate electrode type DG-FET including a low-resistance electrode portion as a first electrode portion and a second electrode portion.
• the second electrode section is distinguished from the low-concentration electrode section, and does not generate a depletion layer even when the absolute value of the gate-source voltage increases.
• both the low-resistance electrode portion and the second electrode portion are formed of a semiconductor layer doped with impurities, the impurity concentration of the second electrode portion is increased to maintain the function of the low-concentration electrode portion. The two need to be distinguished.
• the low-concentration electrode portion and the second electrode portion which are the first electrode portion, and the high-melting-point metal portion, the high-melting-point metal compound portion interposed between them, or the lamination thereof.
• a DG-FET having a gate electrode including a portion can be formed.
• a high melting point metal portion, a high melting point metal compound portion, and the like are interposed between the low concentration electrode portion and the second electrode portion to distinguish the two and protect the low concentration electrode portion. Therefore, the stable function of the low concentration electrode section can be maintained.
• a high melting point metal part . Since a high melting point metal compound part is interposed, the resistance of the gate electrode of the DG-FET can be reduced.
• a DG-FET having a gate electrode including a low-concentration electrode portion as a first electrode portion, a second electrode portion, and an impurity diffusion preventing layer interposed therebetween is provided. Can be formed.
• This manufacturing method is used to avoid impurity diffusion between the low-concentration electrode portion and the second electrode portion, which may impair the function of the low-concentration electrode portion and, consequently, the function of the DG-FET. It is especially significant in that it can be done.
• the impurity diffusion preventing layer are a high melting point metal layer and a high melting point metal nitride layer.
• a low-resistance compound layer can be formed between the low-concentration electrode portion as the first electrode portion and the second electrode portion. That is, the resistance of the DG-FET gate electrode can be reduced by a simple process of heat treatment after formation of the refractory metal layer.
• the impurity diffusion preventing layer is formed simultaneously with the low-resistance compound layer between the low-concentration electrode portion as the first electrode portion and the second electrode portion, It is possible to simultaneously prevent the function of the DG-FET from deteriorating due to impurity diffusion that may occur between the electrode portion and the second electrode portion and reduce the resistance of the gate electrode by a simple process.
• the above first to seventh manufacturing methods may involve additional steps typified by a step of forming a so-called LDD (lightly doped drain) structure.
• LDD lightly doped drain
• the source / drain diffusion layer is distinguished from the low concentration electrode portion in terms of impurity concentration.
• An electrode portion having a high impurity concentration to be formed can be formed simultaneously with the formation of the source nodrain diffusion layer.
• the second electrode portion having a high impurity concentration contributes to lowering the resistance of the DG-FET gate electrode.
• ion implantation into the low concentration electrode portion and LDD The ion implantation for forming the structure can be performed simultaneously.
• the ninth manufacturing method of the present invention it is possible to form an inverter that does not use DG-FET as a pull-down transistor and uses DG-FET as a pull-down transistor. Further, according to the ninth manufacturing method of the present invention, it is possible to form an SRAM using DG-FET as the transfer transistor and not using DG-FET as the drive transistor. By adopting DG-FET in these circuits, it is possible to increase the / 5 ratio, which leads to an increase in the circuit stability and a noise margin during low-voltage operation without increasing the chip size.
• DG-FET may be produced by using the production methods of the above-mentioned] to -8.
• the element region may be formed by using any element isolation technique. Also, the size, shape, properties, and the like of the element isolation region are not particularly limited.
• high melting point metal examples include titanium (T i), tungsten (W), and molybdenum (M o).
• examples of the high melting point metal compound include high melting point metal silicides such as titanium silicide and tungsten silicide, and high melting point metal nitrides such as titanium nitride and tungsten nitride.
• the polysilicon layer 15 and the thermal oxide film layer 14 are selectively anisotropically etched to form a gate insulating film 16 and a low-concentration electrode portion.
• a gate electrode 17 is formed.
• this mask is used as a mask 18, or once removed, a mask 18 is formed again on the gate electrode 17 by photolithography.
• arsenic (A s) to Ion implantation at a high dose (3 E 1 5 / cm 2 ) ( Figure 1 (b)).
• a heat treatment is performed at 850 to 900 for 15 to 30 minutes to activate the ion-implanted portion and to form a high impurity concentration n + type 30 diffusion layer 23, 24.
• the low-concentration electrode section 17 is formed (FIG. 1 (c)).
• the impurity concentration forming a 1 E 1. 5 to 1 E 1 6 / by cm 3 of p Ueru 1 2 selective oxidation method on the surface 5 0 0 0 ⁇ 7 0 0 0 A Fi one field oxide film 1 3 I do.
• a 150 A thermal oxide film layer 14 serving as a gate insulating film is formed in the element region surrounded by the field oxide film.
• a polysilicon layer 15 serving as a gate electrode portion is deposited on the thermal oxide film layer 14 to a thickness of 1500 to 300 A by a CVD method, and the polysilicon layer 15 is formed on the polysilicon layer 15. Li down the (P) is implanted at a low dose (1 E 1 4 / cm 2 ) ( FIG. 2 (a);).
• the polysilicon layer 15 and the thermal oxide layer 14 are selectively anisotropically etched using a mask formed by photolithography to form a gate insulating film 16 and a gate electrode portion 17. I do.
• a mask 18 is formed on the gate electrode 17 by photolithography by removing or removing this mask as a mask 18. So After that, the phosphorus (P) is ion-implanted at a low dose (5E13 / cm ") (Fig. 2 (b)
• an oxide film of 300 OA is deposited on the entire surface by a CVD method, and a CVD film (hereinafter, referred to as a “spray”) remaining on the side surfaces of the gate electrode portion 17 and the gate insulating film 16 by anisotropic etching. 19) is formed.
• the width of the gate oxide film 19 defines an n-type SZD diffusion layer (FIG. 2 (c)).
• arsenic (A s) is ion-implanted at a high dose (3E 1) using the mask 20 on the gate electrode 17 formed by photolithography and the spacer oxide film 19 as a mask. (Fig. 2 (d);). Then, the ion-implanted portion is activated by a heat treatment at 850 to 900 for 15 to 30 minutes, and the n-type S / D diffusion layers 21 and 22 with low impurity concentration and high impurity The n + -type S / D diffusion layers 23 and 24 and the low-concentration electrode portion 17 are formed (FIG. 2 (e)).
• the manufacturing process of the second embodiment can be further simplified. That is, phosphorus was not implanted into the polysilicon layer 15 at the stage shown in FIG. 2 (a), and anisotropic etching was performed without forming the mask 18 at the stage shown in FIG. 2 (b). NOTE ON Ion re down the gate electrode unit 1 7 formed in remain exposed at low dose (5 E 1 3 / cm 2 ). By such ion implantation, the step of implanting ions into the gate electrode portion 17 and the step of implanting ions with a low impurity concentration for forming the LDD structure can be simultaneously realized.
• the manufacturing process after FIG. 2 (b) is the same as that shown in FIGS. 2 (c) to 2 (d).
• a 15 OA thermal oxide film layer 14 serving as a gate insulating film is formed in the element region surrounded by the field oxide film.
• a polysilicon layer 15 serving as a gate electrode is formed by CVD. It is deposited on the thermal oxide film layer 14 with a thickness of 1500 to 300 A.
• titanium (T i) or titanium nitride (T i N) is deposited on the polysilicon layer 15 in a thickness of 300 to 1000 A by a sputtering method, it is then subjected to a nitrogen atmosphere.
• RTP Rapid Thermal Process
• processing for example, the first time: 600-750, 15-45 seconds, the second: 75-900 ° C, 15-45 seconds
• TiSi 2 titanium silicide
• the polysilicon layer 1 5 on the silicide titanium emission layer 2 9 and titanium nitride emissions (eg T i N) layer 3 0 are simultaneously formed (Fig. 3 (a)) 0
• the titanium silicide layer 29 and the titanium nitride layer 30 are formed by depositing titanium relatively thickly or by relaxing the conditions of the RTP process (for example, by shortening the process time) to form a titanium silicide layer 29 and a titanium nitride layer 30.
• An intermediate titanium layer (not shown) may be left unreacted.
• a titanium silicide layer 29, a titanium layer and a titanium nitride layer 30 can be simultaneously formed on the polysilicon layer 15.
• a mask 18 is formed by photolithography, and this deposited layer is selectively anisotropically etched to form a gate insulating film 16, a gate electrode portion 17, a titanium silicide portion 31, and A laminate composed of the titanium nitride portion 32 is formed. This laminate may have a titanium portion between the titanium silicide portion 31 and the titanium nitride portion 32 in some cases.
• this mask is used as a mask 18 or it is removed and a mask 18 is formed on the gate electrode 17 by photolithography, and arsenic (A s) is subsequently deposited at a high doping amount ( 3 E 15 / cm 2 ) for ion injection (Fig. 3 (b)).
• the first electrode part 17 is formed (FIG. 3 (c)).
• the gate electrode 17 may be formed by anisotropically etching the layer 15c
• the impurity concentration to form a 1 E 1 5 ⁇ 1 E 1 6 / cm 3 of p Ueru 1 by two surface selective oxidation method 5 0 0 0 ⁇ 7 0 0 0 A Fi one field oxide film 1 3.
• a 150 A thermal oxide film layer 14 serving as a gate insulating film is formed in the element region surrounded by the field oxide film 13 and a gate electrode is formed on the thermal oxide film layer i4.
• a polysilicon layer 15 to be a part is deposited to a thickness of 1500 to 300 OA by a CVD method. Then,
• a titanium layer or a titanium nitride layer is deposited to a thickness of 300 to 100 A by a sputtering method.
• an RTP treatment is performed in a nitrogen atmosphere (for example, the first time: 600 to 75 ° C. 15 to 45 seconds, 2nd time: 75 to 900. C, 15 to 45 seconds), and a titanium silicide layer is formed in the contact area between the titanium layer or the titanium nitride layer and the polysilicon layer 15.
• part or all of the titanium layer is changed to a titanium nitride layer.
• a titanium silicide layer 29 and a titanium nitride layer 30 are formed on the polysilicon layer 15 and an unreacted residual titanium layer (not shown) is formed between these layers in some cases.
• this deposited layer is selectively anisotropically etched using a mask 18 formed by photolithography to form a gate insulating film 16, a gate electrode 17, a titanium silicide 31, and A laminate composed of the titanium nitride portion 32 is formed.
• the mask 18 is used as a mask or is removed and a mask is formed on the titanium nitride 31 by photolithography. Further, phosphorus (P) is ion-implanted into the exposed P-well 12 at a low dose (5E13c) (FIG. 4 (b)).
• a spacer oxide film 19 is formed on the side surface of the laminate by anisotropic etching.
• the width of the silicon oxide film 19 defines the low impurity concentration (n-type) S / D diffusion layer (Fig. 4
• element (A s) was applied at a high dose (3E 15 / cm 2 ) using the mask 20 on the titanium nitride layer 32 formed by photolithography and the spacer oxide film 19 as a mask. Inject ion into p-well 12 (Fig. 4 (d)). And 8 5 0 ⁇ 9 0
• the ion-implanted part is activated, and n-type S / D regions 21 and 22 with low impurity concentration and n + type S with high impurity concentration
• the / D diffusion layers 23 and 24 and the low concentration electrode part 17 are formed (FIG. 4E).
• Field A 15 OA thermal oxide film layer 14 is formed in the element region surrounded by the oxide film to become a gate insulating film.
• a polysilicon layer 15 serving as a gate electrode is deposited on this thermal oxide film layer 14 to a thickness of 150 to 300 A by a CVD method.
• the poly silicon co emission layer 1 5 Li down the (P) at a low dose (1 E 1 4 / cm 2 ) is ion-implanted.
• an insulating layer 25 made of silicon nitride (for example, Si 3 N 4 ) is deposited on the polysilicon layer 15 by a CVD method (FIG. 5A).
• a gate insulating film 16, a gate electrode portion 17 and an insulating film 26 are sequentially stacked by selective anisotropic 4 ′ raw etching using a mask formed by photolithography on the deposited layer. Form the body. Subsequently, the mask on the insulating film 26 is once removed, and arsenic (A s) is implanted into the P-well 12 at a high dose (3E15 / cn, 2 ) using the insulating film 26 as a mask ( Figure 5 (b)).
• the impurity concentration 1 E 1. 5 to: form the IE 1 6 / cm 3 p Ueru 1 by two surface selective oxidation method 5 0 0 0 ⁇ 7 0 0 0
• a 15 OA thermal oxide film layer 4 serving as a gate insulating film is formed in the element region surrounded by the oxide film 13, and polysilicon serving as a gate electrode portion is formed on the thermal oxide film layer 14.
• Layer 15 is deposited by CVD at a thickness of 1500-30000A.
• An insulating layer 25 made of silicon nitride is deposited on the polysilicon layer 15 by a CVD method (FIG. 6 (a)).
• this deposited layer was sequentially laminated by a selective anisotropic etching using a mask formed by photolithography, consisting of a gate insulating film 16, a gate electrode portion 17 and an insulating film 26. Form a laminate. Furthermore, P ⁇ El 1 2 low dose re down (P) to the absolute ⁇ 2 6 as a mask (5 E 1 3 / cm 2 ;) in which Ion implantation (FIG. 6 (b)) 0
• an oxide film of 300 OA is deposited on the entire surface by the CVD method. This oxide film is subjected to anisotropic etching to form a spacer oxide film 19 remaining on the side surface of the laminate (FIG. 6 (c) :).
• arsenic (A s) is ion-implanted at a high dose (3E1 ⁇ / cin 2 ) using the insulating film 26 and the spacer oxide film 19 as a mask (FIG. 6 (d)).
• a high dose 3E1 ⁇ / cin 2
• the ion-implanted part is activated, and the n-type SZD diffusion layers 21 and 22 with low impurity concentration and high impurity concentration are activated.
• n ⁇ type S./D diffusion layer 2 3, 2 4 and n-type to form the lightly doped electrode unit 1 7 (FIG. 6 (e)).
• Fee A thermal oxide layer 14 of 150 A serving as a gate insulating film is formed in the element region surrounded by the gate oxide film.
• a polysilicon layer 15 serving as a gate electrode is deposited to a thickness of 150 to 300 A by a CVD method. Then poured Li down the (P) at a low dose (1 E 1 4 / cm 2 ).
• a titanium layer or a titanium nitride layer is deposited to a thickness of 300 to 100 A by a sputtering method.
• RTP treatment is performed in a nitrogen atmosphere (for example, first time: 600 to 75, then 15 to 45 seconds, second time: 750 to 900, 15 to 45 seconds).
• a titanium silicide layer can be formed in a contact region between the titanium layer or the titanium nitride layer and the polysilicon layer 15.
• a titanium silicide layer 29 and a titanium nitride layer 30 are formed on the polysilicon layer 15 and, if necessary, a residual titanium layer (not shown) is formed between these layers. Further, an insulating layer 25 made of silicon nitride is deposited on the titanium nitride layer 30 by a CVD method (FIG. 7 (a)).
• a titanium layer is deposited by a sputtering method.
• a tungsten layer may be deposited instead of carbon, and thereafter the tungsten layer is silicified by performing the same treatment as described above. It can be left almost unreacted without being converted into a substance or nitride.
• this deposited layer is selectively anisotropically etched using a photolithographic mask to form a gate insulating film 16, a gate electrode portion 17, a silicon silicide portion 31, a titanium nitride portion 32, and an insulating film 2.
• a photolithographic mask to form a gate insulating film 16, a gate electrode portion 17, a silicon silicide portion 31, a titanium nitride portion 32, and an insulating film 2.
• the absolute ⁇ 2 6 to Ion implanting arsenic (A s) as a mask at a high dose (3 E 1 5 / cm 2 ) ( FIG. 7 (b) :).
• the ion-implanted portion is activated by performing a heat treatment at 850 to 900 for 15 to 30 minutes, and the n + type SZD regions 23, 24 and n type of high impurity concentration are activated.
• the low concentration electrode portion 17 is formed (FIG. 7 (c)).
• FIGS. 8 (a) to 8 (e) An embodiment of a method of manufacturing a DG-FET having an LDD type according to the present invention will be described with reference to FIGS. 8 (a) to 8 (e).
• the impurity concentration to form a 1 E 1. 5 to ⁇ E 1 6 / cm 3 p Ueru 1 by two surface selective oxidation method 5 0 0 0 ⁇ 7 0 0 0
• a field oxide film 1 3 A thermal oxide film layer 14 of 150 A serving as a gate insulating film is formed in the element region surrounded by the field oxide film 13.
• a polysilicon layer 15 serving as a first gate electrode portion is deposited on the thermal oxide film layer 14 to a thickness of 1500 to 300 OA by a CVD method.
• Ion implantation re down the (P) at a low dose (1 E 1 4 / cm 2 ).
• a titanium layer or a titanium nitride layer is deposited on the polysilicon layer 15 to a thickness of 300 to 1000 A by a sputtering method.
• perform RTP treatment in a nitrogen atmosphere for example, the first time: 600 to 750 seconds ; 15 to 45 seconds, the second time: 750 to 900 seconds, 15 to 45 seconds).
• part or all of the titanium layer is changed to a titanium nitride layer, and a titanium silicide layer can be formed in a contact region between the titanium layer or the titanium nitride layer and the polysilicon layer 15.
• a titanium silicide layer 29 and a titanium nitride layer 30 are formed on the polysilicon layer 15 and, if necessary, an unreacted residual titanium layer (not shown) is formed between these layers. Further depositing absolute ⁇ 2 5 by CVD on the titanium nitride layer 3 0 made of a nitride divorced (FIG 8 (a)) 0
• this deposited layer is selectively anisotropically etched using a mask formed by photolithography to form a gate insulating film 16, a gate electrode portion 17, a titanium silicide portion 31, and a titanium nitride portion.
• a laminate comprising 32 and insulating film 26 is formed.
• the Ma while either or leaving removed disk, absolute ⁇ 2 6 re down (P) as a mask low de - implanted at's weight (5 E 1 3 / cm 2 ) ( FIG. 8 (b)) .
• an oxide film of 300 A is deposited on the entire surface by a CVD method.
• anisotropic etching to form the spacer oxide film 1 9 on the side surface of the laminate (FIG. 8 (c)) 0
• arsenic (A s) is ion-implanted at a high dose (3E 15 / cm 2 :) using the insulating film 26 and the spacer oxide film 19 as a mask (FIG. 8D).
• the ion-implanted portion is activated, and the n ⁇ -type SZD diffusion layers 21, 22, and 22, with a low impurity concentration are formed.
• ⁇ + type SZ with high impurity concentration D diffusion layers 23 and 24 and n-type low concentration electrode part 17 are formed (FIG. 8 (e)) [Example 9]
• the impurity concentration to form a 1 E 1 5 ⁇ 1 E 1 6 / cm 3 of p Ueru 1 by two surface selective oxidation method 5 0 0 0 ⁇ 7 0 0 0
• a Fi one field oxide film 1 3 A 15 OA thermal oxide film layer 14 serving as a gate insulating film is formed in the element region surrounded by the field oxide film.
• a polysilicon layer 15 serving as a first gate electrode is deposited on the thermal oxide film layer 14 to a thickness of 1500 to 300 A by a CVD method.
• a polysilicon layer 27 serving as a second gate electrode is deposited on the polysilicon layer 15 to a thickness of 1500 to 300 A by a CVD method or a sputtering method (FIG. 9). (a)). Thereafter, the polysilicon layer 27 is usually heavily doped with phosphorus, and the resistance is reduced by heat treatment.
• this deposited layer is selectively anisotropically etched using a mask formed by photolithography to form a gate insulating film 16, a first gate electrode 17, and a second gate 17.
• the electrode section 28 is formed.
• arsenic (A s) is ion-implanted at a high dose (3E1 ⁇ / cm 2 ) using the second gate electrode portion 28 as a mask (FIG. 9 (b)). At this time, the ion is also injected into the second gate electrode section 28.
• the ion implantation for forming the S / D diffusion layer and the ion implantation for the second gate electrode portion 28 doped with a high concentration of impurities can be simultaneously performed. There is.
• a high melting point metal such as tungsten (W) or titanium (T i) or tungsten silicide (for example, WS i)
• tungsten silicides such as TiSi 2
• the second gate electrode portion 28 may be formed by depositing with a thickness of 1500 to 300 A by sputtering. In this case, if a refractory metal layer or a refractory metal compound layer is deposited, an RTP process is performed, and a titanium silicide layer is formed in a contact region with the polysilicon layer 15, the resistance of the gate electrode is reduced. Can be reduced, which is preferable.
• the impurity concentration to form a 1 E 1. 5 to 1 E 1 6 / by cm 3 of p Ueru selective oxidation method 1 2 surface 5 0 0 0 ⁇ 7 0 0 0 A field oxide film 1 3.
• a 150 A thermal oxide film layer serving as a gate insulating film is formed in the element region surrounded by the field oxide film.
• a polysilicon layer 15 serving as a first gate electrode portion is deposited on the thermal oxide film layer 14 to a thickness of 1500 to 300 OA by a CVD method. Then injected re down the (P) at a low dose (1 E 1 4 / cm 2 ).
• a polysilicon layer 27 serving as a second gate electrode is deposited on the polysilicon layer 15 to a thickness of 150 to 300 A (FIG. 10 (a). )). Thereafter, usually, the polysilicon layer 27 is doped with phosphorus (P) at a high concentration, and the resistance is reduced by a subsequent heat treatment. Next, this deposited layer is selectively anisotropically etched using a mask formed by photolithography .. Gate insulating film 16, first gate electrode 17, and second gate A laminate composed of the electrode portions 28 is formed. Then, a low de re down (P) a second gate electrode section 2 8 as a mask - for Ion implantation with's weight (5 E 1 3 / cm 2 :) ( Fig 1 0 (b) :).
• arsenic (A s) is ion-implanted at a high dose (3E 15 / cm 2 ) using the second gate electrode part 28 and the spacer oxide film 19 as a mask (FIG. 10 (d)). )). At this time, ions are also implanted into the second gate electrode portion 28.
• the ion implantation for forming the S.ZD diffusion layer and the ion implantation for the second gate electrode portion 28 in which impurities are doped at a high concentration can be simultaneously performed. There is an advantage.
• a high melting point metal such as tungsten and titanium or a high melting point metal silicide such as tungsten silicide / titanium silicide is deposited by CVD or
• the second gate electrode portion 28 may be formed by depositing with a thickness of 150 to 300 OA by a sputtering method.
• the impurity concentration to form a 1 E 1 5 ⁇ 1 E 1 6 / cm 3 of p Ueru 1 by two surface selective oxidation method 5 0 0 0 ⁇ 7 0 0 0
• a 15 OA thermal oxide film layer 14 serving as a gate insulating film is formed in the element region surrounded by the field oxide film 13.
• a polysilicon layer 15 serving as a first gate electrode portion is deposited to a thickness of 1500 to 300 A by a CVD method.
• low dose re down (P) (: 1 E 1 4 / cm 2;) injected with. Titanium or titanium nitride is deposited to a thickness of 300 to 1000 A by a sputtering method.
• a titanium silicide layer 29 is formed between the polysilicon layer 15 and the titanium layer or titanium nitride layer. At this time, part or all of the titanium layer is changed to a titanium nitride layer. Finally, a titanium silicide layer 29 and a titanium nitride layer 30 are formed on the polysilicon layer 15, and an unreacted residual titanium layer (not shown) is formed between these layers in some cases. I do. Thereafter, a polysilicon layer serving as a second gate electrode portion is deposited to a thickness of 150 to 300 A by a CVD method (FIG. 11A). After that, the polysilicon layer 27 is usually linked. Doping to a high concentration, and lower the resistance by subsequent heat treatment.
• this deposited layer is selectively anisotropically etched using a photolithographically formed mask to form a gate insulating film 16, a first gate electrode portion 17, and titanium silicide (Ti).
• S i 2) A laminate comprising a part 31, a titanium nitride part 32 and a second gate electrode part 28 is formed.
• the second gate electrode portion 2 8 Ion implantation arsenic (A s) at high dose (3 E 1 5 / cm 2 ) as a mask (FIG. 1 1 (b)). At this time, ions are implanted into the second gate electrode portion 28 at the same time.
• the ion implantation for forming the S / D diffusion layer and the ion implantation to the second gate electrode portion 28 which is heavily doped with impurities can be simultaneously performed. There is an advantage.
• the second gate electrode portion 28 may be formed by depositing the second gate electrode portion 28 with a thickness of 150 to 300 A.
• Embodiments of a method of manufacturing a DG-FET having an LDD structure according to the present invention will be described with reference to FIGS. 12 (a) to 12 (e).
• the impurity concentration to form a 1 E 1 5 ⁇ 1 E 1 6 / cm 3 of p Ueru 1 5 0 0 0 ⁇ 7 0 0 0 A by the second surface selective oxidation off Rudo oxide film 1 3.
• a 150 A thermal oxide layer 14 serving as a gate oxide film is formed in the element region surrounded by the field oxide film.
• a polysilicon 15 to be a first gate electrode portion is deposited to a thickness of 1500 to 300 by CVD.
• titanium or titanium nitride is deposited to a thickness of 300 to 100 OA by a sputtering method.
• nitrogen atmosphere RTP processing for example, the first time: 600 to 750, 15 to 45 seconds, the second time: 750 to 900, 15 to 45 seconds.
• a titanium silicide layer 30 can be formed in a contact region between the titanium layer or the titanium silicide layer 29 and the polysilicon layer 15.
• a titanium silicide layer 29 and a titanium nitride layer 30 remain on the polysilicon layer 15, and in some cases, an unreacted titanium layer (not shown) remains between these layers.
• a polysilicon layer serving as a second gate electrode portion by CVD is deposited in a thickness of 1 5 0 0 ⁇ 3 0 0 0 A ( FIG. 1 2 (a)) 0
• this deposited layer is selectively anisotropically etched using a mask formed by photolithography.
• a laminate composed of the titanium silicide part 32 and the second gate electrode part 28 is formed.
• phosphorus (P) is ion-implanted at a low dose (5E13 / cm 2 ) using the second gate electrode portion 28 as a mask (FIG. 12B).
• an oxide film of 300 OA is deposited on the entire surface by the CVD method.
• a spacer oxide film 19 is formed on the side surface of the laminate by anisotropic etching (FIG. 12 (c). Further, the second gate electrode 28 and the spacer oxide film 19 are formed).
• Arsenic (A s) is ion-implanted at a high dose (3E 15 / cm 2 ) as a mask (FIG. 12 (d)).
• n + -type SZD diffusion layers 23 and 24 having a high impurity concentration, the low-concentration electrode section 17 and the n--type high conductive electrode section 28 are formed (FIG. 12 (e)).
• this manufacturing method it is possible to simultaneously perform ion implantation for forming the SZD diffusion layer and ion implantation for the second gate electrode portion 28 in which impurities are doped at a high concentration. .
• Embodiment of the method for manufacturing a DG-FET having a single drain structure according to the present invention Will be described based on FIGS. I3 (a) to (c).
• a field oxide film 1 3 A thermal oxide film layer 14 of 150 persons to be a gate oxide film is formed in the element region surrounded by the field oxide film.
• polysilicon 15 serving as a first gate electrode portion is deposited on the thermal oxide film layer 14 to a thickness of 1500 to 300 A by a CVD method.
• Ion implantation re down the (P) low dose (at 1 E 1 4 / cm 2 :) .
• snow titanium (Ti) snow titanium
• a polysilicon layer serving as a second gate electrode portion is deposited to a thickness of 1500 to 300 A by a CVD method.
• RTP treatment is performed in a nitrogen atmosphere (for example, the first time: 600 to 750 seconds: 15 to 35 seconds, the second time: 780 to 900 seconds, 15 to 35 seconds).
• part or all of the titanium layer is changed to titanium silicide, and a titanium silicide layer 33 can be formed in a contact region between the titanium layer and the polysilicon layer 15.
• the gate insulating film 16, the first gate electrode portion 17, the titanium silicide portion 34, and the second gate electrode are selectively anisotropically etched using a mask formed by photolithography.
• a laminate consisting of part 28 is formed.
• a laminate covering the titanium layer is formed by anisotropic etching.
• phosphorus (P) is ion-implanted at a high dose (5E15 cm 2 ) using the second gate electrode section 28 as a mask (FIG. 13B).
• Embodiments of a method of manufacturing a DG-FET having an LDD structure according to the present invention will be described with reference to FIGS. 14 (a) to 14 (e).
• a 15 OA thermal oxide film layer 14 serving as a gate oxide film is formed in the element region surrounded by the field oxide film.
• a polysilicon 15 to be a first gate electrode portion is deposited on the thermal oxide film layer 14 by a CVD method to a thickness of 1500 to 3500 persons.
• titanium (T i) is deposited to a thickness of 300 to 1000 A by the snow and titanium method.
• RTP treatment is performed in a nitrogen atmosphere (for example, first time: 600 to 75 ° C. 10 to 25 seconds, second time: 750 to 900 ° C., 10 to 30 seconds).
• first time 600 to 75 ° C. 10 to 25 seconds
• second time 750 to 900 ° C., 10 to 30 seconds.
• part of the titanium layer is changed to a titanium nitride layer
• a titanium silicide layer is formed in a contact region between the titanium layer and the polysilicon layer 15.
• a titanium silicide layer 331, a titanium nitride layer 35, and possibly an unreacted titanium layer remain between these layers on the polysilicon layer 15.
• a polysilicon layer 27 serving as a second gate electrode portion is deposited to a thickness of 150 to 300 A by the CDV method.
• a thin titanium silicide layer 332 is formed in a contact region between titanium nitride layer 35 and polysilicon layer 27.
• the titanium nitride layer 35 may disappear for the second time depending on the RTP processing conditions.
• at least a titanium silicide layer 331, a titanium nitride layer 35, and a titanium silicide layer 332 can be formed on the polysilicon layer 15 (FIG. 14 (a)).
• this deposited layer is selectively anisotropically etched using a photolithographically formed mask to form a gate insulating film 16, a first gate electrode portion 17, and a titanium silicide portion 3.
• a laminate comprising 41, a titanium nitride portion 36, a titanium silicide portion 342, and a second gate electrode portion 28 is formed.
• the low dose of Li down the second gate electrode portion 2 8 as a mask (5 E 1 3 / cm 2 ) at which Ion implantation (Fig. 1 4 C b)) c
• an oxide film of 300 persons is deposited on the entire surface by the CVD method.
• a spacer oxide film 19 is formed on the side surface of the laminate by anisotropic etching (FIG. 14 ('c)).
• arsenic (A s) is ion-implanted at a high dose (3E 1 ⁇ C, 2 ) using the second gate electrode 28 and the base oxide film 19 as a mask (FIG. 4 (d)); Thereafter, by ripening at 850 to 900. C for 15 to 30 minutes, the ion-implanted portion is activated, and the n-type S / D diffusion layer 21.2 with a low impurity concentration is formed. 2, n-type S / D diffusion layer with high impurity concentration 2 3 ; 24, low-concentration electrode section 7 and n ⁇ -type high conductive electrode section 28 are formed (Fig. 14 (e )).
• the manufacturing method it is possible to enhance the adhesiveness of individual portions constituting the multilayer gate electrode. Further, according to this embodiment, since the titanium silicide 341 and 342, which are low-resistance compound layers, are formed, the resistance of the gate electrode can be reduced. In addition, the characteristics of the low-concentration electrode portion 17 can be maintained by the impurity diffusion preventing function of titanium nitride. Further, ion implantation for forming the SZ'D diffusion layer and ion implantation to the second gate electrode portion 28 doped with a high concentration of impurities can be performed simultaneously.
• This embodiment is a P-type channel DG-FET.
• a titanium nitride layer 35 is deposited to a thickness of 30 to 100 mm by sputtering.
• a polysilicon layer 15 serving as a low concentration electrode portion is deposited to a thickness of 1500 to 300 OA by a CVD method.
• a titanium layer or a titanium silicide layer is deposited to a thickness of 300 to 90 OA by a sputtering method. Then, a heat treatment is performed, and a contact area between the titanium nitride layer 35 and the polysilicon layer 27 is formed. Alternatively, a thin titanium silicide layer (not shown) may be formed, and a titanium silicide layer 33 may be formed between the polysilicon layer 15 and the uppermost titanium layer. If such a heat treatment is not performed, then RTP treatment in a nitrogen atmosphere (for example, the first time: 600-750, 15-35 seconds, the second stroke: 750-900) ° 15 to 35 seconds).
• a part of the titanium layer is changed to a titanium nitride layer 35, and a thin titanium silicide layer (not shown) is formed in the contact area between the titanium nitride layer 35 and the polysilicon layers 15 and 27. It is formed (Fig. 15 (a)).
• the deposited layer is selectively anisotropically etched using a mask formed by photolithography to form a gate insulating film 16, a highly conductive electrode portion 28, a titanium nitride portion 36, A laminate having at least a low concentration electrode portion 1, a titanium silicide portion 331 and a titanium nitride portion 36 is formed. Further, the titanium silicide portion 3 3 1 and the titanium nitride portions 3 6 Ion implanting boron as a mask at high dose (4 E 1 5 / cm 2 ) ( Fig. 1 5 (b)),
• the FET has a low-concentration electrode part 17 and an intermediate electrode part 28
• the feature is that it is arranged above.
• the step of implanting a low dose ion into the silicon layer 15 is performed before the step of implanting a high dose ion into the position of the 3/0 diffusion layers 23 and 24.
• the function as a mask becomes insufficient.
• Boron (B) is ion-implanted into the polysilicon layer 15 through the mask, depending on the dose amount. If this phenomenon is actively utilized, the former low-dose ion implantation can be omitted and replaced by the latter high-dose ion implantation.
• ion implantation into the second gate electrode portion or the highly conductive electrode portion can be simultaneously performed by ion implantation of a high dose into the position of the SZD diffusion layers 23 and 24. Therefore, the manufacturing process can be simplified.
• ion implantation into the low-concentration electrode portion through the mask can be performed at the same time as ion implantation with a high dose into the position of the SZD diffusion layers 23 and 24, so that the manufacturing process is simplified.
• the refractory metal portion and the refractory metal silicide portion contribute to lowering the resistance of the entire gate electrode
• the low-resistance second gate electrode portion contributes to lowering the resistance of the entire gate electrode.
• a high-conductivity electrode part or a low-resistance part is formed on the low-concentration electrode part, and this part is interposed. It also has the characteristic that it can form an omic contact.
• the high melting point metal nitride was used for the first gate electrode portion (low concentration electrode portion). It functions as an impurity diffusion prevention layer between the IGBT and the second gate electrode (highly conductive electrode), so that both electrodes can be functionally distinguished and the DG-FET is prevented from deteriorating in function and stabilized. Can be realized.
• the refractory metal silicide layer formed at the intermediate position of the multilayer gate electrode structure by the RTP process contributes to lowering the resistance value of the gate electrode and improves the mechanical strength or thermal strength of the entire gate electrode To contribute.
• the gate electrode portion 1 on or above the gate insulating film 14 is doped to a low impurity concentration such that a depletion layer is generated when the gate-source voltage is large. but high dose in order not to cause depletion (5 E 1 4 / cm 2 ) Li down (P) or injected with, it may be injected Boron (B).
• This method is particularly effective in a method of manufacturing a semiconductor device in which a plurality of transistors are arranged, when deactivating a specific DG-FET, that is, when changing to a conventional MIS-FET.
• boron (B, BF 2 ) implantation for adjusting the value of the threshold voltage Vt is performed before or after gate oxide film formation, and implantation for punch-through countermeasures is performed.
• Boron (B, BF 2) is implanted before or after the oxide film formation, or before or after the LDD implantation.
• N-channel MIS-FET the n-type well (or N-type semiconductor substrate or N-type semiconductor layer) is used to perform LDD implantation (low impurity concentration layer).
• SD implantation high impurity concentration layer
• implantation for preventing punch-through may be performed with phosphorus or arsenic.
• no depletion layer occurs in the P-channel even when the absolute value of the gate-source voltage is large.
• the low-concentration electrode section is dropped with boron (B, BF 2 ) and the threshold voltage Vt For adjustment, use phosphorus or arsenic as necessary.
• the low concentration electrode section 17 may be formed of a polysilicon layer doped with impurities at a low concentration during vapor phase growth.
• FIG. 17 shows MIS-FET, which is the basis of the present invention, that is, DG-FET and the conventional M-FET. This is a comparison between the drain current I ds and the gate 'source voltage ⁇ ; gs' for IS-FET.
• the solid line (a) in the figure indicates the first gate electrode portion of polysilicon with a low impurity concentration (1.0 E 14 / m 2 ) and a high melting point metal or
• the graph shows the characteristics of a DG-FET having a gate electrode composed of the compound or a second gate electrode portion of polysilicon doped with impurities at a high concentration.
• ( ⁇ ) is the first gate electrode of polysilicon doped with phosphorus to a high impurity concentration (5.0 E 1 / cm 2 or more) and a high melting point metal or its compound or a high concentration of impurities.
• This shows the characteristics of a conventional MIS-FET having a gate electrode composed of a second gate electrode portion made of polysilicon doped with GaAs. Both transistors have M 0 S.
• the impurity implanted into the first gate electrode portion is the same n-type as the source / drain diffusion layer.
• drain current I ds is expressed by the following equation.
• n mobility
• Cox gate insulating film capacity
• ⁇ ' dielectric constant of gate insulating film
• Lox gate insulating film thickness
• W channel width
• L channel length
• FIG 17 shows the Ids-Vgs characteristics of an n-channel transistor.
• the curve (a) shown by the solid line is the DG-FET of the present invention, and the curve (mouth) shown by the dotted line is It shows the characteristics of a conventional MIS-FET.
• the DG-FET has a drain current I ds similar to that of the conventional MIS-FET when the gate-source voltage is small.
• the rising position and inclination It is clear that the threshold voltage Vt is the same as that of the conventional MIS-FET and does not replace the conventional MIS-FET.
• the rate of increase of the drain current I ds is smaller than that of the conventional MIS-FET. Therefore, DG-FET indicates that the effective gate insulating film thickness increases as the gate-source voltage increases.
• the rate of increase of the drain current I ds can be reduced when the gate-source voltage is large.
• the gate voltage is small, there is a disadvantage that the drain current I ds becomes small and the threshold voltage V I increases.
• DG-FET does not have such problems as in the prior art.
• the solid line in FIG. 1 8 (I) shows the I ds- Vgs characteristics of the DG-F ET according to the present invention., The ball port emissions at a low impurity concentration (1. 0 E 1 4 / cm 2)
• a DG having a gate electrode consisting of a first gate electrode part of doped polysilicon and a second gate electrode part of polysilicon doped with a high melting point metal or its compound or highly doped impurities One FET.
• positive broken line in the drawing (the mouth) is doped shows an I ds- Vgs characteristics of the conventional MIS-FET, the Boron in the high impurity concentration (5. 0 E 1 4 / cm 2 or higher) It has a gate electrode composed of a first gate electrode portion of silicon and a second gate electrode portion of polysilicon doped with a high melting point metal or a compound thereof or a high concentration of impurities.
• Both transistors are the same as in FIG. 17 in that they are NMOS, but the semiconductor substrate, semiconductor layer, or well that forms the gate electrode is P-type, and the impurities implanted into the first gate electrode are It is an n-type impurity different from the channel.
• the N-MOS uses the n-type (n-conductivity-type) gate electrode portion having a low impurity concentration, thereby allowing the gate *
• the gate-source voltage is increased when a source-to-source voltage is applied in the direction in which this transistor turns on, a depletion layer can be generated.
• Solid line in the figure (I) is taupe poly Nriko first gate one gate electrode portion and the refractory metal or its compound of emissions or high concentration impurity in the ball opening emissions low impurity concentration (3 E 1 3 / cfn 2 )
• the graph shows the characteristics of a DG-FET having a gate electrode composed of a doped polysilicon second gate electrode.
• the dashed line (open) in the figure indicates that the first gate electrode of polysilicon doped with a high impurity concentration (5.0 E14 / 'cm 2 or more) in the hole and the high melting point metal or its compound or high concentration.
• MIS-FET has the characteristics of a conventional MIS-FET with a gate electrode consisting of a second gate electrode part made of impurity-doped polysilicon.
• -All transistors are PM0S, and the semiconductor substrate on which the gate electrode is formed -.
• the semiconductor layer or well is of n-type
• the source 'drain diffusion layer is of p-type
• the conductivity type of impurities implanted into the first gate electrode part with low impurity concentration is source-drain diffusion. It is the same P type as the layer.
• the drain current I ds of the DG-FET is about the same as that of the conventional MIS-FET, and the rising position of the curve It can be seen that the threshold voltage Vt does not replace that of the conventional MIS-FET since the slope is almost the same as that of the conventional MIS-FET.
• the rate of increase of the drain current I ds becomes smaller than that of the conventional MIS-FET. Therefore, it can be seen that in DG-FET, the effective thickness of the gate insulating film increases as the gate-source voltage increases.
• the first gate electrode If the impurity to be implanted is of the same n-type as the semiconductor substrate and semiconductor layer that make up the gate, as can be inferred from Fig. 18, there is a gap between the DG-FET and the conventional MIS-FET. Since no difference is observed, the relationship between the drain current Ids and the source-gate voltage Vgs is not shown.
• the pull-down transistor 33 and the pull-up transistor 34 are constituted by MIS-FETs having single or multilayer gate electrodes.
• the gate electrode portion on or above the gate insulating film of the pull-down transistor 33 is ion-implanted at a high dose such that a depletion layer does not occur even when the gate-source voltage increases.
• ion implantation of phosphorus (P) is performed under the condition that the dose amount is 15 E 1 / cm 2 or more.
• the first gate electrode portion or the low concentration electrode above the gate insulating film when a voltage between the gate and the source is applied in a direction in which the transistor turns on, low dose enough to depletion according to an increase in the absolute value occurs in the voltage (e.g., perform re down implanted at 1 E 1 4 / cm 2) is Ion implanted at.
• a bull-up transistor and a blue-down transistor both have a two-layer gate electrode composed of a first electrode part and a second electrode part (another layer is interposed between the first electrode part and the second electrode part).
• the first electrode of the pull-up transistor may be a low-concentration electrode
• the second electrode above the pull-down transistor 33 and the pull-up transistor 34 may be connected between the gate and the source.
• High conductivity such as polysilicon part, which is ion-implanted at a high dose that does not generate a depletion layer even if the voltage increases, high melting point metal part, high melting point silicide part such as titanium silicide or tungsten silicide. Electrode part.
• Fig. 23 shows the input / output transfer characteristics of a conventional inverter with a built-in DG-FET manufactured by the manufacturing method according to the present invention, and the solid lines (a) and (mouth) show the former.
• the dashed lines (2) and (c) show the input-output transfer characteristics of the inverter.
• NM H the high-side margin
• NM L the low-side margin
• the inverter according to the present invention has an input / output transfer characteristic approximately equal to that of the inverter with the value of 2, and the conventional inverter with the value of ⁇ , of 4. ing. This can be achieved by forming an inverter using the DG-F ⁇ ⁇ of the present invention. This means that the chip size can be reduced compared to the case of the inverter.
• the inverter according to the present invention has substantially the same high side margin (NM H ) as compared to the conventional inverter, but has the same low side margin (NM L :). , it can be seen e this being 0. 2 ⁇ 0. 2 5 V increases, the I Nhata according to the present invention, which means that it is ensured a more stable operation. Therefore, by using the inverter according to the present invention for a logic circuit such as an AND circuit or a 0R circuit, it is possible to configure a mouthpiece circuit capable of sufficiently securing a noise margin even with a low-voltage power supply. it can.
• FIG. 24 is an equivalent circuit diagram of a high resistance load type SRAM cell.
• S5 is a bit line
• 36 is an anti-bit line
• 37 and 38 are transfer transistors (pull-up transistors)
• 39 and 40 are drive transistors (buld-down transistors)
• 4 1 and 42 are high-resistance polysilicon
• 43. and 44 are storage nodes
• 45 is a ground line
• the sources of the driving transistors 39 and 40 are connected to ground Vss and high One end of each of the resistance polysilicons 41 and 42 is connected to the power supply Vdd.
• the transfer transistors 37 and 38 gate the low-concentration electrode part, that is, the electrode part that is doped with impurities at such a low concentration that an air gap layer is generated as the absolute value of the gate-source voltage increases. It has a gate electrode provided on or above the insulating film. That is, this transfer transistor is manufactured by any of the above-described methods of manufacturing a DG-FET according to the present invention.
• the driving transistors 39 and 40 do not have a low-concentration electrode portion, and the gate electrode has a high concentration of impurities to such an extent that a gap layer does not occur even if the gate-source voltage increases.
• the gate electrode is composed only of a doped polysilicon portion, a high melting point metal portion, or a high melting point silicide portion such as titanium silicide or tungsten silicide.
• the noise cell evaluation method for the memory cell can be shown by the evaluation diagram shown in FIG. 25 since the configuration of the driving transistor and the transfer transistor is the same as that of the inverter in FIG. That is, the input voltage V1 is plotted on the X axis and the output voltage V2 is plotted on the Y axis, and at the same time, the input voltage V1 is plotted on the Y axis and the output voltage V2 is plotted on the X axis. Can be.
• FIGS. 26 and 27 are evaluated in the same manner as the inverter pull-down transistor and bull-up transistor noise margin in FIGS. 26 and 27.
• the thermal oxide film layer 1 4 shows only an example in which the gate insulating film 16 is formed by self-aligning etching, but the anisotropic etching is performed to leave the thermal oxide film layer 14 partially or wholly, thereby leaving the electrode portion or the laminate. It is clear that may be formed.
• the MIS-FET having the LDD structure is often described as the embodiment, and it is apparent that the MIS-FET having the DDD (Double Diffused Drain) structure can be applied.
• DDD Double Diffused Drain
• two types of impurities having different diffusion coefficients can be easily formed by ion implantation at different concentrations.
• the gate electrode portion having a low impurity concentration may be formed by depositing a polysilicon layer doped with a low concentration of impurities.
• This manufacturing method is an extremely effective manufacturing method that can adjust the impurity concentration to manufacture MIS-FET with different transistor characteristics even if the chip size is the same on the same semiconductor substrate.
• the circuit stability can be improved without increasing the chip size of a semiconductor device formed in a logic circuit, an SRAM circuit, or the like having an inverter configuration, and without increasing the thickness of a gate oxide film.
• the MIS-FET manufactured by the manufacturing method realized by the present invention has an advantage that the threshold voltage Vt is not increased. Therefore, the threshold voltage Vt of the pull-up transistor and the threshold voltage Vt of the inverter transistor of the inverter are the same, and MIS-FET having different characteristics can be provided. In addition, there is an advantage that good characteristics can be maintained even during low-voltage dynamic pressure operation.
• the conductivity of the gate electrode can be increased as a whole. Therefore, it has the advantage of contributing to the improvement of the switching characteristics of the MIS-FET and enabling high-speed operation.
• the impurity diffusion prevention layer is formed between the first electrode portion and the second electrode portion so that the conductivity of each gate electrode is made different. Therefore, it has the effect of maintaining and stabilizing the characteristics of the DG-FET. Also, according to the present invention, the characteristics can be changed without changing the thickness of the gate oxide film, so that the manufacturing process can be simplified and the single gate electrode having the LDD structure can be used.
• the ion implantation of the SZD diffusion layer and the ion implantation of the upper gate electrode portion functioning as a mask can be simultaneously formed, thereby simplifying the manufacturing process. it can.
• a low-concentration electrode portion is provided on or above the gate insulating film, a low-impurity-concentration ion implantation step for forming an LDD structure and a low-concentration electrode portion polysilicon portion are formed. Since the ion implantation process can be performed simultaneously, the manufacturing process can be simplified.
• 1 (a) to 1 (c) are cross-sectional views showing one embodiment of a method for manufacturing a MIS field-effect transistor according to the present invention.
• FIGS. 2A to 2E are cross-sectional views showing another embodiment of the method of manufacturing the MIS field-effect semiconductor device according to the present invention.
• 3A to 3C are cross-sectional views showing another embodiment of the method for manufacturing the MIS field-effect semiconductor device according to the present invention.
• FIGS. 4A to 4E are cross-sectional views showing another embodiment of the method of manufacturing the MIS field-effect semiconductor device according to the present invention.
• 5 (a) to 5 (c) are cross-sectional views showing another embodiment of the method for manufacturing a MIS field-effect semiconductor device according to the present invention.
• FIGS. 6A to 6E are cross-sectional views showing another embodiment of the method for manufacturing the MIS field-effect semiconductor device according to the present invention.
• FIG. 7A to 7C show a method of manufacturing the MIS field-effect semiconductor device according to the present invention. It is sectional drawing which shows the other Example of a method.
• FIGS. 8A to 8E are cross-sectional views showing another embodiment of the method of manufacturing the MIS field-effect semiconductor device according to the present invention.
• 9 (a) to 9 (c) are cross-sectional views showing another embodiment of the method of manufacturing the MIS field-effect semiconductor device according to the present invention.
• 10 (a) to 10 (e) are cross-sectional views showing another embodiment of the method for manufacturing the MIS field-effect semiconductor device according to the present invention.
• 11 (a) to 11 (c) are cross-sectional views showing another embodiment of the method for manufacturing the MIS field-effect semiconductor device according to the present invention.
• 12 (a) to 12 (e) are cross-sectional views showing another embodiment of the method for manufacturing the MIS field-effect semiconductor device according to the present invention.
• FIGS. 13A to 13C are cross-sectional views showing another embodiment of the method for manufacturing the MIS field-effect semiconductor device according to the present invention.
• 14 (a) to 14 (e) are cross-sectional views showing another embodiment of the method for manufacturing the MIS field-effect semiconductor device according to the present invention.
• FIGS. 15A to 15C are cross-sectional views showing another embodiment of the method for manufacturing the MIS field-effect semiconductor device according to the present invention.
• FIGS. 16A to 16D are diagrams for explaining the operation of the MIS field-effect semiconductor device of the present invention.
• FIG. 17 is a diagram showing drain current-gate voltage characteristics of the present invention and a conventional MIS field-effect semiconductor device.
• FIG. 18 is a diagram showing the drain current-gate voltage characteristics of the present invention and the conventional MS field effect semiconductor device.
• FIGS. 19 (a) to 19 (d) are diagrams for explaining the operation of the MIS field-effect semiconductor device of the present invention.
• FIG. 20 is a diagram showing drain current-gate voltage characteristics of the present invention and a conventional MIS field-effect semiconductor device.
• 21 (a) to 21 (e) are cross-sectional views showing a method for manufacturing a conventional MIS field-effect semiconductor device.
• FIG. 22 is a circuit diagram showing an inverter surface.
• FIG. 23 is a diagram showing the input / output transfer characteristics of an inverter using the present invention and a conventional MIS field-effect semiconductor device.
• FIG. 24 is a circuit diagram showing a 24 S RAM image path.
• Figure 25 is an evaluation diagram of the 5-inverter configuration.
• FIG. 26 is an evaluation diagram of a margin of the present invention and a conventional SRAM.
• FIG. 27 is an evaluation diagram of the present invention and a conventional SRAM margin.

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• 1994
  • 1994-05-06 JP JP6094266A patent/JPH07176732A/ja not_active Withdrawn
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