WO1995007493A1 - Dispositif d'affichage et procede de pilotage associe - Google Patents
Dispositif d'affichage et procede de pilotage associe Download PDFInfo
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- WO1995007493A1 WO1995007493A1 PCT/JP1994/001502 JP9401502W WO9507493A1 WO 1995007493 A1 WO1995007493 A1 WO 1995007493A1 JP 9401502 W JP9401502 W JP 9401502W WO 9507493 A1 WO9507493 A1 WO 9507493A1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0202—Addressing of scan or signal lines
- G09G2310/0205—Simultaneous scanning of several lines in flat panels
- G09G2310/021—Double addressing, i.e. scanning two or more lines, e.g. lines 2 and 3; 4 and 5, at a time in a first field, followed by scanning two or more lines in another combination, e.g. lines 1 and 2; 3 and 4, in a second field
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0224—Details of interlacing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0232—Special driving of display border areas
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0283—Arrangement of drivers for different directions of scanning
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0464—Positioning
- G09G2340/0471—Vertical positioning
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0464—Positioning
- G09G2340/0478—Horizontal positioning
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0464—Positioning
- G09G2340/0485—Centering horizontally or vertically
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2011—Display of intermediate tones by amplitude modulation
Definitions
- the present invention relates to a display device such as a liquid crystal display device in which a plurality of display pixels are arranged in a matrix, and a driving method thereof.
- Liquid crystal display devices are used in a variety of fields, such as televisions, displays for combi- ters, and electronic notebooks. Liquid crystal display devices are particularly lightweight and thin. Attention is focused on the features of low power consumption.
- a liquid crystal projector separates white light from a light source into three primary colors, red, green, and blue, using a dichroic mirror.
- the light of these color components is made to enter three independent liquid crystal display devices, respectively, and the red, green, and blue images are displayed on the liquid crystal display devices.
- the displayed image is optically recombined and projected onto a transmissive or reflective screen to produce a color display.
- liquid crystal display devices for liquid crystal projectors
- the incident optical system and the projection optical system be miniaturized in order not to increase in size.
- the display image of the liquid crystal display device is enlarged and projected on a screen, not only the display device can be reduced in size, but also the pitch of the display pixels can be reduced. You also need to kill.
- a display panel composed of a plurality of display pixels and a drive circuit for driving the display pixels are integrally formed on a substrate. Attempts have been made to eliminate the inconvenience of forming and connecting the display cell and the drive circuit section.
- the driving circuit of the above-described display device mainly includes a shift register row connected to a plurality of shift register power rows S. Be configured.
- S. Be configured.
- the shift register array is a form in which signals are sequentially transferred through these shift registers, a disconnection or disconnection occurs. If a defect such as a short circuit is present in a part of the shift register array, all downstream shift registers will malfunction.
- Japanese Patent Application Laid-Open No. 62-271569 / 1988 replaces a drive circuit section mainly composed of a shift register. And a pair of decodes that output pulses sequentially based on the binary count value obtained by counting clock noise and its inverted output. Disclosed is the use of a drive circuit composed of a D as a drive circuit of a display device.
- the drive circuit section mainly with the decoder By configuring the drive circuit section mainly with the decoder in this way, even if there is a defect such as a disconnection or a short circuit in the middle of wiring, it can respond to defective points. Since only output is not obtained, sufficient reliability can be ensured, for example, by providing a pair of decoders redundantly in the drive circuit. It will be possible.
- the power of Shina and the power of Shina are disclosed in Japanese Patent Application Laid-Open No. 62-271715.
- the decoder since the decoder has a plurality of logic circuits each corresponding to one scanning line or one signal line, the display device is provided with a plurality of logic circuits. With the increase in definition, the number of logical circuits will increase significantly in addition to the number of wires for transmitting numerical signals, and conversely, the manufacturing yield will decrease. Furthermore, if each logic circuit section is arranged corresponding to one scanning line or one signal line, it is possible to sufficiently cope with the high-speed operation accompanying the high definition of the display device. It becomes difficult.
- the extra display panel that does not correspond to the effective scanning lines of the video signal.
- a method of scanning a horizontal pixel line during a vertical flyback period or the like to display a black blank In the above-described configuration, it is difficult to scan all of the remaining horizontal pixel lines in a very short time in such a configuration. However, reliable black display cannot be expected.
- the present invention has been made in view of the above-mentioned technical problems, and has as its object to provide a display device in which malfunctions are significantly reduced. You.
- Another purpose of the present invention is to provide the number of horizontal pixel lines of display cells and the number of effective scanning lines of video signals, or the number of display pixels constituting one horizontal pixel line.
- An object of the present invention is to provide a display device and a driving method capable of obtaining a good display image even when the number of video data and the number of video data of a video signal are different from each other. . Disclosure of the invention
- a display device includes a plurality of display devices arranged in a matrix.
- a display panel having a pixel electrode to be provided, a scan path for supplying a scan signal to the scan line, and n (n is a positive integer of 2 or more) in the scan circuit.
- a display device comprising: a bit input numerical signal; and a scanning control circuit for supplying an inverted input numerical signal of the input numerical signal.
- An input wiring group consisting of a plurality of input wirings to which the input numerical signal and the inverting input numerical signal are input for each bit; the input numerical signal and the inversion; Fewer than the number of scan lines for selectively inputting numerical input signals
- a plurality of logic circuits, and output distribution means for outputting at least two of the logic circuits corresponding to at least two of the scanning lines. ing.
- the display device of the present invention electrically connects a plurality of signal lines and a plurality of scanning lines, and the signal lines and the scanning lines, which are arranged in a matrix form.
- a display panel including a switch element to be connected and a pixel electrode connected to the switch element; and n (n is a positive integer of 2 or more) bits.
- a selection control circuit for generating an input numerical signal of the above and an input numerical signal inverted from the input numerical signal, and the input numerical signal and the inverted input numerical value from the selection control circuit
- a video signal input circuit based on a signal is selected at a predetermined timing, and the video signal is supplied to the signal line as video data. Then, the video signal supply circuit section includes the input numerical signal and the input numerical signal.
- An input wiring group consisting of a plurality of input wirings to which the inverted input numerical signal is input for each bit; A plurality of logic circuits less than the number of signal lines for selectively inputting the input numerical signal and the inverted input numerical signal, from the logic circuit; And at least two output lines which correspond to the above-mentioned signal lines.
- the driving method of the display device of the present invention is based on the video data of the video signal on the display panel formed by arranging a plurality of horizontal pixel lines composed of a plurality of display pixels.
- the number of effective scanning lines in the vertical scanning period of the video signal is more than the number of horizontal pixel lines corresponding to the number of effective scanning lines.
- at least one of the horizontal pixel lines which does not correspond to the effective scanning line of the video signal has non-display data included in the first vertical scanning period.
- the non-display data is displayed on the other horizontal pixel lines that do not correspond to the effective scanning lines of the video signal, and is displayed on the other horizontal pixel lines.
- the driving method of the display device is such that a display panel comprising a plurality of horizontal pixel lines composed of a plurality of display pixels is arranged on a display panel.
- the number of video data in one horizontal scanning period of the video signal is equal to the number of display pixels in the horizontal pixel line. If the display data is not enough, at least one non-display data that does not correspond to the video data is displayed on the display pixel during the first period, and the video data is displayed on the display pixel.
- the display device is characterized in that non-display data is displayed in a non-corresponding other display pixel in a second period different from the first period.
- the supply circuit section is composed of a logical circuit section that has fewer scanning lines or fewer signal lines than the number of scanning lines or signal lines that are selectively output based on the input numerical signal from the selection control circuit section.
- the number of horizontal pixel lines of the display panel and the number of effective scanning lines of the video signal, or one horizontal pixel line can be reduced. Even if the number of display pixels and the number of video data of the video signal are different, for example, at least one horizontal line that does not correspond to the effective scanning line of the video signal.
- the non-display data is displayed on the pixel line in the first period, and the non-display data is displayed on other horizontal pixel lines that do not correspond to the effective scanning line of the video signal during the first period.
- the non-display data is displayed in at least one display pixel that does not correspond to the video data that is different from the second period or that does not correspond to the video data.
- Non-display data is applied to other display pixels that do not correspond to the data for the first period. Do that the second phase between'm in and the child that are shown in Table by Li, it is in the non-display area that Do not possible to display the hidden data.
- FIG. 1 is a diagram schematically showing a configuration of a liquid crystal projector according to one embodiment of the present invention.
- FIG. 2 is a diagram schematically showing the configuration of the liquid crystal display device shown in FIG.
- FIG. 3 is a diagram schematically showing the configuration of the scanning line drive circuit shown in FIG.
- FIG. 4 is a diagram schematically showing the configuration of the video signal line driving circuit shown in FIG.
- FIG. 5 is a diagram showing one driving waveform of the scanning line driving circuit shown in FIG.
- FIG. 6 is a diagram showing another driving waveform of the scanning line driving circuit shown in FIG.
- FIG. 7 is a diagram showing another driving waveform of the scanning line driving circuit shown in FIG.
- FIG. 8 is a diagram showing one driving waveform of the video signal line driving circuit shown in FIG.
- FIG. 9 is a diagram showing an example of an image displayed by the liquid crystal projector shown in FIG.
- FIG. 10 is a diagram showing a voltage-light transmittance characteristic showing a relationship between a voltage between a pixel electrode and a common electrode of the liquid crystal display device shown in FIG. 1 and a transmittance.
- BEST MODE FOR CARRYING OUT THE INVENTION a liquid crystal projector according to an embodiment of the present invention will be described with reference to the drawings.
- Fig. 1 schematically shows the configuration of this liquid crystal projector: L-Cutter 1.
- This liquid crystal projector 1 has a light source 2.
- a reflecting mirror 3 that reflects the light source light emitted to the back of the light source 2 and a light source light source 2 from the light source 2.
- the first dichroic mirror that reflects only the red component R contained in the source light that has passed through the light source optical lens 5 and transmits the blue components G and B
- the first reflection mirror that guides the red component R reflected in 7 to the liquid crystal display device 101 for displaying red. 11. Reflects only the green component G from the transmitted light that has passed through the first and first dike ⁇ -tickler — 7 and leads to the liquid crystal display device 501 for green display.
- the second dichroic mirror 9 which transmits the blue component ⁇ to the liquid crystal display device 601 for blue display, transmits the liquid component to the image transmitted through the liquid crystal display device 101.
- the third dike mirror 13 for synthesizing the image transmitted through the liquid crystal display device 501 and the liquid crystal display on the image transmitted through the liquid crystal display device 101 It circulates through a second reflection mirror 15 and a fourth dichroic mirror 17 for synthesizing an image transmitted through the device 601.
- the image synthesized in this way is condensed by the condensing lens 19, passes through the opening of the second aperture mask 21 and then is projected by the projection lens. It is projected onto the screen 4 1 by 3 1.
- FIG. 2 schematically shows the configuration of the liquid crystal display device 101 shown in FIG. Since the other liquid crystal display devices 501 and 601 have substantially the same structure as the liquid crystal display device 101, the description thereof will be omitted.
- the liquid crystal display device 101 is a pair of electrode substrates 1 1 1 and 1 9 1 And a polymer-dispersed nematic liquid crystal layer 103 held between them.
- the liquid crystal layer 103 is composed of a polymer resin material and a nematic liquid crystal having a positive dielectric anisotropy dispersed in the polymer resin material. .
- One electrode substrate 111 is a pair of redundant scanning line driving circuits 200 disposed on the left and right sides of the liquid crystal layer 103 on the transparent insulating substrate of Ishihide. 1a and 201b, and a redundant set of video signal line drive circuits 3101a and 3101, which are disposed above and below the liquid crystal layer 103, respectively.
- the gate line s is connected to the scanning line 161, and the thin film transistor is formed of a polycrystalline silicon in which a drain is electrically connected to the video signal line 163.
- a transistor (hereinafter abbreviated as TFT) 165 composed of IT ⁇ (Indium-Tin-Oxide) electrically connected to the source of this TFT 165
- IT ⁇ Indium-Tin-Oxide
- the other electrode substrate 191 is configured such that a common electrode 195 made of IT0 is arranged on a transparent insulating substrate.
- Each of the liquid crystal display devices 101, 501 and 601 is a polymer dispersion held between the pixel electrode 167 and the common electrode 195.
- the scanning line drive circuit 201a includes a numerical signal conversion circuit section 21 la, a scan selection circuit section 21a connected to the numerical signal conversion circuit section 21a, and a scan selection circuit section.
- the output control circuit section 2411a connected to the noise amplifier 2311a connected to the 2211a and the noise amplifier 2311a connected to the It is composed of
- the numerical signal conversion circuit section 211a includes 10 non-inverting signal lines for supplying 10-bit digital numerical signals SA1 to SA10, and these digital signals.
- Digital numerical signal SA 1 Digital digital signal SA 1 1, which is an inverted version of SA 10, which supplies SA 20 — 20 numerical values composed of 10 inverted signal lines
- the 10-bit non-inverting signal line and the inverting signal line are A different combination is selected for each of the wiring sections 2 13 a.
- a first stage Li click scan wiring section 2 1 3 a, a first 0 bit (2 9) non-inverted signal line, the non-inverting of the ninth bit (2 8) signal line, the eighth bit (2 7) non-inverted signal line, 7th-bit (2 6) non-inverted signal line, 6th-bit (2 5) non-inverted signal line, 5th bit (2 4) non-inverted signal line, 4th-bit (2 3) non-inverted signal line, a third bit (2 2) non-inverted signal line, a second bit ( Two non-inverted signal lines and the inverted signal line of the first bit (2.) are selected, and in the matrix wiring section 213a of the second stage, the 10th bit is selected.
- the logic circuits in each stage consist of four 3-input NOR gates — N 0 1 — N 0 4 and two 2-input NAND gates NA 1 and NA 2, 1 And a two-input NOR gate N05.
- the output terminals of the NOR gates NO 1 and N 02 are connected to the first and second input terminals of the NAND gate NA 1, respectively.
- the output terminals of NOR 'gates NO3 and N04 are NAND, and the output terminals of gate NA2 are the first and second input terminals, respectively. Connected.
- the output terminals of the NAND gates NA1 and NA2 are connected to the first and second input terminals of the NOR gate N05, respectively.
- the output signal of the NOR gate N05 of each logic circuit section 21a is led to the scan selection circuit section 22a.
- the output signal of the NOR gate N ⁇ 5 of each logic circuit 2 15 a is divided into three, and the output signal is divided into first and second signals, respectively.
- the third two-input NAND gate NA 3 Supplied to the first input terminal of NA5.
- the second input terminals of these NAND gates NA 3 -NA 5 are connected to three scan select lines A, B, and C, respectively.
- the output terminal of the first NAND gate NA 3 is connected to the two input nodes provided in common with the NAND gate ⁇ 5 for the logic circuit section 2 15 a in the preceding stage. Connected to the second input terminal of gate N06.
- the output terminal of the second NAND gate NA4 is connected to the first input terminal of the two-input NOR gate NO7.
- the second input terminal of the NOR gate NO 7 is connected to the power supply terminal set to the ⁇ N level.
- the output terminal of the third NAND gate NA 5 is connected to the other NAND gate NA 3 commonly used for the NAND gate NA 3 for the subsequent logic circuit section 21 a. Connected to the 1st input terminal of input NOR gate N ⁇ 6.
- the output signals of the NOR gates N06 and N07 are led to the output control circuit section 2411a via the buffer amplifiers 2311a, respectively. It is.
- These output control circuit sections 241a are connected to output control signals VG0 and VG1 supplied via output control signal lines G0 and G1, respectively. It is controlled by Output control signal VG 1 Is a signal obtained by inverting the output control signal VG0, and the output control circuit 241a performs a knock-off operation based on the output control signals VG0 and VG1. Determine the force that connects the amplifier 2 3 1 a to the scan line 16 1.
- the operation of one of the scanning line driving circuits 201a is defective, the electrical connection between the scanning line driving circuit 201a and the scanning line 161 is interrupted. That is, the other scanning line driving circuit 201b can be operated without the undesirable influence of the scanning line driving circuit 201a.
- the scanning line driving circuit 201a forms one set of two scanning lines suitable for displaying the video signal VS for television broadcasting, etc., and includes an odd field period and an even field.
- Figure 4 shows the case where two lines are driven at the same time by selecting and scanning so that the combination of the scanning lines selected at the same time differs between the field periods. Refer to and explain.
- the numerical signal line 2 1 2a has ⁇ 0 0 0 0 0 0 0 0 0 0 1 ⁇ , every two horizontal scanning periods from the counter circuit.
- a digital numerical signal S ⁇ 1 — SA 10 0 outputs ⁇ 0 0 0 0 0 0 0 output from the counter circuit 0 0 when 1 ⁇ 2 9 signal line, 2 8 signal line, 2 7 signal line, 2 6 signal line, 2 5 signal line, 2 4 signal line, 2 3 signal line, 2 2 signal line, 2 the each of the first signal line contact good beauty 2 ° inversion signal line ⁇ 0 ⁇ force or 2 9 inverted signal line, 2 8 anti Utateshin line, 2 7 inverted signal line, 2 6 inverted signal line, 2 5 inverted signal line, 2 4 inverted signal line, 2 3 inverted signal line, 2 2 inverted signal line, the each of the 2 1 inverted signal line contact good beauty 2 ° signal line ⁇ 1 ⁇ pixel-resolution Re applied is It is.
- the numerical signal line 2 1 2 a Urn Chi 2 9 signal line, 2 8 signal line, 2 7 signal line, 2 6 signal line, 2 5 signal line, 2 4 signal line, 2 3 signal line, 2 2 signal line, 2 0 signal is applied ⁇ 0 ⁇ each the lines of your good beauty 2 1 inverted signal line, 2 9 inverted signal line, 2 B anti Utateshin line, 2 7 inverted signal line, 2 6 inverted signal line, 2 5 inverted signal line, 2 4 inverted signal line, 2 3 inverted signal line, 2 2 inverted signal line, 2 ° each to the inverted signal line contact good beauty 2 1 signal line is ⁇ 1 ⁇ Ru is applied. Therefore, in response to the input of the digital numerical signal ⁇ 0 0 0 0 0 0 0 0 1 0 ⁇ , the numerical signal conversion circuit is used. Only the output S2
- the 1st select line A takes the 0N level in the first field period and the 2nd field in the second field. Is a selection signal VA having a level of 0 FF.
- the second scanning selection line B has a constant selection signal VB having a 0N level, and the third scanning selection line C has a selection signal VA inverse to the selection signal VA.
- Phase selection signal VC is applied.
- the output S from the numerical signal conversion circuit section 211a and the selection signals VA, VB, and VC of the respective scanning selection lines A, B, and C depend on the output signal S.
- the scanning signal VY j is output to two adjacent scanning lines 1661 during each horizontal scanning period as shown in FIG. . Then, the first field period and the second field period are selected at the same time. The combination of the two scanning lines 161 is different. I'm sorry.
- the odd-numbered scanning lines are applied to the odd-numbered field period by the scanning-line driving circuit 201a so as to be suitable for displaying the video signal VS of a television broadcast or the like.
- the scanning-line driving circuit 201a a description will be given of an interlaced drive in which even-numbered scanning lines are selectively scanned one by one during the field period.
- the selection signal VA that takes the ⁇ N level during one field period and takes the 0FF level during the second field period
- a selection signal VC having a fixed level of 0FF is impressed on the selection signal VB of the opposite phase to the selection signal VA and the third scanning selection line C.
- scanning is performed by the output from the numerical signal conversion circuit section 2] 1a and the selection signals VA, VB, and VC of the scanning selection lines A, B, and C.
- the scanning signal VY j is output for each scanning line during each horizontal scanning period. Then, the selected scanning line 161 is different between the first field period and the second field period.
- all the scanning lines are sequentially selected and scanned in each vertical scanning period by the scanning line driving circuit 211a so as to be suitable for displaying a video signal VS such as a computer signal.
- a video signal VS such as a computer signal.
- the first scanning selection line A has a selection signal VA power s with one cycle as a 1Z2 horizontal scanning period
- the second scanning selection line B has a selection signal VA.
- the selection signal VB having a phase opposite to that of the signal VA, and the selection signal V having a constant 0FF level is applied to the third scanning selection line C. C is being applied.
- a scanning signal VYj for sequentially selecting and scanning two scanning lines during one horizontal scanning period is output from the scanning lines 161 and 261.
- two-line simultaneous drive, interlace drive, and sequential scan drive can be selected.
- the video signal line driving circuit 301a of the liquid crystal display device 101 will be described with reference to FIG.
- the description of the video signal line driving circuit 301b will be omitted. Is omitted.
- This video signal line drive circuit 301a is a numerical signal conversion circuit section 311a composed of a matrix wiring section 313a and a logic circuit section 315a, and a numerical signal conversion section.
- Output control circuit 3 3 1a connected to the circuit 3 2 1a and the amplifier 3 2 1a connected to the circuit 3 3 1a ,
- the video signal selection circuit 3 4 1a connected to the output control circuit 3 3 1a, the storage capacitor 3 5 connected to the output of the video signal selection circuit 3 4 1a 1a.
- the numerical signal conversion circuit section 311a is composed of nine non-inverting signal lines and 9 non-inverting signal lines for supplying a 9-bit digital number signal DA1 to DA9. It consists of nine inverted signal lines that supply digital digital signals DA1 and D D9, which are inverted digital digital signals DA1 0 to D ⁇ 18. 18 Numerical signal lines 3 1 2a and a multi-stage logical circuit section 3 15 a including a set of 3 input NAND gates NA 1 1 N ⁇ 3 In each common bit, one of the non-inverting signal line and the inverting signal line, whichever is selected, is assigned to the corresponding logic circuit section 3 15 a 3 input NAND gate. NA 1 — Consists of a matrix wiring section 3 13 a connected to NA 3.
- the non-inverting signal line and the inverting signal line for 9 bits are selected by different combinations for each matrix wiring section 313a ⁇ .
- a first stage Li click scan wiring portion 3 1 3 a, 9 bits (2 8) of the inverted signal line, 8th-bit (2 7) of the inverted signal line, inversion signal line of the seventh bit (2 6), the sixth bit (2 5) of the inverted signal line, the inverted signal line of the fifth bit (2 4), fourth bit (2 3 inverted signal line), the third bit (2 2) of the inverted signal line, the second bit (2 1) inverted signal line, the non-inverted signal line of the first bit (2 °) is Selected.
- Each logic circuit section 3 15a has three 3-input NAND gates NA 1 and NA 3 and one 3-input NOR gate N ⁇ 1 Is configured.
- the output terminals of the NAND gates NA 1 — NA 3 are connected to the first, second, and third input terminals of one 3 ⁇ power NOR gate NOI, respectively. It is.
- NOR circuit of each logic circuit section 3 15a-The output signal of NO1 is guided to the output control circuit section 331a via the noise amplifier 321a. .
- the output signal of the NOR gate N01 of each logic circuit section 31a is divided into eight, and eight 2 inputs are provided.
- the first input terminal of the power NOR gate N02 is supplied via a NOFFAMP 3333a, respectively.
- the output control line G2 is connected to the second input terminal of these NOR gates N02.
- the output signal of the NOR gate NO 2 is guided to the video signal selection circuit section 34 1 a as the output signal of the output control circuit section 331 a, and the video signal selection section
- the signals are input to the gates of the eight analog switches 343a provided for selecting the video data in the circuit section 341a.
- the drains of these analog switches 34 3 a are connected to eight video signal input lines 34 45 a, respectively, and the output control circuit 33 1 During the ON period of each output S from a, the analog switches 343 3a sample video signals VS1, ..., VS8 from the source of a. It is a mechanism to be output.
- Each of the video data VD sampled by the video signal selection circuit section 34 1 a is corresponding to the corresponding video signal line via the storage capacitor section 3 51 a that holds the video data VD. Supplied to 16 3.
- a 9-bit digital numeric signal DA 1 _DA 9 is a timing for selecting and outputting video data VD to the video signal line 16 3 corresponding to each display pixel.
- the counter is provided by a counter circuit or the like (not shown). Therefore, they are sequentially added. And have you in each Timing of, No. de I di data Le numerical signal DA 1 - DA 9 numeric signal line 3 1 2 2 8 signal lines of Chi sales of a, 2 7 signal line, 2 6 Shin Line , 2 5 signal line, 2 4 signal line, 2 3 signal line, 2 2 signal line, 2 1 signal line, 2.
- a digital signal numerical signal DA 1 — DA 9 and an inverted signal DA 10 — DA 18 are shown in FIG. such have inverting output circuit or et numerical signal lines 3 1 2 a Urn Chi 2 9 inverted signal line, 2 8 inverted signal line, 2 7 inverted signal line, 2 6 inverted signal line, 2 5 inverted signal line, 2 4 inverted signal line, 2 3 inverted signal line, 2 2 inverted signal line, 2 1 inverted signal line, Ru is 2 ° out inversion signal line force.
- mosquitoes c te circuit power at the time of al de I di data Le numerical signal DA 1 one DA 9 force s ⁇ 0 0 0 0 0 0 0 1 ⁇ is 2 8 signal line, 2 7 signal line, 2 6 signal line, 2 5 signal line, 2 4 signal line, 2 3 signal line, 2 2 signal line, 2 1 signal line, is your good beauty 2 ° inversion signal line is ⁇ 0 ⁇ , was or 2 9 inverted signal line, 2 8 inverted signal line, 2 7-inverted signal line, 2 6 inverted signal line, 2 5 inverted signal line, 2 4 inverted signal line, 2 3 inverted signal line, 2 2 inverted signal line, 2 ⁇ 1 ⁇ is applied to the 1 inverted signal line and the 2 ° signal line, respectively.
- the input of the digital numerical signal DA 1 -DA 9 s ⁇ 0 0 0 0 0 0 0 0 1 ⁇ is as shown in FIG.
- the output S 1 is obtained from the first stage of the output control circuit 3331a.
- video signals VS1,..., VS8 as shown in FIG. 3 (c) are input to the eight video data lines 345a. Accordingly, while the output S1 from the first stage and the first stage of the output control circuit unit 331a is in the 0N period, the first to eighth video data selecting analogs are selected. The log switch 343a is selected at the same time, and the respective video data VD1,..., VD8 appear on the first to eighth video signal lines 163. It is forced.
- the analog for selecting the ninth to sixteenth video data is provided.
- the switch 343a is selected at the same time, and the respective video data VI] 9,..., VD16 are output to the ninth to sixteenth video signal lines 163. It is done.
- the video data VD 1,..., VD 184 are output to 184 video signal lines 163 for each horizontal scanning period.
- the video data VD output to the video signal line 16 3 via the TFT 16 5 through the pixel electrode 6 1 Then, the potential difference between the pixel electrode 167 and the common electrode 195 is retained for the period until the next scan line 161 is selected, and the display is displayed. It is done.
- the number of effective scanning lines of the video signal VS and the image are more than the number of horizontal pixel lines of the liquid crystal display device 101 or the number of display pixels constituting one horizontal pixel line.
- the number of data VD is small.
- the number of effective video data VD of the video signal VS is one. A description will be given of the case where eight lines are displayed.
- Non-display areas 90 1 and 90 3 each consisting of 140 horizontal lines and 127 horizontal pixel lines are provided, and 408 each on the left and right
- a non-display area 9705 and 907 consisting of display pixels of the same type are provided, and the display area 700 is formed at a substantially central portion of the display screen by, for example, the sequential driving shown in FIG. Explains how to set up and display.
- the scanning line driving circuit 201a shown in FIG. 2 has a ⁇ 0 0 0 1 0 0 1 1 1 ⁇ force, etc. during a vertical scanning period during the first field period. 0 1 1 1 1 0 0 0 1 1 0 ⁇ based on the 10-bit digital numerical signal SA 1 —SA 10 based on the R 0 M force that increases in order.
- 1 4 1st to 908th pixel lines are selected sequentially, and the first vertical retrace period during the first field period In between, the ⁇ 0 0 0 0 0 0 0 0 1 ⁇ power and the ⁇ 0 0 0 0 1 1 1 0 ⁇ power of the 10-bit digital numerical signal from the ROM Based on SA 1 -SA 10, the first to 28 th horizontal pixel lines are sequentially scanned as the first block 70 1, and the fifth fifth line thereafter.
- R 0 increases sequentially from ⁇ 0 0 0 0 1 1 1 0 0 1 ⁇ to ⁇ 0 0 0 1 0 0 0 1 1 0 ⁇
- the fifth block 705 based on the 130-bit digital numerical signal SA 1 -SA 10
- the horizontal pixel lines are scanned sequentially, and ⁇ 0 1 1 1 0 0 0 1 1 1 ⁇ to ⁇ 0 during the sixth vertical retrace period during the sixth field period 1 1 1 0 1 0 1 0 0 ⁇ in sequence [I R R ⁇ M force, based on the 10-bit digital numerical signal SA 1 — SA 10
- the 909th pixel and the 93rd horizontal pixel line are sequentially scanned, and the first pixel in the subsequent 10th field period is scanned.
- the 10th block 710 is the 1st block and the horizontal plane of the 1 035 Scans both lines sequentially.
- the video input line 345a of the video signal line drive circuit 301a displays the 409th to 14432th display during the horizontal scanning period.
- the non-display data VB and the non-display pixels corresponding to the 1st to 408th non-display pixels are provided together with the 104 video data VD corresponding to the pixel.
- a video signal including non-display data VB corresponding to the non-display pixel of the 1840th pixel is input.
- non-display data VB corresponding to the display pixel 1840 is input to the video input line 345a during each vertical flyback period of each field period. It is forced.
- non-display data VB is displayed on the 28th horizontal pixel line of the first color. This is sequentially repeated, and the non-display data VB is displayed in all of the non-display areas 901 and 903 divided into 10 blocks.
- the non-display data VB corresponding to the first to J-th non-display pixels corresponding to the first to J-eighth pixels, and the non-display pixels V143 to No. 1840 corresponding to the first to J-eighth non-display pixels Transferring the non-display data VB) within each horizontal retrace period may be difficult in time.
- the non-display data VB corresponding to the first to the 408th non-display pixels, the first non-display data VB Rather than displaying all of the non-display data VB corresponding to the non-display pixels of the 4th to the 1800th pixels in the same horizontal period, a plurality of non-display data VBs are not displayed. May be displayed separately for each block.
- the non-display data VB corresponding to the 1st to 80th non-display pixels during the direct scanning period during the 1st field period is applied to each horizontal blanking period.
- the non-display data VB corresponding to the 81st to 160th non-display pixels is transferred to each of them during the vertical scanning period during the second field period.
- the data is transferred and displayed within the horizontal flyback period, and thereafter, the non-operations of the first through the second through the first through the second vertical scanning periods during the first and the second field periods are performed.
- the non-display areas 901 and 903 may be formed by transferring the non-display data VB corresponding to the display pixels within each horizontal blanking period and displaying the same. .
- the non-display pixels corresponding to the non-display data in each water pixel column need not be equal to each other as described above, but are different from each other. It may be good.
- the 141st to 142nd horizontal pixel lines are 1st to 80th horizontal pixel lines.
- the non-display data VB is displayed on the non-display pixels of the first pixel and the pixels of the horizontal pixel line of the 144th pixel are output from the 81st pixel to the 144th pixel.
- the non-display data VB is displayed on the non-display pixels of No. 1 4 6, and the non-display data VB is displayed on the non-display pixels V 1 to H 4.
- the non-display area is divided into a plurality of blocks, such as displaying the non-display data VB on the non-display pixel of the 240th pixel from one input device.
- the non-display pixels for displaying the non-display data may be different for each pixel line. In this way, for example, the 144th power, the 144th water, etc.
- the non-display data V13 corresponding to the 80th non-display pixel from the first input to the 80th non-display pixel is the 141st to the 142nd.
- the non-display data corresponding to the 1st to 80th non-display pixels is removed from the storage capacitor section 351a and remains when the horizontal pixel line is displayed.
- non-display data VB is displayed in the 1st to 80th non-display pixels, and the 81st to 160th non-display pixels are displayed.
- the non-display data VB is displayed on the screen.
- the scanning line drive circuits 201a and 201b and the video signal drive circuit 301a and The display area 700 is easily placed in the approximate center of the display screen by controlling the number of digital knob signals input to 301b respectively. You can let them do it.
- the memory function of the storage capacitor section 351a is used well. Therefore, even if there are many non-display pixels in each horizontal pixel line, it is possible to form a non-display area without requiring special frame memory or the like. You.
- the 1st to 9th horizontal pixel lines are selected during the vertical vertical scanning period, and the 1st block is selected during the 1st vertical flyback period.
- the first horizontal pixel line, and the second block during the second vertical retrace interval as the second, second, second, second,.
- the 10th block is the 10th, 20th, 30th, etc. horizontal lines.
- the digital numerical signals SA 1 -SA 20 may be selected so that the pixel lines are sequentially selected.
- the non-display areas 901 and 903 are selected during the vertical flyback period compared to the above-described method. Because the horizontal pixel lines that make up the non-display areas 901 and 903 are evenly dispersed in the display screen, the non-display areas 901 and 903 are Even if the number of blocks to be divided increases, it is possible to realize a good display image without flicker or the like.
- the non-display areas 901 and 903 in the vertical scanning direction are divided into 10 blocks, and the non-display areas are hidden in 10 vertical retrace periods.
- Force s configured to write non-display data (VB) to each horizontal pixel line in areas 901 and 903, non-display area 901 at a time It goes without saying that all horizontal pixel lines composing 903 can be selected.
- VB non-display data
- non-display data (VB) is written in a horizontal pixel line.
- the effective scanning line of the video signal VS is larger than the number of horizontal pixel lines of the liquid crystal display device 101 or the number of display pixels constituting one horizontal pixel line.
- the display area 700 and the non-display areas 901, 903, 905, and 907 are respectively displayed.
- the enlargement ratio of the projection lens 31 of the liquid crystal projector 1 is set to the number of effective scanning lines or the effective image A configuration that automatically detects the number of reductions in the number of projector VDs and increases the enlargement ratio of the projection lens 31 of the liquid crystal projector 1 based on the detection result. In this way, even if the number of effective lines of the video signal VS or the number of effective video data VD fluctuates, a substantially constant size display is always displayed on the screen 41.
- An area 700 is configured.
- each scan corresponds to the input digital numerical signals SA1-SA20 and DAI-DA18.
- the line 161 and the analog switch 343a for selecting each image data are selected. Therefore, according to the liquid crystal display device 101 of this embodiment, the scanning line 161 and the analog switch 343a for selecting video data are sequentially selected as described above. Not only digital signals but also digital signals can be applied to digital signal lines 2 1 2 a and 3 1 2 a by digital signal SA 1 -SA 20 and DA 1-DA 18. It is possible to select the scanning line 161 and the analog switch 343a for selecting the video data.
- the liquid crystal projector 1 of this embodiment the case where the number of horizontal pixel lines is different from the number of effective scanning lines of the video signal VS is different. Even if the number of display pixels constituting one horizontal pixel line and the number of video data VD constituting one effective scanning line are different, A display area and a non-display area can be configured at arbitrary positions.
- the non-display area Multiple horizontal pixel lines Inspection is performed by dividing the data into vertical retrace periods, or by dividing the display pixels in the non-display area into a plurality of vertical scanning periods by the water and retrace periods.
- the present invention is limited to the force showing the example of arranging the display area substantially in the center of the display screen, as described above.
- the display area may be arranged at an arbitrary position by the control of the digital numerical signal SA 1-1 SA 10, DA 1-DA 9. Or multi-screens.
- the respective scanning lines 16 1 and 16 1 in any order may be used. It is also possible to select an analog switch 343a for selecting each video data.
- the liquid crystal projector 1 of this embodiment is configured by three substantially similar liquid crystal display devices 101, 501, and 601. As can be seen from FIG. 1, the number of inversions of the image transmitted through only the liquid crystal display device 501 is an odd number.
- the other liquid crystal display devices 101 and 601 are different in the order of selecting the analog switch 343a for selecting video data or the order of selecting the scanning lines 161. It must be different from the configuration.
- the digital numerical signal input to the liquid crystal display device 501 is output as a digital numerical signal which is sequentially subtracted.
- the counter circuit to be activated it is possible to use the three liquid crystal display devices 101, 501, and 601 common to the three panels. In such a case, the transmitted light is changed according to the pixel shape of each of the liquid crystal display devices 101, 501, and 601. Even if inverted, its shape is almost the same
- the display image can be inverted, and the display image from the liquid crystal projector 1 can be displayed.
- the display is made in the form of a transmission screen and the case where the display is made in the form of a reflection screen, depending on the force, counter, R ⁇ M, etc. Switching can be easily performed by setting the digital numerical signals SA 1-SA 10 and DAI-DA 9.
- the input numerical signals SA 1 -S A20 for operating the scanning line driving circuit 201 a are 10 bits, and the video signal line driving circuit 30 la is operated.
- the numerical value signal DAI-DA 18 is composed of 9 bits.
- the combination of connections in the matrix wiring section 213a Accordingly, the maximum number of scan lines 161 that can be controlled is 102.
- the scanning selection circuit unit 221a is provided between the matrix wiring unit 213a and each scanning line 161 in this embodiment.
- Various driving is enabled, and the control of the scanning line 161 of 103 can be performed without unnecessarily increasing the number of bits of the input numerical signal (SA1-SA20). It is possible.
- the scanning drive circuits 201a and 201b and the video signal line drive circuits 301a and 301b are integrally formed on the substrate 113. A place to eliminate the hassle of connecting by making Although it is shown, it is acceptable to use an external circuit using individual ICs.
- one of the scanning line driving circuits 201a and 201b and the video signal line driving circuits 301a and 301b in the liquid crystal display device 101 of the present embodiment, or One of the driving circuits 201a, 201b, 301a, and 301b may be constituted by a plurality of shift registers as in the conventional case, and the scanning line driving circuits 201 on both sides may be used.
- the connection form between the numerical signal line 211a in the matrix wiring part 213a and the logic circuit part 215a may be different between a and 201b.
- a polymer-dispersed liquid crystal which can greatly increase the light use efficiency because of the need for a polarizing plate or the like, is used.
- the above-described force is not limited to the above-mentioned force, and any conventionally known various liquid crystal materials can be used.
- each of the liquid crystal display devices 101, 501, and 601 is arranged between a pixel electrode and a common electrode such that liquid crystal molecules are twisted 90 ° between the electrodes.
- a nematic liquid crystal having a positive dielectric constant anisotropy is held through the film, and a polarizing plate is placed on the outer surface of the substrate such that the polarization axis is aligned with the orientation axis. It is good if they are arranged and configured.
- the transmittance becomes maximum when the potential difference between the pixel electrode and the common electrode is 0 V, and the potential difference becomes large.
- the so-called normally white mode liquid crystal display devices 101, 501, and 601 whose transmittance is reduced are constructed.
- the liquid crystal projector 1 in which the normally-white mode liquid crystal display devices 101, 501, and 601 configured as described above are used is used. Then, the non-display areas 90 1 and 90 3, 905, and 907 shown in FIG.
- the non-display data VB is written to the pixel, the potential difference between the pixel electrode and the common electrode obtained in the normal display state is outside the potential difference region 61 as shown in FIG.
- the non-display area 90 1 and 90 3, 9 05, 9 07 are divided into multiple blocks by selecting and using the drive voltage of the potential difference area 63 However, even when the display is completed in a plurality of periods, good black display can be ensured.
- a force is applied to a liquid crystal projector 1 composed of three liquid crystal display devices 101, 501, and 601, as an example.
- a liquid crystal projector 1 composed of three liquid crystal display devices 101, 501, and 601, as an example.
- it can be composed of a single liquid crystal display device, and it is also acceptable to adopt various methods for the optical system. It may be a direct-view type liquid crystal display device.
- a liquid crystal pixel is used as a display element, and a display element in which light transmittance or light reflectance changes in response to a force drive voltage that indicates a case where a liquid crystal pixel is used.
- the present invention can be effectively applied to a display device using an element capable of modulating light, such as a display element in which the amount of emitted light varies depending on the drive voltage.
- this embodiment uses a predetermined digital numerical signal that does not output any signal from the digital signal conversion circuit between the digital numerical signal trains, for example, all the bits. You may change it to introduce "0". This predetermined digital numerical signal can prevent the output pulses from being duplicated, so that the display device can be operated stably.
- the scanning circuit or the video signal supply circuit has a certain number of scanning lines selectively output based on the input numerical signal from the selection control circuit. Is the number of logical turns less than the number of signal lines Because it is composed of roads, the number of wirings for transmitting numerical signals and the number of roads for suppressing numerical signals can be reduced, even for high-definition displays. Manufacturing yield is good.
- the number of horizontal pixel lines of the display panel and the number of effective scanning lines of the video signal, or one horizontal pixel line are provided. Even if the number of display pixels and the number of video data of the video signal are different, for example, at least it does not correspond to the effective scanning line of the video signal.
- non-display data is displayed on the pixel line during the first period, and at the same time, non-display data is displayed on other horizontal pixel lines that do not correspond to the effective horizontal line of the video signal Display data in a second period different from the first period, or hide non-display data in at least one display pixel that does not correspond to video data in the first period Display and hide non-display data for other display elements that do not correspond to video data for the first period Ri by the and the child you table shows between different Do that second phase, the non-table display region that Do not possible to display the hidden data.
- the scanning circuit or the video signal supply circuit of the display device is constituted by a logic circuit which selectively outputs a signal based on a numerical signal input from the selection control circuit.
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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KR1019950701828A KR0175194B1 (ko) | 1993-09-09 | 1994-09-09 | 표시장치 및 그 구동방법 |
US08/432,165 US5801672A (en) | 1993-09-09 | 1994-09-09 | Display device and its driving method |
DE69429242T DE69429242T2 (de) | 1993-09-09 | 1994-09-09 | Anzeigevorrichtung |
EP94926385A EP0674207B1 (en) | 1993-09-09 | 1994-09-09 | Display device |
Applications Claiming Priority (8)
Application Number | Priority Date | Filing Date | Title |
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JP22431393 | 1993-09-09 | ||
JP5/224313 | 1993-09-09 | ||
JP22875893 | 1993-09-14 | ||
JP5/228747 | 1993-09-14 | ||
JP5/228758 | 1993-09-14 | ||
JP22874793 | 1993-09-14 | ||
JP6/17141 | 1994-02-14 | ||
JP1714194 | 1994-02-14 |
Publications (1)
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WO1995007493A1 true WO1995007493A1 (fr) | 1995-03-16 |
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PCT/JP1994/001502 WO1995007493A1 (fr) | 1993-09-09 | 1994-09-09 | Dispositif d'affichage et procede de pilotage associe |
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US (2) | US5801672A (ja) |
EP (1) | EP0674207B1 (ja) |
KR (1) | KR0175194B1 (ja) |
DE (1) | DE69429242T2 (ja) |
TW (1) | TW272275B (ja) |
WO (1) | WO1995007493A1 (ja) |
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JP3774704B2 (ja) * | 2003-03-04 | 2006-05-17 | キヤノン株式会社 | 画像信号処理装置及び画像表示装置並びにその方法 |
JP3774706B2 (ja) * | 2003-03-14 | 2006-05-17 | キヤノン株式会社 | 画像表示装置及び画像表示装置の変換回路の特性決定方法 |
KR20060065277A (ko) * | 2004-12-10 | 2006-06-14 | 삼성전자주식회사 | 디스플레이장치 및 그 제어방법 |
JP2010128014A (ja) * | 2008-11-25 | 2010-06-10 | Toshiba Mobile Display Co Ltd | 液晶表示装置 |
KR20180057101A (ko) * | 2016-11-21 | 2018-05-30 | 엘지디스플레이 주식회사 | 게이트 구동회로 및 이를 이용한 표시패널 |
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US5801672A (en) * | 1993-09-09 | 1998-09-01 | Kabushiki Kaisha Toshiba | Display device and its driving method |
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- 1994-09-09 US US08/432,165 patent/US5801672A/en not_active Expired - Fee Related
- 1994-09-09 WO PCT/JP1994/001502 patent/WO1995007493A1/ja active IP Right Grant
- 1994-09-09 EP EP94926385A patent/EP0674207B1/en not_active Expired - Lifetime
- 1994-09-09 KR KR1019950701828A patent/KR0175194B1/ko not_active IP Right Cessation
- 1994-09-09 DE DE69429242T patent/DE69429242T2/de not_active Expired - Fee Related
- 1994-09-26 TW TW083108916A patent/TW272275B/zh active
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1998
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JPS6026932A (ja) * | 1983-07-25 | 1985-02-09 | Canon Inc | 液晶表示装置 |
JPS62271569A (ja) * | 1986-05-20 | 1987-11-25 | Sanyo Electric Co Ltd | 画像表示装置の駆動回路 |
JPS63218927A (ja) * | 1987-03-06 | 1988-09-12 | Matsushita Electronics Corp | 画像表示装置 |
JPH04165329A (ja) * | 1990-10-30 | 1992-06-11 | Toshiba Corp | 液晶表示装置の駆動方法 |
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Cited By (3)
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---|---|---|---|---|
KR100440359B1 (ko) * | 1995-11-06 | 2004-10-14 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 능동매트릭스표시장치및스캐닝회로 |
JP2009025822A (ja) * | 1998-03-27 | 2009-02-05 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
JP2003044013A (ja) * | 2001-07-31 | 2003-02-14 | Toshiba Corp | 駆動回路、電極基板及び液晶表示装置 |
Also Published As
Publication number | Publication date |
---|---|
KR0175194B1 (ko) | 1999-03-20 |
US5801672A (en) | 1998-09-01 |
EP0674207A1 (en) | 1995-09-27 |
TW272275B (ja) | 1996-03-11 |
EP0674207A4 (en) | 1996-08-21 |
DE69429242T2 (de) | 2002-08-14 |
KR950704713A (ko) | 1995-11-20 |
EP0674207B1 (en) | 2001-11-28 |
DE69429242D1 (de) | 2002-01-10 |
US6107983A (en) | 2000-08-22 |
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