Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
  • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
  • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

Definitions

• the present invention relates to a method for producing a monocrystalline silicon layer which is separated from an underlying silicon substrate by a buried insulator layer.
• ZMR process Zone Melt Recrystallization
• SIMOX SIMOX
• MA Guerra The Status of SIMOX technology. DN Schmidt, editor, Silicon-on-Insulator Technology and Devices, vol. 90-6, pages 21 to 47. The Electrochemical Society, Inc., 1990.
• the third method which is counted among SOI technologies, is the afer bonding method. This is known from the following literature, among others: W. P. Maszara. Silicon-on-Insulator by Wafer Bonding: A review. J. Electrochem. Soc. , 138: 341-347, 1991.
• the most important advantage of this method is that the thickness of the silicon film is extremely uniform and can be set very precisely between about 50 nm and a few 10 ⁇ m by the choice of ion energy or by subsequent epitaxial growth of silicon.
• the main disadvantages of this method lie in the need for very high implantation doses as well as in the associated high costs and in the practical and physical limitation of the maximum oxide thickness to approximately 0.5 ⁇ m.
• the surface of a wafer can first be thermally oxidized or a dielectric layer can be deposited on the wafer.
• a second wafer is treated in the same way or else leave treated.
• the surfaces of the two wafers are brought into contact with one another after hydrophilization, whereupon the wafers which adhere easily to one another by hydrogen bonding are insolubly connected to one another in a subsequent tempering step.
• one of the two wafers is thinned from the original thickness, which is surely a few 100 ⁇ m, to the desired level. This is done either by grinding or ' by polishing or by chemical etching as well as by combinations of these thin processes.
• the process is checked using complex measuring methods.
• etching stop processes are used.
• an etching stop is introduced into one of the two wafers before bonding, which inhibits the chemical reaction during the thinning on the back.
• the layer thickness of the insulated silicon layer is determined by the depth in which the etching stop layer is introduced into the wafer to be thinly etched.
• the person skilled in the past therefore chose either the SIMOX process for producing a monocrystalline silicon layer on a buried dielectric, if a uniform, precisely adjustable silicon film thickness is required for the desired application and the processes associated with this process high costs due to the high implantation doses required and the restriction to a maximum oxide layer thickness of 0.5 ⁇ m.
• the wafer bonding method was used instead.
• the invention is therefore based on the object of specifying a method for producing monocrystalline silicon layers which leads to a high uniformity of the thickness of the silicon film produced, with which a high crystal quality of the silicon layer is achieved and with which the buried layer Insulator layers can be produced, the thickness of which is not limited to the oxide thickness which can be achieved with SIMOX processes.
• a preferred exemplary embodiment of the method according to the invention is explained in more detail below.
• the starting point of the method according to the invention are two silicon wafers.
• a SIMOX silicon wafer is first produced from one of the two silicon wafers using the SIMOX method.
• a buried SIMOX oxide layer is first formed by high-dose oxygen implantation, through which a silicon layer is separated from the silicon substrate of the SIMOX wafer.
• the thickness of the silicon layer can then be reduced or increased by methods known per se. For example, it is possible to strengthen the silicon layer by epitaxial growth.
• the silicon layer of the SIMOX silicon wafer is cured by tempering. This is preferably done at temperatures between 700 ° C and 1412 ° C for a period between thirty minutes and 15 hours.
• either the SIMOX silicon wafer or the other wafer, which will be referred to below as the carrier wafer, or both wafers are now thermally oxidized and / or provided with a dielectric.
• the dielectric layer is deposited on the carrier wafer, it is considered preferable to produce it on the entire surface of the carrier wafer. Then, as will be explained in more detail, it can then be used to protect the carrier wafer against Etching agents are used.
• Typical temperatures used in this tempering step are in the range of 800 ° C to 1300 ° C.
• the wafers bonded together to form a single disk of essentially twice the thickness are now etched in an alkaline solution until the chemical reaction on the buried SIMOX oxide layer is slowed down.
• the now exposed SIMOX oxide layer is preferably removed using hydrofluoric acid, which exposes the essentially monocrystalline silicon layer.
• the surface that is now exposed is the previous interface between the silicon layer and the SIMOX oxide layer that has now been removed by etching.
• the bonded wafer can be thermally oxidized and the resulting sacrificial oxide can then be etched away by wet chemistry.
• the wafer can also be polished chemically and / or mechanically.
• Another possibility which leads to both an improvement in the surface and a reduction in the crystal defect density of the silicon layer, is to introduce the required oxygen dose in the SIMOX oxygen implantation in sequential partial implantations of partial doses and tempering.
• Implantationsdo ⁇ sen from l ' ⁇ o 17 cm be applied "2 to 3 • 10 18 cm” 2.
• tion dose 4-10 17 cm “ 2 to produce the etching stop.
• this implantation dose which is far below the implantation doses that are typically used in SIMOX technology for producing buried, insulating layers, there is a considerable cost reduction achieved with simultaneous improvement in the quality of the silicon layer.
• the tempering is preferably carried out at 700 ° C. to 1412 ° C. with a duration of thirty minutes to 15 hours. Compared to the temperatures of above 1300 ° C with tempering times of six hours used in typical SIMOX tempering, a further cost reduction is therefore possible.
• Any etching medium with sufficient selectivity of the etching rate between silicon and silicon dioxide can be used for the back etching of the SIMOX silicon wafer.
• a 20 percent KOH solution at 80 ° C. is preferred. In this case a doping of 1.8 ⁇ 10 18 cm 2 is necessary.
• the method according to the invention while saving costs compared to the SIMOX method, it is possible to produce high-quality silicon layers with a very homogeneous layer thickness and an essentially monocrystalline structure, without being subject to restrictions with regard to the thickness of the buried insulator layer .
• the advantages of the SIMOX method and the wafer bonding method are therefore combined without having to accept the disadvantages and limitations of these methods.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Recrystallisation Techniques (AREA)
• Element Separation (AREA)

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Citations (2)

• 1992
  • 1992-04-01 DE DE19924210859 patent/DE4210859C1/de not_active Expired - Fee Related
• 1993
  • 1993-03-25 WO PCT/EP1993/000734 patent/WO1993020584A1/de not_active Ceased
  • 1993-03-31 FR FR9303955A patent/FR2689682B1/fr not_active Expired - Fee Related

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Non-Patent Citations (5)

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