FR2689682B1 - Procede de realisation d'une couche de silicium monocristalline sur un dielectrique enseveli. - Google Patents
Procede de realisation d'une couche de silicium monocristalline sur un dielectrique enseveli.Info
- Publication number
- FR2689682B1 FR2689682B1 FR9303955A FR9303955A FR2689682B1 FR 2689682 B1 FR2689682 B1 FR 2689682B1 FR 9303955 A FR9303955 A FR 9303955A FR 9303955 A FR9303955 A FR 9303955A FR 2689682 B1 FR2689682 B1 FR 2689682B1
- Authority
- FR
- France
- Prior art keywords
- producing
- silicon layer
- crystal silicon
- coated dielectric
- dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H10P90/1914—
-
- H10W10/181—
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE4210859A DE4210859C1 (enExample) | 1992-04-01 | 1992-04-01 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2689682A1 FR2689682A1 (fr) | 1993-10-08 |
| FR2689682B1 true FR2689682B1 (fr) | 1998-07-31 |
Family
ID=6455732
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR9303955A Expired - Fee Related FR2689682B1 (fr) | 1992-04-01 | 1993-03-31 | Procede de realisation d'une couche de silicium monocristalline sur un dielectrique enseveli. |
Country Status (3)
| Country | Link |
|---|---|
| DE (1) | DE4210859C1 (enExample) |
| FR (1) | FR2689682B1 (enExample) |
| WO (1) | WO1993020584A1 (enExample) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19715138A1 (de) * | 1997-04-13 | 1998-10-22 | Fraunhofer Ges Forschung | Verfahren zur Herstellung einer Anordnung von in Serie bzw. Reihe geschalteten Einzel-Solarzellen |
| US6455398B1 (en) * | 1999-07-16 | 2002-09-24 | Massachusetts Institute Of Technology | Silicon on III-V semiconductor bonding for monolithic optoelectronic integration |
| JP4828230B2 (ja) | 2004-01-30 | 2011-11-30 | 株式会社Sumco | Soiウェーハの製造方法 |
| DE102004029929A1 (de) * | 2004-06-21 | 2006-01-05 | Infineon Technologies Ag | Verfahren zum Herstellen von Mikrostrukturen |
| CN100487885C (zh) * | 2005-07-29 | 2009-05-13 | 上海新傲科技有限公司 | 一种绝缘体上硅的制作方法 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3976511A (en) * | 1975-06-30 | 1976-08-24 | Ibm Corporation | Method for fabricating integrated circuit structures with full dielectric isolation by ion bombardment |
| DE69126153T2 (de) * | 1990-02-28 | 1998-01-08 | Shinetsu Handotai Kk | Verfahren zur Herstellung von verbundenen Halbleiterplättchen |
-
1992
- 1992-04-01 DE DE4210859A patent/DE4210859C1/de not_active Expired - Fee Related
-
1993
- 1993-03-25 WO PCT/EP1993/000734 patent/WO1993020584A1/de not_active Ceased
- 1993-03-31 FR FR9303955A patent/FR2689682B1/fr not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| WO1993020584A1 (de) | 1993-10-14 |
| DE4210859C1 (enExample) | 1993-06-09 |
| FR2689682A1 (fr) | 1993-10-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |