FR2689682B1 - Procede de realisation d'une couche de silicium monocristalline sur un dielectrique enseveli. - Google Patents

Procede de realisation d'une couche de silicium monocristalline sur un dielectrique enseveli.

Info

Publication number
FR2689682B1
FR2689682B1 FR9303955A FR9303955A FR2689682B1 FR 2689682 B1 FR2689682 B1 FR 2689682B1 FR 9303955 A FR9303955 A FR 9303955A FR 9303955 A FR9303955 A FR 9303955A FR 2689682 B1 FR2689682 B1 FR 2689682B1
Authority
FR
France
Prior art keywords
producing
silicon layer
crystal silicon
coated dielectric
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9303955A
Other languages
English (en)
French (fr)
Other versions
FR2689682A1 (fr
Inventor
Gassel Helmut
Vogt Holger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Original Assignee
Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV filed Critical Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Publication of FR2689682A1 publication Critical patent/FR2689682A1/fr
Application granted granted Critical
Publication of FR2689682B1 publication Critical patent/FR2689682B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
FR9303955A 1992-04-01 1993-03-31 Procede de realisation d'une couche de silicium monocristalline sur un dielectrique enseveli. Expired - Fee Related FR2689682B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19924210859 DE4210859C1 (enExample) 1992-04-01 1992-04-01

Publications (2)

Publication Number Publication Date
FR2689682A1 FR2689682A1 (fr) 1993-10-08
FR2689682B1 true FR2689682B1 (fr) 1998-07-31

Family

ID=6455732

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9303955A Expired - Fee Related FR2689682B1 (fr) 1992-04-01 1993-03-31 Procede de realisation d'une couche de silicium monocristalline sur un dielectrique enseveli.

Country Status (3)

Country Link
DE (1) DE4210859C1 (enExample)
FR (1) FR2689682B1 (enExample)
WO (1) WO1993020584A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19715138A1 (de) * 1997-04-13 1998-10-22 Fraunhofer Ges Forschung Verfahren zur Herstellung einer Anordnung von in Serie bzw. Reihe geschalteten Einzel-Solarzellen
WO2001006546A2 (en) * 1999-07-16 2001-01-25 Massachusetts Institute Of Technology Silicon on iii-v semiconductor bonding for monolithic optoelectronic integration
JP4828230B2 (ja) 2004-01-30 2011-11-30 株式会社Ｓｕｍｃｏ Ｓｏｉウェーハの製造方法
DE102004029929A1 (de) * 2004-06-21 2006-01-05 Infineon Technologies Ag Verfahren zum Herstellen von Mikrostrukturen
CN100487885C (zh) * 2005-07-29 2009-05-13 上海新傲科技有限公司 一种绝缘体上硅的制作方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3976511A (en) * 1975-06-30 1976-08-24 Ibm Corporation Method for fabricating integrated circuit structures with full dielectric isolation by ion bombardment
EP0444943B1 (en) * 1990-02-28 1997-05-21 Shin-Etsu Handotai Company Limited A method of manufacturing a bonded wafer

Also Published As

Publication number Publication date
DE4210859C1 (enExample) 1993-06-09
WO1993020584A1 (de) 1993-10-14
FR2689682A1 (fr) 1993-10-08

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Legal Events

Date Code Title Description
ST Notification of lapse