FR2689682B1 - Procede de realisation d'une couche de silicium monocristalline sur un dielectrique enseveli. - Google Patents

Procede de realisation d'une couche de silicium monocristalline sur un dielectrique enseveli.

Info

Publication number
FR2689682B1
FR2689682B1 FR9303955A FR9303955A FR2689682B1 FR 2689682 B1 FR2689682 B1 FR 2689682B1 FR 9303955 A FR9303955 A FR 9303955A FR 9303955 A FR9303955 A FR 9303955A FR 2689682 B1 FR2689682 B1 FR 2689682B1
Authority
FR
France
Prior art keywords
producing
silicon layer
crystal silicon
coated dielectric
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9303955A
Other languages
English (en)
French (fr)
Other versions
FR2689682A1 (fr
Inventor
Gassel Helmut
Vogt Holger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Original Assignee
Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV filed Critical Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Publication of FR2689682A1 publication Critical patent/FR2689682A1/fr
Application granted granted Critical
Publication of FR2689682B1 publication Critical patent/FR2689682B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
FR9303955A 1992-04-01 1993-03-31 Procede de realisation d'une couche de silicium monocristalline sur un dielectrique enseveli. Expired - Fee Related FR2689682B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE4210859A DE4210859C1 (enExample) 1992-04-01 1992-04-01

Publications (2)

Publication Number Publication Date
FR2689682A1 FR2689682A1 (fr) 1993-10-08
FR2689682B1 true FR2689682B1 (fr) 1998-07-31

Family

ID=6455732

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9303955A Expired - Fee Related FR2689682B1 (fr) 1992-04-01 1993-03-31 Procede de realisation d'une couche de silicium monocristalline sur un dielectrique enseveli.

Country Status (3)

Country Link
DE (1) DE4210859C1 (enExample)
FR (1) FR2689682B1 (enExample)
WO (1) WO1993020584A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19715138A1 (de) * 1997-04-13 1998-10-22 Fraunhofer Ges Forschung Verfahren zur Herstellung einer Anordnung von in Serie bzw. Reihe geschalteten Einzel-Solarzellen
US6455398B1 (en) * 1999-07-16 2002-09-24 Massachusetts Institute Of Technology Silicon on III-V semiconductor bonding for monolithic optoelectronic integration
EP1710836A4 (en) * 2004-01-30 2010-08-18 Sumco Corp METHOD FOR PRODUCING AN SOI WATER
DE102004029929A1 (de) * 2004-06-21 2006-01-05 Infineon Technologies Ag Verfahren zum Herstellen von Mikrostrukturen
CN100487885C (zh) * 2005-07-29 2009-05-13 上海新傲科技有限公司 一种绝缘体上硅的制作方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3976511A (en) * 1975-06-30 1976-08-24 Ibm Corporation Method for fabricating integrated circuit structures with full dielectric isolation by ion bombardment
DE69126153T2 (de) * 1990-02-28 1998-01-08 Shinetsu Handotai Kk Verfahren zur Herstellung von verbundenen Halbleiterplättchen

Also Published As

Publication number Publication date
WO1993020584A1 (de) 1993-10-14
DE4210859C1 (enExample) 1993-06-09
FR2689682A1 (fr) 1993-10-08

Similar Documents

Publication Publication Date Title
EP0946974A4 (en) PRODUCTION OF A CRYSTALLINE SEMICONDUCTOR FILM ON A GLASS SUBSTRATE
MA23544A1 (fr) Formation d'une couche d'argent sur un substrat vitreux
EP0317445A3 (en) Method for fabricating a silicon carbide substrate
EP0594030A3 (en) Process for the fabrication of a wafer having a moncrystalline silicium carbide layer
AU585800B2 (en) Method for depositing a layer of abrasive material on a substrate
EP0610899A3 (en) Process for producing a silicon oxide film.
EP0970514A4 (en) MANUFACTURING METHOD FOR A THIN SILICON FILM
FR2670693B1 (fr) Procede pour nettoyer la surface d'un substrat par plasma.
EP0639858A3 (en) SOI technology for the production of silicon islands with a uniform thickness.
FR2683555B1 (fr) Installation pour la realisation d'une couche de protection de plate-forme.
EP0597302A3 (en) Process for etching a silicon substrate.
GB2193976B (en) Process for depositing a polysilicon film on a substrate
FR2690106B1 (fr) Feutre aiguillete comportant une couche de revetement et procede pour sa fabrication.
AU586047B2 (en) Apparatus for continuous silicon carbide whisker production
FR2607481B1 (fr) Procede et dispositif de formation d'une couche d'articles sur une table d'accumulation
FR2529189B1 (fr) Procede de fabrication d'une bande de silicium polycristallin pour photophiles
FR2648454B1 (fr) Procede de modification de la surface d'un substrat en verre
EP0598230A3 (en) Method of cleaning the surface of a silicon substrate.
FR2746544B1 (fr) Substrat de type silicium sur isolant pour la fabrication de transistors et procede de preparation d'un tel substrat
EP0238084A3 (en) Apparatus for depositing mono-molecular layer
FR2588277B1 (fr) Procede de depot d'une couche de tungstene sur une surface dielectrique
EP0600664A3 (en) Dry etching process for a silicon thin film.
FR2599892B1 (fr) Procede d'aplanissement d'un substrat semiconducteur revetu d'une couche dielectrique
FR2695118B1 (fr) Procédé de formation d'une couche barrière sur une surface d'un objet en verre.
FR2764309B1 (fr) Procede de creation d'une couche de silicium sur une surface

Legal Events

Date Code Title Description
ST Notification of lapse