WO1993010557A1 - Traitement destine aux plaquettes de silicium - Google Patents

Traitement destine aux plaquettes de silicium Download PDF

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Publication number
WO1993010557A1
WO1993010557A1 PCT/JP1992/000662 JP9200662W WO9310557A1 WO 1993010557 A1 WO1993010557 A1 WO 1993010557A1 JP 9200662 W JP9200662 W JP 9200662W WO 9310557 A1 WO9310557 A1 WO 9310557A1
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WO
WIPO (PCT)
Prior art keywords
atoms
silicon wafer
hours
temperature
wafer
Prior art date
Application number
PCT/JP1992/000662
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English (en)
Japanese (ja)
Inventor
Hiroyuki Kawahara
Hisami Motoura
Noriyuki Uemura
Original Assignee
Komatsu Electronic Metals Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=18258735&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO1993010557(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Komatsu Electronic Metals Co., Ltd. filed Critical Komatsu Electronic Metals Co., Ltd.
Publication of WO1993010557A1 publication Critical patent/WO1993010557A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering

Definitions

  • the present invention relates to defects in semiconductor silicon wafers used in semiconductor manufacturing, and in particular to SPD (Surface Particle and Surface Particles).
  • the present invention relates to a wafer processing technique called “defect” for making the surface of the wafer defective and fouling with a low tear.
  • SPD is a semiconductor silicon wafer which is observed on the surface by a part counter after washing a semiconductor silicon wafer with NH (NH4OM2O2-H2O). Say anything more than 0 ".
  • Sections to be solved by the invention Therefore, as an easy way to reduce SPD, it is only necessary to slow down the pulling speed in the production of single crystals, but naturally this will reduce productivity. However, it affects its physical properties, such as oxygen-induced defects and oxygen precipitation ability.
  • the present invention provides a new technology that can reduce SPD even for a wafer obtained from a single crystal grown at an increased pulling speed.
  • an unheated semiconductor silicon wafer having an oxygen concentration of X L0 17 to 2 X I 0 18 atoms / cc and a carbon concentration of tx 10 16 atomsZcc or less is subjected to 1000 x 1000 in an oxidizing atmosphere. ° C to L300. It is heat-treated at a temperature of C for 0.5 to 5 hours.
  • the oxygen saturation t X ⁇ 0 17 to 2 x I 0 18 atoms / cc, the carbon agitation LO x LO 16 atonisZ The unheated semiconductor silicon wafer of CC or less is subjected to L000 in an inert atmosphere. Heat-treat at a temperature of ° C to 1300 ° C for 0.5 to 5 hours.
  • an unheated semiconductor silicon nanometer having an oxygen concentration ix 10 17 to 2 X 10 18 atoms cc carbon concentration LX lOT 6 atoms After heat treatment at 1300 ° C at 0-5 to 5 o'clock, the main surface is polished.
  • an unheat-treated semiconductor silicon wafer having an oxygen agitation t X ⁇ 0 17 to 2 ⁇ L 0 18 atoms / cc and a carbon concentration L ⁇ L 0 16 atoms / eC or less is placed in an inert atmosphere. After heat treatment at a temperature of 1000 ° C to 1300 ° C for 0.5 to 5 hours, the main surface is polished.
  • FIG. 1 is a graph showing the relationship between the heat treatment temperature and the SPDO in silicon wafer.
  • Fig. 2 shows the relationship between the oxide film breakdown voltage failure rate and SPD.
  • Figure 3 shows the relationship between the single crystal pulling rate by the Chiral Sky method and the SPD teaching in the crystal.
  • SPD is thought to be a type of defect formed during the crystal cooling process during single crystal growth, but it is not yet clear at this time.
  • the oxygen disturbance IX 10 17 to 2 X I 0 1 toms / cc and the carbon concentration is I x I 0 16 atoms / cc or less: t 000 as in the present invention . It is considered that these may be dissolved by the temperature treatment of C or more.
  • U00 was used for 25 wafers each obtained from a silicon single crystal having the same physical properties. Heat treatment was performed at C and 1000 ° C.
  • FIG. 1 plots the average values of the SPD teaching of the wafers obtained in Example L and Reference Example I above for each processing temperature. As can be seen, the SPD education in the wafer has been drastically reduced due to the heat treatment at 1000 ° C or higher.
  • Wafer in / out speed to heat treatment furnace ⁇ 2 ⁇ 77 ⁇ min
  • the percentage of non-defective products that have changed from Z wafers has increased to 90%.
  • heat treatment at L000 ° C or more in oxidizing or inert atmosphere By using the heat treatment method of the present invention, the breakdown voltage of the oxide film can be greatly increased. Further, after this heat treatment, the main surface of the wafer is mirror-polished, whereby the yield i can be further improved. Therefore, when a device is formed, productivity can be significantly improved.
  • the unheated wafer that has been ejected is usually first subjected to a heat treatment at about 650 ° C. for erasing thermal donors.
  • the treatment is also necessary because it also has the function of eliminating thermal damage.
  • the present invention is intended to reduce defects in semiconductor silicon wafers used in semiconductor manufacturing, and in particular, to reduce the scrutiny and contamination of the wafer surface called SPD (Surface Particle and Defect). Applies to wafer processing technology.
  • SPD Surface Particle and Defect

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

Une plaquette de silicium destinée aux semi-conducteurs présente une concentration en oxygène de 1x10?17 à 2x1018¿ atomes/cm3 et une concentration en carbone de 1x1016 atomes/cm3. Dans une atmosphère oxydante ou inerte, on la porte à 1000 à 1300 °C pendant 30 minutes à 5 heures. En plus, on peut éventuellement polir comme un miroir la surface principale de cette plaquette une fois qu'elle a subi ce traitement thermique. La présente invention vise à limiter le nombre de défauts présents dans les plaquettes à semi-conducteurs et à améliorer le rendement de leur fabrication.
PCT/JP1992/000662 1991-11-22 1992-05-22 Traitement destine aux plaquettes de silicium WO1993010557A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3/332779 1991-11-22
JP3332779A JP2770091B2 (ja) 1991-11-22 1991-11-22 シリコンウェハの処理方法

Publications (1)

Publication Number Publication Date
WO1993010557A1 true WO1993010557A1 (fr) 1993-05-27

Family

ID=18258735

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1992/000662 WO1993010557A1 (fr) 1991-11-22 1992-05-22 Traitement destine aux plaquettes de silicium

Country Status (2)

Country Link
JP (1) JP2770091B2 (fr)
WO (1) WO1993010557A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0948037A1 (fr) * 1996-07-29 1999-10-06 Sumitomo Metal Industries, Ltd. Plaquette epitaxiale en silicium et son procede de fabrication
WO2004073057A1 (fr) * 2003-02-14 2004-08-26 Sumitomo Mitsubishi Silicon Corporation Procede de fabrication d'une tranche de silicium
JP2008133171A (ja) * 2006-10-04 2008-06-12 Siltronic Ag シリコンウェハおよびその作製方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5893982A (en) * 1997-01-08 1999-04-13 Seh America, Inc. Prevention of edge stain in silicon wafers by oxygen annealing
EP1061565A1 (fr) 1998-12-28 2000-12-20 Shin-Etsu Handotai Co., Ltd Procede de recuit thermique d'une plaquette de silicium, et plaquette de silicium
US7160385B2 (en) 2003-02-20 2007-01-09 Sumitomo Mitsubishi Silicon Corporation Silicon wafer and method for manufacturing the same
EP1542269B1 (fr) * 2002-07-17 2016-10-05 Sumco Corporation Procédé de fabrication d'un tranche de silicium de haute résistance
WO2010016586A1 (fr) 2008-08-08 2010-02-11 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 Procédé de fabrication de tranche de semi-conducteur

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03184345A (ja) * 1989-12-13 1991-08-12 Nippon Steel Corp シリコンウェハおよびその製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03184345A (ja) * 1989-12-13 1991-08-12 Nippon Steel Corp シリコンウェハおよびその製造方法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0948037A1 (fr) * 1996-07-29 1999-10-06 Sumitomo Metal Industries, Ltd. Plaquette epitaxiale en silicium et son procede de fabrication
EP0948037A4 (fr) * 1996-07-29 2000-02-02 Sumitomo Metal Ind Plaquette epitaxiale en silicium et son procede de fabrication
WO2004073057A1 (fr) * 2003-02-14 2004-08-26 Sumitomo Mitsubishi Silicon Corporation Procede de fabrication d'une tranche de silicium
EP1513193A1 (fr) * 2003-02-14 2005-03-09 Sumitomo Mitsubishi Silicon Corporation Procede de fabrication d'une tranche de silicium
EP1513193A4 (fr) * 2003-02-14 2007-02-28 Sumco Corp Procede de fabrication d'une tranche de silicium
CN100397595C (zh) * 2003-02-14 2008-06-25 三菱住友硅晶株式会社 硅片的制造方法
US7563319B2 (en) 2003-02-14 2009-07-21 Sumitomo Mitsubishi Silicon Corporation Manufacturing method of silicon wafer
JP2008133171A (ja) * 2006-10-04 2008-06-12 Siltronic Ag シリコンウェハおよびその作製方法
US7964275B2 (en) * 2006-10-04 2011-06-21 Siltronic Ag Silicon wafer having good intrinsic getterability and method for its production

Also Published As

Publication number Publication date
JP2770091B2 (ja) 1998-06-25
JPH05144827A (ja) 1993-06-11

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