WO1992017832A1 - Generateur de temps local pour un ordinateur - Google Patents

Generateur de temps local pour un ordinateur Download PDF

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Publication number
WO1992017832A1
WO1992017832A1 PCT/GB1992/000593 GB9200593W WO9217832A1 WO 1992017832 A1 WO1992017832 A1 WO 1992017832A1 GB 9200593 W GB9200593 W GB 9200593W WO 9217832 A1 WO9217832 A1 WO 9217832A1
Authority
WO
WIPO (PCT)
Prior art keywords
time
computer
local time
bus
register
Prior art date
Application number
PCT/GB1992/000593
Other languages
English (en)
Inventor
Steven Hosgood
Original Assignee
Institute For Industrial Information Technology Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute For Industrial Information Technology Limited filed Critical Institute For Industrial Information Technology Limited
Priority to CA002107584A priority Critical patent/CA2107584A1/fr
Publication of WO1992017832A1 publication Critical patent/WO1992017832A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock

Definitions

  • This invention relates to a local time generator for a computer, to make the local time available when required by a central processing unit of the computer.
  • a particular application where local time is needed accurately is in a loosely coupled distributed computer system, where the individual node computers operate in their own timeframes, but where correction of the time generators of the nodes is carried out to synchronise these timeframes.
  • each node it is desirable for each node to record the time of receipt of each message over the communications medium from other nodes, and to apply a timestamp to each transmitted message so that the receiving node computer can compare the time of transmission, according to the timeframe of the transmitting node, with the time of receipt as measured in its own time frame.
  • a local time generator for a computer which makes the local time available when required by any element or unit of the computer, e.g. a central processing unit of the computer.
  • a local time generator for a computer comprising means for continuously generating signals representing local time, and a time bus to which said time signals are continuously applied.
  • the local time is continuously available on the timebu ⁇ , and may be used by any unit connected onto the timebus.
  • the local time generator includes at least one register connected to the timebus.
  • the processor of the computer into which the local time generator is fitted, may at any instant command the register to latch its contents, which then represent the local time at that instant.
  • the processor can proceed with othe operations and retrieve the recorded time or timestamp from th register when free to do so.
  • the processor ma command the snap-shot register to indicate when a predetermine local time is reached: for this purpose the processor load the snap-shot register with data representing the set time after which the register continuously compares that set tim with the local time appearing on the time bus, until the se time is reached.
  • the snap-shot register may be arranged to respond t an input signal for example received via an input interface o the computer into which the time generator is fitted, t trigger the snap-shot register to latch into itself the loca time at that instant.
  • the processor can retrieve this recor or timestamp later on.
  • Any number of snap-shot registers may be provided i the computer so that a number of events may be recorded an retrieved later by the processor, before the registers ar reset.
  • the computer into which the time generator is fitte may comprise a plurality of processors, each with its own dat bus, memory and optionally an input/output interface, plus snap-shot register connected to the timebus.
  • the computer into which the time generator is fitte may comprise a node computer for a loosely coupled distribute computer system, in which case it further comprises communications unit for coupling the data bus to communications medium common to a plurality of such nod computers.
  • the communications medium has a snap shot register associated with it, for the purpose of recordin the time of receipt of each message received over th communications medium, and for applying a timestamp to eac message which the node computer transmits.
  • the node computer compares the time o receipt of each message according to its own time frame, wit the timestamp carried by that message and representing the tim of transmission, measured according to the timeframe of th transmitting node computer. If any discrepancy is foun (allowing for transmission time) , the time generator of the node computer can be adjusted automatically to synchronise with the other node computer(s) .
  • the adjustment of the time generator is carried out by altering the rate of change of time for a period
  • the time generator is formed as a unit together with at least one snap-shot register (preferably two snap-shot registers) and preferably as an integrated circuit.
  • Figure 1 is a schematic block diagram of a node computer fitted with a local time generator in accordance with this invention, the computer being shown in a loosely coupled distributed computer system;
  • Figure 2 is a schematic block diagram of the local time generator.
  • each node computer in a loosely coupled distributed computer system.
  • the overall system comprises a plurality of such node computers connected to a common communication medium MED.
  • Each node computer may comprise a single processor, or as shown it may comprise a plurality of processors one of which may act as a master supervising the others.
  • each processor comprises a bus to which is connected the CPU, memory MEM, an input/output interface I/O, and a snap- shot register SSR (the function of which will be described) .
  • the computer bus CBI for one of the CPU's may extend to a communications unit COMMS which is coupled to the communications medium MED.
  • the bus for each of the other processors may also be connected to the bus CBI by respective communications units e.g. CM. This is one of many possible architectures.
  • the node computer is fitted with a local time generator which comprises a time generator TIME GEN, a timebus TB and two snap-shot registers SSRl, SSR2.
  • the snap-shot registers SSRl and SSR2 are connected to the timebus: register SSRl i triggered from the communications unit COMMS and register SSR is connected to the databus CBI of the master processor.
  • Th snapshot register e.g. SSR of each of the other processors i also connected to the time bus TB.
  • the time generator continuously generate signals defining the local time and applies these signals t the timebus TB: the signals may be updated typically ever 1 ⁇ s.
  • the timebus TB therefore always carries the curren local time and this is available to all processors and to th communications unit COMMS via the respective snap-sho registers.
  • this register latches its contents, corresponding to the data currently on the timebus; th register now holds data representing the local time at th instant the processor made the command; the processor need no retrieve this data from the snap-shot register immediately, bu may carry on with further processing and then retrieve the dat or timestamp when free to do so.
  • a processor may command it snap-shot register to indicate when a predetermined local tim has been reached: in this case the register holds dat representing the time set by the processor and continuousl compares this data with the local time data appearing on th timebus TB: when these two correspond, the register sends a indicating signal to its processor.
  • the snap-shot register SSRl is for use solely by th main communications unit COMMS.
  • the communications unit COMMS can instruct the register SSRl to record the time of receipt of the message, for retrieval later by one of the processors over the data bus.
  • the communications unit COMMS can instruct the register SSRl to record the time of transmission, so that this can be added as a timestamp to the outgoing message and also recorded by the transmitting processor.
  • the time generator TIME GEN and two snap-shot registers SSRl and SSR2 are formed as a unit o a single chip and Figure 2 shows further details.
  • the time generator comprises a data bu connectable externally to the data bus CBI of the nod computer: also the timebus may be extended via an externa interface.
  • Snap-shot registers SSRl and SSR2 are connecte to the data bus and timebus of the chip.
  • a timing system T is driven by an external 16 MHz crystal and in turn drives 52 bit counter COUNT. In essence the timing system comprise a divider ( ⁇ 16) but is adjustable as will be described.
  • Th timebus preferably includes 16 data lines, 4 strobe lines an a status line and the time signals are applied to the timebu in multiplex manner: thus the complete data to define th local time consists of too many bits to be carrie simultaneously on the timebus, so the contents of the counte (defining the local time) are applied to the time-bus dat lines in four parts in succession, the strobe lines definin each of the four parts in turn.
  • Each snap-shot register ha a command unit CU which acts to latch the register content upon receipt of a signal from an external trigger input TRI 1 or TRIG 2.
  • the local time held by the counter COUNT may be set o updated by data written into it from the data bus.
  • the timin system can be adjusted by an adjustment register AR, fo example to synchronize with the timing systems of other nod computers coupled to the same communications medium MED.
  • a address decode circuit DECODE receives external address an strobe inputs via a buffer, to drive the adjustment registe AR under the command of a control register CR.
  • the maste processor of the node is able to compare the time of receip of any message, against a timestamp contained in that messag and indicating the time of transmission according to th timeframe of the transmitting node computer.
  • th master processor of the appropriate node runs a known algorith to calculate a correction needed to adjust its own timin generator.
  • the correction is applied via the data bus to th adjustment register AR and thence to the timing system TS.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Multi Processors (AREA)

Abstract

Un générateur de temps local pour un ordinateur, plus particulièrement un ordinateur nodal faisant partie d'un système d'ordinateurs distribués à liaison souple, comprend des moyens permettant de générer en continu des signaux de temps local, ainsi qu'un bus de temps auquel sont appliqués lesdits signaux. Un système d'horloge TS pilote ainsi un compteur COUNT, les lignes de sortie étant reliées en parallèle aux lignes respectives du bus de temps. Lors de l'utilisation du générateur, le temps local est disponible sur le bus de temps, et peut être utilisé par toute unité reliée au bus de temps. Un ou plusieurs registres SSR1, SSR2 sont reliés au bus de temps et peuvent être enclenchés pour enregistrer le temps de réalisation de toute opération.
PCT/GB1992/000593 1991-04-02 1992-04-02 Generateur de temps local pour un ordinateur WO1992017832A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA002107584A CA2107584A1 (fr) 1991-04-02 1992-04-02 Generateur de signaux horaires pour ordinateur

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9106868.4 1991-04-02
GB9106868A GB2254455B (en) 1991-04-02 1991-04-02 Calendar time generator for a computer.

Publications (1)

Publication Number Publication Date
WO1992017832A1 true WO1992017832A1 (fr) 1992-10-15

Family

ID=10692508

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1992/000593 WO1992017832A1 (fr) 1991-04-02 1992-04-02 Generateur de temps local pour un ordinateur

Country Status (5)

Country Link
EP (1) EP0578684A1 (fr)
AU (1) AU1532992A (fr)
CA (1) CA2107584A1 (fr)
GB (1) GB2254455B (fr)
WO (1) WO1992017832A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2331165A (en) * 1997-11-08 1999-05-12 Gerald William Haywood Computer mountable clock/calendar
GB2371552A (en) * 2000-08-25 2002-07-31 Reckitt Benckiser Poly(vinyl alcohol) packaging for e.g. a detergent composition

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2566555A1 (fr) * 1984-06-22 1985-12-27 Austria Mikrosysteme Internal Reseau d'ordinateurs interconnectables pour travail en temps reel
US4803708A (en) * 1986-09-11 1989-02-07 Nec Corporation Time-of-day coincidence system
EP0355363A2 (fr) * 1988-08-19 1990-02-28 Motorola, Inc. Circuit intégré rythmeur avec plusieurs canaux et processeur de service attribué

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2064835B (en) * 1979-12-11 1984-06-06 Casio Computer Co Ltd Power consumption control system for electronic digital data processing devices
US4368514A (en) * 1980-04-25 1983-01-11 Timeplex, Inc. Multi-processor system
US4845437A (en) * 1985-07-09 1989-07-04 Minolta Camera Kabushiki Kaisha Synchronous clock frequency conversion circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2566555A1 (fr) * 1984-06-22 1985-12-27 Austria Mikrosysteme Internal Reseau d'ordinateurs interconnectables pour travail en temps reel
US4803708A (en) * 1986-09-11 1989-02-07 Nec Corporation Time-of-day coincidence system
EP0355363A2 (fr) * 1988-08-19 1990-02-28 Motorola, Inc. Circuit intégré rythmeur avec plusieurs canaux et processeur de service attribué

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2331165A (en) * 1997-11-08 1999-05-12 Gerald William Haywood Computer mountable clock/calendar
GB2371552A (en) * 2000-08-25 2002-07-31 Reckitt Benckiser Poly(vinyl alcohol) packaging for e.g. a detergent composition

Also Published As

Publication number Publication date
GB2254455B (en) 1995-01-04
AU1532992A (en) 1992-11-02
CA2107584A1 (fr) 1992-10-03
EP0578684A1 (fr) 1994-01-19
GB2254455A (en) 1992-10-07
GB9106868D0 (en) 1991-05-22

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