Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
  • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
  • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
  • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
  • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
  • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
  • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
  • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
  • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
  • H01L25/0657—Stacked arrangements of devices
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
  • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
  • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
  • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
  • H01L2225/06503—Stacked arrangements of devices
  • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
  • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
  • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
  • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
  • H01L2225/06503—Stacked arrangements of devices
  • H01L2225/06551—Conductive connections on the side of the device
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
  • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
  • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
  • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
  • H01L2225/06503—Stacked arrangements of devices
  • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01005—Boron [B]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01006—Carbon [C]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01014—Silicon [Si]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01023—Vanadium [V]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01033—Arsenic [As]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01058—Cerium [Ce]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01087—Francium [Fr]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/013—Alloys
  • H01L2924/014—Solder alloys
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/12—Passive devices, e.g. 2 terminal devices
  • H01L2924/1204—Optical Diode
  • H01L2924/12042—LASER
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/14—Integrated circuits

Definitions

• the present invention relates to a method and a device for the interconnection of stacked semiconductor pads, each of the pads containing an integrated circuit.
• the pellets are arranged on a printed circuit, joined to each other perpendicular to the printed circuit; the connection pads of each of the pads are brought to the same side of the pad; this side is arranged on the printed circuit and the connections with the latter are made there.
• this arrangement has in particular limitations related to the number of pads that it is physically possible to have on one side of a semiconductor chip; in addition, it is expensive because the pads are not standard (the arrangement of the pads must be changed); finally, the connections thus made are not very accessible and moreover not visible, which limits their use.
• the present invention relates to an interconnection device for stacked integrated circuits which avoids these drawbacks and limitations by the use of the faces of the stack as an interconnection surface.
• wafers formed from one or more semiconductor wafers are stacked and made integral with each other; in one embodiment, their connection pads are each connected to any one of the faces of the stack except one, called base, which is intended to be in contact with a printed circuit substrate.
• the connection of the wafers to each other is carried out on the faces of the stack; the case. where appropriate, the connection of the wafers with the printed circuit is carried out by means of so-called stacking pads, formed on the faces of the stack, for example in the vicinity of the edges of the base, the connections joining the pads together formed on the faces of the stack and at least some of them being non-rectilinear.
• Figure 1 is therefore an exploded view of a stack according to the invention of semiconductor wafers.
• the plates P can be semiconductor wafers or a printed circuit, ceramic or epoxy, comprising one or more semiconductor chips.
• the stack is for example closed by a first insulating plate F v , forming the front face and a second insulating plate F resort, forming the rear face.
• FIG. 2 represents, by way of example, a wafer P of the stack of the previous figure, constituted by a semiconductor wafer.
• This consists of a semiconductor wafer 20 in which is made any integrated circuit, a memory for example.
• On the surface of the plate P appear studs * ? -., Arranged for example in the vicinity of two of the edges of the plate, allowing the electrical connection of the circuit contained in the plate to the outside; the pads P_ can of course be arranged around the four sides of the plate P, or at any point on its surface.
• the stack of FIG. 1 is, in this embodiment, intended to be placed on a printed circuit substrate CI via one of its faces B, called the base.
• the front and rear faces F v and F- p for example, carry so-called stacking studs P p , intended for connection of the nipple to the other circuits carried by the printed circuit Cl.
• These stacking pads P ⁇ are arranged for example in the vicinity of the base B.
• FIG. 3 illustrates an exemplary embodiment of the stack interconnection method according to the invention.
• the first step marked 61, consists in electrically connecting the pads P of the plates P to the lateral faces of the stack. This step is illustrated in FIG. 4, which is a section along the plane A-A of FIG. 1.
• each of these plates is covered with an insulating layer 30, except at the locations of the connection pads P.
• a conducting wire F is connected, for example by welding, to each of the pads P thinkof each of the wafers.
• Each of the wires F is directed towards one of the faces of the stack, according to the needs of the connectors.
• the wires F can be replaced by conductive tapes. To simplify the description, we will speak hereinafter only of "conductive wires" or of “conductors” F.
• each of the plates P can be, before stacking, covered with a drop of protective insulating material (silicone or the like), as E is usual for the protection of the semiconductor pellets.
• the assembly is then joined together using an insulating material D, such as an epoxy resin.
• an insulating material D such as an epoxy resin.
• the dielectric material D has not been hatched although seen in section.
• the stack is then cut or polished so that the wires F are flush with IPS faces of the stack.
• the next step (63, Figure 3) consists of depositing one (or more) conductive coating, M, metallic for example, on all of the fnc-r-- of the stack thus formed.
• the next step (64, FIG. 3) consists in making connections on the lateral faces of the stack, from the layer M, connecting the wires F to each other and to the pads P- ,.
• FIG. 5 represents a stack according to the invention on which are illustrated examples of connections.
• FIGS 6a and 6b illustrate in more detail the step
• FIG. 6a represents a fractional and enlarged view of a piece of the base of FIG. 5, where we see a connection C and a pad of base P-p.
• Figure 6b is a sectional view along an axis BB of Figure 6a.
• connection C is formed by two etchings 51 and 52, produced using a laser which locally destroys the metal layer M and reveals the insulating layer D (pointElée in FIG. 6a for the clarity of the diagram), making thus the electrical insulation of the connection
• the pedestal pads P can be advantageously produced by the same laser engraving technique, as shown in FIG. 6a.
• FIG. 7 represents another embodiment of the method according to the invention.
• connection of fEs or ribbons
• empéement and joining of the plates are identical to what was described figure 3.
• the next step (73) consists in making a groove in the base, at the level where the fs F are flush so as to release the end of the latter.
• This step has been illustrated in FIG. 8 where an alignment of five fEs F of the face F ⁇ of FIG. 5 has been reproduced by way of example, the groove being marked 81 and the base, E.
• These grooves such as 81 can be produced by laser etching in the insulating material D (see FIG. 4).
• the next step (74) consists in depositing a conductive layer (metal for example) on the whole of the footing, that is to say faces of the footing, grooves (teEes that 81) and fEs F.
• the last step (75) shown in FIG. 7 consists in removing the conductive layer on the flat surfaces of the base, so as to only allow it to remain in the grooves teEes 81 where eEe makes the desired connection. This last step can be carried out for example by polishing or using a laser.
• FIG. 8 shows a straight groove 81 connecting aligned fEs F, but the grooves can of course take any shape and connect any fE F depending on the connections to be made.
• This embodiment has the advantage, compared to the previous one, of allowing a smaller connection pitch.
• FIG. 9 illustrates an alternative embodiment of the connections of the plates on the faces of the base according to the invention.
• the empEement E is shown as obtained after the process described in FIG. 7, that is to say having grooves (81, 91) formed at the level of the fEs F, the grooves and the fEs F being metaEized (layers 92 and 93, respectively) and the plane faces F., of the base being de-metallized.
• an insulating material 95 is deposited in each of the grooves so as to seal them. If necessary, the section of the fEs F is then cleaned so as to allow a later electrical connection.
• the next step consists in metallizing the whole of the base E again and then in etching in this last conductive layer the contours (98) of the connections (96, 97) to be produced, in a similar manner to what is described below. above (step 64 of Figure 3 in conjunction with Figures 6).
• FIG. 9 shows only two connections, which have been hatched for the readability of the figure, one (97) connecting one of the fEs F of the groove 91 with other pads not shown and the other (96) passing through the two grooves (91, 81), without electrical connection.
• This variant thus makes it possible to simply cross connections on the surface of the base.
• the fEs F can be individually isolated.
• the connection to the printed circuit is made by the pad blocks Pp, which can be placed on any lacquered side and which, therefore, can be numerous.
• the connection pads Pp, -printed circuit are accessible and visible, which reduces the cost and allows certain applications, notably mEitaires.
• the base has been described such that the plates are perpendicular to the printed circuit but that the base can be produced in the other direction and the plates be parallel to this printed circuit.
• the pedestal pads Pp Have been illustrated on the faces F v and Fp, but can be arranged on any lacquered side of the pedestal and anywhere on these faces, depending on the application; in fact, when the base is, as shown in FIG. 1, intended to be placed on a printed circuit, the pads Pp can be placed on any side, except the base, but preferably in the vicinity of the edges of the base; but E is also possible to interconnect two (or more) stacks with each other, in which case the pads Pp can occupy any position.
• connections C by laser has been described using an etching technique but it is also possible to use a deposition technique using a laser; for this purpose, the stack is placed in an organometallic vapor and the area where it is desired to form the connection; the heating causes the decomposition of the vapor and the deposition of the metal at the desired location; the deposition of a local insulating layer is done, as necessary, in a similar manner by adapting the composition of the vapor.
• a single layer of connections C has been shown on the footing, but it is possible to have several (isolated between eEes), for example by the laser deposition technique described above, so for example to allow crossings of connections.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Wire Bonding (AREA)
• Design And Manufacture Of Integrated Circuits (AREA)

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Citations (3)

• 1990
  • 1990-12-11 FR FR9015473A patent/FR2670323B1/fr not_active Expired - Fee Related
• 1991
  • 1991-12-06 EP EP91403307A patent/EP0490739B1/de not_active Expired - Lifetime
  • 1991-12-06 KR KR1019920701892A patent/KR920704344A/ko active IP Right Grant
  • 1991-12-06 DE DE69126599T patent/DE69126599T2/de not_active Expired - Lifetime
  • 1991-12-06 WO PCT/FR1991/000978 patent/WO1992010853A1/fr unknown
  • 1991-12-06 ES ES91403307T patent/ES2104681T3/es not_active Expired - Lifetime
  • 1991-12-06 JP JP50211392A patent/JP3415621B2/ja not_active Expired - Lifetime

Patent Citations (3)

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