WO1990014690A1 - Structure de protection contre des decharges electrostatiques a contrainte alterable de tension - Google Patents

Structure de protection contre des decharges electrostatiques a contrainte alterable de tension Download PDF

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Publication number
WO1990014690A1
WO1990014690A1 PCT/US1990/002609 US9002609W WO9014690A1 WO 1990014690 A1 WO1990014690 A1 WO 1990014690A1 US 9002609 W US9002609 W US 9002609W WO 9014690 A1 WO9014690 A1 WO 9014690A1
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WO
WIPO (PCT)
Prior art keywords
region
conductivity type
transistor
substrate
emitter
Prior art date
Application number
PCT/US1990/002609
Other languages
English (en)
Inventor
Leslie Ronald Avery
Original Assignee
David Sarnoff Research Center, Inc.
Sharp Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB898911360A external-priority patent/GB8911360D0/en
Application filed by David Sarnoff Research Center, Inc., Sharp Corporation filed Critical David Sarnoff Research Center, Inc.
Publication of WO1990014690A1 publication Critical patent/WO1990014690A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection

Definitions

  • the present invention relates to electrical protection devices, and more particularly to devices providing protection for monolithic integrated circuits against relatively large voltage transients.
  • Integrated circuits are incorporated in many types of electrical equipment. Such integrated circuits are generally vulnerable to damage from high voltage transients.
  • high voltage transients may have positive and/or negative peak levels of 100 volts or more and may have a duration of several microseconds.
  • High voltage electrostatic discharge (ESD) transients can also result from a user becoming electrostatically charged, for example, by friction or by induction and touching equipment controls.
  • Protection devices applicable to the protection of integrated circuits from damage that would otherwise result from a high voltage transient are known in the art. Such devices are described in, for example, Avery, U.S. Patent No.
  • a protection device be able to handle transients associated with relatively large energy without itself being destroyed or having its protective capability significantly impaired. Furthermore, it is desirable that the protective device provide an indication of having been subjected to a large voltage transient.
  • a semiconductor protection circuit comprises a semiconductor substrate of a first conductivity type, a region of second conductivity type in the substrate at the surface thereof.
  • the region of second conductivity type has disposed therein first and second regions of the second conductivity type, a third region of the first conductivity type at the surface of the substrate, and a fourth region of the second conductivity type at the surface of the substrate adjacent the third region.
  • a shallow field region of first conductivity type extends a distance from the surface into the region of second conductivity type and extends between the first and second regions.
  • a first electrical contact overlies the first region of the second conductivity type.
  • a second electrical contact overlies the third and fourth regions.
  • a transient-responsive means is responsive to a high voltage transient being applied between a terminal of an integrated circuit to be protected and a source of reference potential for forming a transistor of second polarity type of second polarity type having an emitter electrode formed in the field layer, a base electrode formed in the region of second conductivity type, and a collector electrode formed in the semiconductor substrate, and an avalanche breakdown diode formed between the emitter of the transistor and the electrode contact.
  • a semiconductor protection circuit comprises a semiconductor substrate of a first conductivity type, the substrate having adjacent a surface thereof a relatively shallow, relatively high conductivity, field layer of the first conductivity type.
  • a region of second conductivity type is in the substrate at the surface and has disposed therein first and second regions of the second conductivity type.
  • a further region of first conductivity type is in the substrate at the surface.
  • a further region of the second conductivity type is in the substrate at the surface of the substrate adjacent the further region of the first conductivity type.
  • a terminal overlies the surface of the further region of the second conductivity type.
  • a bipolar transistor of a particular polarity type e.g. NPN or PNP
  • a transient-responsive structure is responsive to a high voltage transient between the terminal and the substrate which alters the doping profile thereby forming a transistor of second conductivity polarity type having an emitter electrode comprising the field layer, a base electrode comprising the region of second conductivity type, a collector electrode formed by the substrate, and an avalanche breakdown diode comprising the emitter of the transistor of second conductivity type and the terminal.
  • a first transistor of a first polarity type has a collector electrode resistively coupled to a terminal of an integrated circuit to be protected against a high voltage transient, an emitter electrode coupled to a point of reference potential, and a base electrode coupled to the point of reference potential.
  • a transient- responsive arrangement is responsive to an occurrence of a high voltage transient for thereupon altering the doping profile and forming in the integrated circuit a second transistor of second polarity type having an emitter electrode coupled to the terminal, a collector electrode coupled to the base electrode of the first transistor, and a base electrode coupled to the collector electrode of the first transistor.
  • Fig. 1 shows a cross-section, not to scale, of a protection device in accordance with the invention
  • Fig. 2 shows a schematic of exemplary connections of a protection circuit and an integrated circuit of the invention
  • Fig. 3 shows a schematic circuit diagram of a protection device corresponding to the device of Fig. 1 ;
  • Fig. 4 shows a graph of an electrical characteristic of the device of Figs. 1 and 3
  • Fig. 5 shows a cross-section, not to scale, of a protection device of another embodiment of the invention
  • Fig. 6 shows a schematic of a protection device corresponding to the device of Fig. 4 and
  • Fig. 7 shows a graph of a characteristic of the device of Figs. 5 and 6
  • a circuit is formed in a semiconductor substrate 10 of P type silicon.
  • An N" well 12 which is relatively lightly doped region, typically 10 4 - l ⁇ l -5/cc, and of relatively low conductivity, is disposed in substrate 10.
  • a first N + region 14 which is relatively heavily doped region, typically l ⁇ l 8/cc, and of relatively high conductivity, is disposed within N" well 12.
  • a second N + region 16 is also formed in the N ⁇ well 12 and extends beyond its border into the substrate 10.
  • a third N + region 18 is disposed in substrate 10 outside of the borders of N- well 12.
  • the N" well 12 and the N+ regions 14, 16, and 18 are typically formed simultaneously in the same processing step.
  • a first P + region 20 which is relatively heavily doped and of relatively high conductivity is in substrate 10 adjacent the third N + region 18 and is preferably in contact therewith so as to form a P + N + junction therewith.
  • N + region 18 be close to first P + region 20.
  • P + implant layers 22 and 24 are commonly referred to in the art as field implant regions. They are generally utilized to increase the inversion voltage of the substrate surface, thereby preventing the formation of spurious conduction channels along the surface which may otherwise result from electrical charge trapped in the overlying layers.
  • An insulating layer 26, such as a silicon oxide, overlies the surface of substrate 10.
  • Insulating layer 26 contains a P type dopant such as boron. Openings are formed in insulating layer 26 over regions 14, 18, and 20 in order to allow the making of electrical contact thereto at a contact surface 28 thereof.
  • a conductive layer 30, which may for example be aluminum, molybdenum, polysilicon or a suicide, -overlies insulating layer 26 and makes contact with N + region 14 and is connected to other circuitry, such as signal utilization circuitry 34 which may be formed on substrate 10.
  • Another conductive layer 32 overlies insulating layer 26 and makes contact with N + region 18 and P + region 20. Conductive layer 30 is also connected to a bond pad 36 for connection to external circuitry. The presence of N" well 12 under contact surface 28 serves to reduce the effect of aluminum penetration which can occur at high current stress levels.
  • Conductive layer 32 is connected to a source of a reference potential.
  • Fig. 2 shows one possible arrangement, in which an integrated circuit 21 is connected between a first terminal 23 and a second terminal 25.
  • terminal 23 is a supply terminal for a voltage of first polarity and terminal 25 is shown as a supply terminal for a source of reference potential.
  • terminal 23 can be an input or output signal terminal rather than a supply terminal.
  • a protection circuit 27 in accordance with the invention is connected between terminals 23 and 25, that is, in parallel with integrated circuit 21. Protection circuit 27 thereby protects integrated circuit 21, by turning on in response to transient voltages to conduct transient energy to a source of reference potential, ground in this example.
  • Fig. 3 shows a schematic equivalent of the circuit formed by the structure of Fig. 1.
  • Resistor Rw is formed substantially by the resistance of the portion of well 12 between N + region 14 and N + region 16.
  • the collector of NPN transistor Ql is formed by N + region 16, and its emitter is formed by N + region 18.
  • the base region of transistor Ql is essentially formed by P + region 24.
  • a resistor Rs, which is connected between the base and emitter electrodes of transistor Ql is formed substantially by the portion of substrate 10 between P + layer 24 and P + region 20 which is connected to N + region 18.
  • Diode Dl is formed by well 12 and substrate 10, contacted by region 20. In its unstressed condition, that is, before ever having been subjected to high voltage stress, the device of Figs.
  • P + layer 22 changes the breakdown voltage between layer 22 and N + regions 14 and 16.
  • P + layer 22 now forms the emitter electrode of a new PNP bipolar transistor, Q2 in Fig. 5.
  • P + layer 22 also forms the anode of a Zener diode, Zl in Fig. 6, with the cathode thereof being formed by N+ region 14.
  • Zener diode Zl is in series with the emitter electrode of transistor Q2.
  • N " well 12 forms the base electrode of transistor Q2, and the substrate 10 forms the collector electrode.
  • Fig. 6 A typical characteristic for the post stressed device is shown in Fig. 7, from which the "snap-back" character of the IV characteristic will be apparent.
  • the device continues to provide a desirable characteristic for providing protection against high level transients.
  • the post stressed behavior is characteristically different from the pre-stressed behavior, and thereby provides a clear indication that the device has been subjected to a high level transient. Such indication can be a very useful analytical tool in engineering diagnostic analysis.
  • Figs. 5 and 6 has been described in terms of a modification of the structure of Figs. 1 and 3, it should be understood that the invention is not so limited.
  • a P + region can be introduced during fabrication in place of implanted P + layer 22.
  • the resulting device then corresponds to the device of Figs. 5 and 6, except that it no longer has utility as an analytical tool.
  • the devices of the invention can be fabricated utilizing standard photolithographic and etching steps for definition and ion implantation for forming the doped regions.
  • a silicon substrate is used with, for example, boron as a P type dopant and phosphorus as an N type dopant, other suitable materials may be used.
  • Modifications of the various embodiments of the invention may occur to one skilled in the art. For example, while the exemplary embodiment has been described in terms of particular conductivity types, converse conductivity types may be used so long as the relative conductivity types remain the same. Such and like modifications are intended to be within the spirit and scope of the invention, and the appended claims.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

Une structure de protection comprend un substrat semiconducteur (10) d'un premier type de conductivité avec une région (12) d'un deuxième type de conductivité agencée à la surface du substrat. La région du deuxième type de conductivité contient des première et deuxième régions (14 et 16) du deuxième type de conductivité, une troisième région (18) du deuxième type de conductivité adjacente à la surface du substrat, et une quatrième région (20) du premier type de conductivité adjacente à la surface du substrat et à la troisième région. Une zone de champ peu profonde (22) s'étend sur une certaine distance dans la région du deuxième type de conductivité entre les première et deuxième régions. Un premier contact électrique (28) est situé sur la surface de la première région et un deuxième contact électrique (28) est situé sur les troisième et quatrième régions. Un organe sensible aux phénomènes transitoires réagit à un phénomène transitoire de haute tension appliqué entre la borne et le substrat, formant un transistor avec une électrode émettrice dans la couche de champ, une électrode de base dans la région du deuxième type de conductivité et une électrode collectrice dans le substrat. Une diode de claquage par avalanche est formée entre l'émetteur du transistor et le contact.
PCT/US1990/002609 1989-05-17 1990-05-14 Structure de protection contre des decharges electrostatiques a contrainte alterable de tension WO1990014690A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB898911360A GB8911360D0 (en) 1989-05-17 1989-05-17 Electronic charge protection devices
GB8911360.9 1989-05-17
US516,497 1990-05-04
US07/516,497 US5010380A (en) 1989-05-17 1990-05-04 Voltage stress alterable ESD protection structure

Publications (1)

Publication Number Publication Date
WO1990014690A1 true WO1990014690A1 (fr) 1990-11-29

Family

ID=26295364

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1990/002609 WO1990014690A1 (fr) 1989-05-17 1990-05-14 Structure de protection contre des decharges electrostatiques a contrainte alterable de tension

Country Status (3)

Country Link
EP (1) EP0472647A4 (fr)
JP (1) JP2505653B2 (fr)
WO (1) WO1990014690A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0699346A1 (fr) * 1993-05-21 1996-03-06 Sarnoff Corporation Circuit redresseur au silicium commande pour la protection de circuits integres contre les decharges electrostatiques
EP0723706A1 (fr) * 1993-10-15 1996-07-31 Intel Corporation Circuit de protection contre les decharges electriques
EP0776539A1 (fr) * 1994-08-17 1997-06-04 Sarnoff Corporation Curcuit de protection electrostatique
CN102130184A (zh) * 2010-12-22 2011-07-20 东南大学 一种应用于高压静电保护的高鲁棒性反偏二极管

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS523389A (en) * 1975-06-27 1977-01-11 Toshiba Corp Field effect semiconductor device
JPS56165356A (en) * 1980-05-26 1981-12-18 Hitachi Ltd Mos semiconductor device
JPS5843557A (ja) * 1981-09-08 1983-03-14 Toshiba Corp 半導体装置
JPS58142578A (ja) * 1982-02-19 1983-08-24 Hitachi Ltd 半導体装置
JPS5980973A (ja) * 1983-09-02 1984-05-10 Hitachi Ltd ゲ−ト保護回路
JPS6364358A (ja) * 1986-09-05 1988-03-22 Nissan Motor Co Ltd Ｃｍｏｓ半導体装置
US4928157A (en) * 1988-04-08 1990-05-22 Kabushiki Kaisha Toshiba Protection diode structure

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3422132C1 (de) * 1984-06-14 1986-01-09 Texas Instruments Deutschland Gmbh, 8050 Freising Schutzschaltungsanordnung
US4633283A (en) * 1985-03-11 1986-12-30 Rca Corporation Circuit and structure for protecting integrated circuits from destructive transient voltages
JPH0523389A (ja) * 1991-07-19 1993-02-02 Onoda Cement Co Ltd 医科用または歯科用硬化性組成物

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS523389A (en) * 1975-06-27 1977-01-11 Toshiba Corp Field effect semiconductor device
JPS56165356A (en) * 1980-05-26 1981-12-18 Hitachi Ltd Mos semiconductor device
JPS5843557A (ja) * 1981-09-08 1983-03-14 Toshiba Corp 半導体装置
JPS58142578A (ja) * 1982-02-19 1983-08-24 Hitachi Ltd 半導体装置
JPS5980973A (ja) * 1983-09-02 1984-05-10 Hitachi Ltd ゲ−ト保護回路
JPS6364358A (ja) * 1986-09-05 1988-03-22 Nissan Motor Co Ltd Ｃｍｏｓ半導体装置
US4928157A (en) * 1988-04-08 1990-05-22 Kabushiki Kaisha Toshiba Protection diode structure

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP0472647A4 *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0699346A1 (fr) * 1993-05-21 1996-03-06 Sarnoff Corporation Circuit redresseur au silicium commande pour la protection de circuits integres contre les decharges electrostatiques
EP0699346A4 (fr) * 1993-05-21 1997-05-07 Sarnoff David Res Center Circuit redresseur au silicium commande pour la protection de circuits integres contre les decharges electrostatiques
EP0723706A1 (fr) * 1993-10-15 1996-07-31 Intel Corporation Circuit de protection contre les decharges electriques
EP0723706A4 (fr) * 1993-10-15 1997-01-08 Intel Corp Circuit de protection contre les decharges electriques
EP0776539A1 (fr) * 1994-08-17 1997-06-04 Sarnoff Corporation Curcuit de protection electrostatique
EP0776539A4 (fr) * 1994-08-17 1998-11-25 Sarnoff David Res Center Curcuit de protection electrostatique
CN102130184A (zh) * 2010-12-22 2011-07-20 东南大学 一种应用于高压静电保护的高鲁棒性反偏二极管

Also Published As

Publication number Publication date
EP0472647A4 (en) 1992-12-23
EP0472647A1 (fr) 1992-03-04
JPH05505061A (ja) 1993-07-29
JP2505653B2 (ja) 1996-06-12

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