EP0472647A4 - Voltage stress alterable esd protection structure - Google Patents
Voltage stress alterable esd protection structureInfo
- Publication number
- EP0472647A4 EP0472647A4 EP19900908837 EP90908837A EP0472647A4 EP 0472647 A4 EP0472647 A4 EP 0472647A4 EP 19900908837 EP19900908837 EP 19900908837 EP 90908837 A EP90908837 A EP 90908837A EP 0472647 A4 EP0472647 A4 EP 0472647A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- region
- conductivity type
- substrate
- transistor
- regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
Definitions
- the present invention relates to electrical protection devices, and more particularly to devices providing protection for monolithic integrated circuits against relatively large voltage transients.
- Integrated circuits are incorporated in many types of electrical equipment. Such integrated circuits are generally vulnerable to damage from high voltage transients.
- high voltage transients may have positive and/or negative peak levels of 100 volts or more and may have a duration of several microseconds.
- High voltage electrostatic discharge (ESD) transients can also result from a user becoming electrostatically charged, for example, by friction or by induction and touching equipment controls.
- Protection devices applicable to the protection of integrated circuits from damage that would otherwise result from a high voltage transient are known in the art. Such devices are described in, for example, Avery, U.S. Patent No.
- a protection device be able to handle transients associated with relatively large energy without itself being destroyed or having its protective capability significantly impaired. Furthermore, it is desirable that the protective device provide an indication of having been subjected to a large voltage transient.
- a semiconductor protection circuit comprises a semiconductor substrate of a first conductivity type, a region of second conductivity type in the substrate at the surface thereof.
- the region of second conductivity type has disposed therein first and second regions of the second conductivity type, a third region of the first conductivity type at the surface of the substrate, and a fourth region of the second conductivity type at the surface of the substrate adjacent the third region.
- a shallow field region of first conductivity type extends a distance from the surface into the region of second conductivity type and extends between the first and second regions.
- a first electrical contact overlies the first region of the second conductivity type.
- a second electrical contact overlies the third and fourth regions.
- a transient-responsive means is responsive to a high voltage transient being applied between a terminal of an integrated circuit to be protected and a source of reference potential for forming a transistor of second polarity type of second polarity type having an emitter electrode formed in the field layer, a base electrode formed in the region of second conductivity type, and a collector electrode formed in the semiconductor substrate, and an avalanche breakdown diode formed between the emitter of the transistor and the electrode contact.
- a semiconductor protection circuit comprises a semiconductor substrate of a first conductivity type, the substrate having adjacent a surface thereof a relatively shallow, relatively high conductivity, field layer of the first conductivity type.
- a region of second conductivity type is in the substrate at the surface and has disposed therein first and second regions of the second conductivity type.
- a further region of first conductivity type is in the substrate at the surface.
- a further region of the second conductivity type is in the substrate at the surface of the substrate adjacent the further region of the first conductivity type.
- a terminal overlies the surface of the further region of the second conductivity type.
- a bipolar transistor of a particular polarity type e.g. NPN or PNP
- a transient-responsive structure is responsive to a high voltage transient between the terminal and the substrate which alters the doping profile thereby forming a transistor of second conductivity polarity type having an emitter electrode comprising the field layer, a base electrode comprising the region of second conductivity type, a collector electrode formed by the substrate, and an avalanche breakdown diode comprising the emitter of the transistor of second conductivity type and the terminal.
- a first transistor of a first polarity type has a collector electrode resistively coupled to a terminal of an integrated circuit to be protected against a high voltage transient, an emitter electrode coupled to a point of reference potential, and a base electrode coupled to the point of reference potential.
- a transient- responsive arrangement is responsive to an occurrence of a high voltage transient for thereupon altering the doping profile and forming in the integrated circuit a second transistor of second polarity type having an emitter electrode coupled to the terminal, a collector electrode coupled to the base electrode of the first transistor, and a base electrode coupled to the collector electrode of the first transistor.
- Fig. 1 shows a cross-section, not to scale, of a protection device in accordance with the invention
- Fig. 2 shows a schematic of exemplary connections of a protection circuit and an integrated circuit of the invention
- Fig. 3 shows a schematic circuit diagram of a protection device corresponding to the device of Fig. 1 ;
- Fig. 4 shows a graph of an electrical characteristic of the device of Figs. 1 and 3
- Fig. 5 shows a cross-section, not to scale, of a protection device of another embodiment of the invention
- Fig. 6 shows a schematic of a protection device corresponding to the device of Fig. 4 and
- Fig. 7 shows a graph of a characteristic of the device of Figs. 5 and 6
- a circuit is formed in a semiconductor substrate 10 of P type silicon.
- An N" well 12 which is relatively lightly doped region, typically 10 4 - l ⁇ l -5/cc, and of relatively low conductivity, is disposed in substrate 10.
- a first N + region 14 which is relatively heavily doped region, typically l ⁇ l 8/cc, and of relatively high conductivity, is disposed within N" well 12.
- a second N + region 16 is also formed in the N ⁇ well 12 and extends beyond its border into the substrate 10.
- a third N + region 18 is disposed in substrate 10 outside of the borders of N- well 12.
- the N" well 12 and the N+ regions 14, 16, and 18 are typically formed simultaneously in the same processing step.
- a first P + region 20 which is relatively heavily doped and of relatively high conductivity is in substrate 10 adjacent the third N + region 18 and is preferably in contact therewith so as to form a P + N + junction therewith.
- N + region 18 be close to first P + region 20.
- P + implant layers 22 and 24 are commonly referred to in the art as field implant regions. They are generally utilized to increase the inversion voltage of the substrate surface, thereby preventing the formation of spurious conduction channels along the surface which may otherwise result from electrical charge trapped in the overlying layers.
- An insulating layer 26, such as a silicon oxide, overlies the surface of substrate 10.
- Insulating layer 26 contains a P type dopant such as boron. Openings are formed in insulating layer 26 over regions 14, 18, and 20 in order to allow the making of electrical contact thereto at a contact surface 28 thereof.
- a conductive layer 30, which may for example be aluminum, molybdenum, polysilicon or a suicide, -overlies insulating layer 26 and makes contact with N + region 14 and is connected to other circuitry, such as signal utilization circuitry 34 which may be formed on substrate 10.
- Another conductive layer 32 overlies insulating layer 26 and makes contact with N + region 18 and P + region 20. Conductive layer 30 is also connected to a bond pad 36 for connection to external circuitry. The presence of N" well 12 under contact surface 28 serves to reduce the effect of aluminum penetration which can occur at high current stress levels.
- Conductive layer 32 is connected to a source of a reference potential.
- Fig. 2 shows one possible arrangement, in which an integrated circuit 21 is connected between a first terminal 23 and a second terminal 25.
- terminal 23 is a supply terminal for a voltage of first polarity and terminal 25 is shown as a supply terminal for a source of reference potential.
- terminal 23 can be an input or output signal terminal rather than a supply terminal.
- a protection circuit 27 in accordance with the invention is connected between terminals 23 and 25, that is, in parallel with integrated circuit 21. Protection circuit 27 thereby protects integrated circuit 21, by turning on in response to transient voltages to conduct transient energy to a source of reference potential, ground in this example.
- Fig. 3 shows a schematic equivalent of the circuit formed by the structure of Fig. 1.
- Resistor Rw is formed substantially by the resistance of the portion of well 12 between N + region 14 and N + region 16.
- the collector of NPN transistor Ql is formed by N + region 16, and its emitter is formed by N + region 18.
- the base region of transistor Ql is essentially formed by P + region 24.
- a resistor Rs, which is connected between the base and emitter electrodes of transistor Ql is formed substantially by the portion of substrate 10 between P + layer 24 and P + region 20 which is connected to N + region 18.
- Diode Dl is formed by well 12 and substrate 10, contacted by region 20. In its unstressed condition, that is, before ever having been subjected to high voltage stress, the device of Figs.
- P + layer 22 changes the breakdown voltage between layer 22 and N + regions 14 and 16.
- P + layer 22 now forms the emitter electrode of a new PNP bipolar transistor, Q2 in Fig. 5.
- P + layer 22 also forms the anode of a Zener diode, Zl in Fig. 6, with the cathode thereof being formed by N+ region 14.
- Zener diode Zl is in series with the emitter electrode of transistor Q2.
- N " well 12 forms the base electrode of transistor Q2, and the substrate 10 forms the collector electrode.
- Fig. 6 A typical characteristic for the post stressed device is shown in Fig. 7, from which the "snap-back" character of the IV characteristic will be apparent.
- the device continues to provide a desirable characteristic for providing protection against high level transients.
- the post stressed behavior is characteristically different from the pre-stressed behavior, and thereby provides a clear indication that the device has been subjected to a high level transient. Such indication can be a very useful analytical tool in engineering diagnostic analysis.
- Figs. 5 and 6 has been described in terms of a modification of the structure of Figs. 1 and 3, it should be understood that the invention is not so limited.
- a P + region can be introduced during fabrication in place of implanted P + layer 22.
- the resulting device then corresponds to the device of Figs. 5 and 6, except that it no longer has utility as an analytical tool.
- the devices of the invention can be fabricated utilizing standard photolithographic and etching steps for definition and ion implantation for forming the doped regions.
- a silicon substrate is used with, for example, boron as a P type dopant and phosphorus as an N type dopant, other suitable materials may be used.
- Modifications of the various embodiments of the invention may occur to one skilled in the art. For example, while the exemplary embodiment has been described in terms of particular conductivity types, converse conductivity types may be used so long as the relative conductivity types remain the same. Such and like modifications are intended to be within the spirit and scope of the invention, and the appended claims.
Abstract
Description
Claims
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB898911360A GB8911360D0 (en) | 1989-05-17 | 1989-05-17 | Electronic charge protection devices |
GB8911360 | 1989-05-17 | ||
US07/516,497 US5010380A (en) | 1989-05-17 | 1990-05-04 | Voltage stress alterable ESD protection structure |
US516497 | 1990-05-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0472647A1 EP0472647A1 (en) | 1992-03-04 |
EP0472647A4 true EP0472647A4 (en) | 1992-12-23 |
Family
ID=26295364
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19900908837 Ceased EP0472647A4 (en) | 1989-05-17 | 1990-05-14 | Voltage stress alterable esd protection structure |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0472647A4 (en) |
JP (1) | JP2505653B2 (en) |
WO (1) | WO1990014690A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5343053A (en) * | 1993-05-21 | 1994-08-30 | David Sarnoff Research Center Inc. | SCR electrostatic discharge protection for integrated circuits |
US5430595A (en) * | 1993-10-15 | 1995-07-04 | Intel Corporation | Electrostatic discharge protection circuit |
US5600525A (en) * | 1994-08-17 | 1997-02-04 | David Sarnoff Research Center Inc | ESD protection circuit for integrated circuit |
CN102130184B (en) * | 2010-12-22 | 2012-10-10 | 东南大学 | High-robustness back biased diode applied to high-voltage static protection |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4633283A (en) * | 1985-03-11 | 1986-12-30 | Rca Corporation | Circuit and structure for protecting integrated circuits from destructive transient voltages |
JPH0523389A (en) * | 1991-07-19 | 1993-02-02 | Onoda Cement Co Ltd | Medical or dental curable composition |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS523389A (en) * | 1975-06-27 | 1977-01-11 | Toshiba Corp | Field effect semiconductor device |
JPS56165356A (en) * | 1980-05-26 | 1981-12-18 | Hitachi Ltd | Mos semiconductor device |
JPS5843557A (en) * | 1981-09-08 | 1983-03-14 | Toshiba Corp | Semiconductor device |
JPS58142578A (en) * | 1982-02-19 | 1983-08-24 | Hitachi Ltd | Semiconductor device |
JPS5980973A (en) * | 1983-09-02 | 1984-05-10 | Hitachi Ltd | Gate protective circuit |
DE3422132C1 (en) * | 1984-06-14 | 1986-01-09 | Texas Instruments Deutschland Gmbh, 8050 Freising | Protective circuit arrangement |
JPS6364358A (en) * | 1986-09-05 | 1988-03-22 | Nissan Motor Co Ltd | Cmos semiconductor device |
JPH0716005B2 (en) * | 1988-04-08 | 1995-02-22 | 株式会社東芝 | Semiconductor device |
-
1990
- 1990-05-14 EP EP19900908837 patent/EP0472647A4/en not_active Ceased
- 1990-05-14 JP JP2508210A patent/JP2505653B2/en not_active Expired - Fee Related
- 1990-05-14 WO PCT/US1990/002609 patent/WO1990014690A1/en not_active Application Discontinuation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4633283A (en) * | 1985-03-11 | 1986-12-30 | Rca Corporation | Circuit and structure for protecting integrated circuits from destructive transient voltages |
JPH0523389A (en) * | 1991-07-19 | 1993-02-02 | Onoda Cement Co Ltd | Medical or dental curable composition |
Non-Patent Citations (1)
Title |
---|
See also references of WO9014690A1 * |
Also Published As
Publication number | Publication date |
---|---|
JPH05505061A (en) | 1993-07-29 |
EP0472647A1 (en) | 1992-03-04 |
WO1990014690A1 (en) | 1990-11-29 |
JP2505653B2 (en) | 1996-06-12 |
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Legal Events
Date | Code | Title | Description |
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PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
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Owner name: SHARP CORPORATION Owner name: DAVID SARNOFF RESEARCH CENTER, INC. |
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Owner name: SARNOFF CORPORATION Owner name: SHARP CORPORATION |
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STAA | Information on the status of an ep patent application or granted ep patent |
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18R | Application refused |
Effective date: 19990719 |