WO1990011614A1 - Procede d'exposition a un faisceau charge, installation relative, diaphragme d'ouverture et procede de production de celui-ci - Google Patents

Procede d'exposition a un faisceau charge, installation relative, diaphragme d'ouverture et procede de production de celui-ci Download PDF

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Publication number
WO1990011614A1
WO1990011614A1 PCT/JP1990/000388 JP9000388W WO9011614A1 WO 1990011614 A1 WO1990011614 A1 WO 1990011614A1 JP 9000388 W JP9000388 W JP 9000388W WO 9011614 A1 WO9011614 A1 WO 9011614A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
film region
exposure
charged beam
pattern
Prior art date
Application number
PCT/JP1990/000388
Other languages
English (en)
Japanese (ja)
Inventor
Hiroaki Wakabayashi
Yoshinori Nakayama
Fumio Murai
Shinji Okazaki
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to JP2504990A priority Critical patent/JP2945471B2/ja
Priority to DE4090437T priority patent/DE4090437T1/de
Priority to US07/613,746 priority patent/US5334845A/en
Publication of WO1990011614A1 publication Critical patent/WO1990011614A1/fr

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
    • H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
    • H01J37/3174—Particle-beam lithography, e.g. electron beam lithography
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/30—Electron or ion beam tubes for processing objects
    • H01J2237/317—Processing objects on a microscale
    • H01J2237/3175—Lithography
    • H01J2237/31776—Shaped beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/30—Electron or ion beam tubes for processing objects
    • H01J2237/317—Processing objects on a microscale
    • H01J2237/3175—Lithography
    • H01J2237/31777—Lithography by projection
    • H01J2237/31788—Lithography by projection through mask

Definitions

  • the present invention relates to a charged beam exposure method and a charged beam exposure apparatus that use a batch exposure beam and have a high throughput.
  • the above-mentioned conventional technology has not been fully considered for the ⁇ -speed processing of light having a large number of patterns, which has a periodic reciprocal reflection such as the integrated electronic memory device.
  • One of the methods to solve this is the optical method shown in Japanese Patent Laid-Open No. 59 — ⁇ 6 9 1 3 ⁇ . There is. In this idea, in addition to the rectangular shape of the charged beam, it becomes part of the pattern 2 3'or the pattern 2 4 shown in Fig. 3. It is possible to prepare the shape.
  • the conventional aperture material is a metal material, it has poor workability, and it is actually difficult to process the aperture material. It is impossible to create a complicated shape of a level (abbreviated as M b DRAM).
  • the above-mentioned y target is achieved by performing pattern exposure without exposing the pattern in a certain area, and exposing it with a triangle. For this reason, it is necessary to consider all of the pattern shape and the array that are included in a certain area in the aperture, and create all of them.
  • a semiconductor single crystal particularly a silicon single crystal is used. Will be realized.
  • the purpose of the present invention is such a product with a large number of patterns. However, it is to provide an exposure method and an exposure apparatus that are high through-put and that can be maintained by this high through-pump regardless of the shot density per unit area. ..
  • Another object of the present invention is to provide an exposure method and an exposure apparatus that have a high processing speed regardless of whether the pattern is complex or not.
  • Another object of the present invention is to provide an aperture stop capable of being used in the above-mentioned exposure method and exposure apparatus and a manufacturing method thereof.
  • Fig. ⁇ (a) is a schematic view of the exposure apparatus of the present invention
  • Fig. (B) is a plan view showing a typical example of a 6 4 MDRAM aperture
  • 2 and 5 are 6 4 M b Figure showing the DRAM layer's gain layer pattern
  • Figure 3 shows the conventional method
  • Figure 4 shows the conventional variable molding.
  • Fig. 6 is a diagram explaining the pattern division by 3 ⁇ 4
  • Fig. 6 is a diagram showing the pattern of the 6 4 b DRA pattern
  • Fig. 7 is 6
  • Fig. 8 shows the exposure time per wafer of the wafer layer of the 4b DRAM pattern
  • Fig. 8 shows the relationship between the acceleration voltage (0) and the range (R) of the incident electron beam.
  • Figure 9 shows the cross-sectional view of the single crystal silicon wafer according to the present invention.
  • Figure 9 shows the cross section of the single crystal silicon wafer according to the present invention.
  • - ⁇ Is a figure showing the method of making a single crystal silicon aperture.
  • Figures 16 and 17 are the shot density of the 6 4 Mb DRAM pattern when exposed.
  • Fig. 18 shows the relationship between the and the throughput.
  • Fig. 18 is a plan view showing a typical example of an aperture for 2 56 Mb DRAM.
  • the target turning pattern 20 is set to an area 2 * 1 containing at least ⁇ or more turning elements, and is set in this area.
  • aperture means specifically, single crystal silicon aperture 1.
  • the other types of patterns are also processed into the above aperture 1 by the li3 ⁇ 4 treatment.
  • the film thickness of the single crystal silicon depends on the energy of the charged beam used for exposure, but the electron beam, which is the charged beam, is the lightest. Then, the range (R) corresponding to the accelerating voltage can be set and the silicon film thickness can be set as well. A preferable thickness is 15 m to 20 m.
  • the patterning of this silicon film is such that the sub-micron level microfabrication is possible by dry etching, and the above-mentioned area 2 1 is the minimum machining dimension.
  • the charged beam generating means that is, the charged beam emitted from the beam source 10 passes through the first rectangular aperture 11.
  • the deflector 1 3 as the control means is used.
  • the beam is shaped into a pattern and the beam is reflected by the deflection deflector 18 which is a control means.
  • the lens 15 and the objective lens 1 6 form a reduced image on the object to be processed, which is the web 19.
  • the wafer resist is provided on the wafer 1 9.
  • the desired pattern can be obtained by repeating this by moving back and forth by ⁇ n the number of pitches and repeating it repeatedly. 20 is obtained.
  • the number of shots is obtained by dividing the total rest area of the notebook by the area of the area created in aperture 1 and the complexity of the pattern shape. Completely independent of Therefore, the number of shots can be significantly reduced compared to the conventional one.
  • the time required for exposure is determined by the product of the exposure time of 1-third and the electrostatic wait time of electron optics, and the total number of shots required for the exposure of the entire pattern. Be touched.
  • Example 1 for exposure of 6 4 Mb DRAM pattern with minimum processing size of 0.3 m To explain o
  • reference numeral 1 is the second forming aperture
  • 2 and 6 are the aperture layers of the gear layer
  • 3 and 5 are the apertures. 4 for a rectangular pattern
  • 8 for a contact layer aperture pattern
  • 9 for a 2 5 6 Mb DRAM gate pattern aperture pattern.
  • 10 is the 0 charged beam source
  • 11 is the ⁇ shaping aperture
  • 1 2 is the ⁇ shaping lens
  • 1 3 is the shaping deflector
  • 14 is the 2nd shaping.
  • Lens 15 is a reduction lens, 1 6 is an objective lens, 17 is an unfocused lens, 1 8 is an auxiliary lens, 1 8 is an auxiliary lens, 1 9 is a wafer, and 20 is 6 4 Mb DRAM gate layer pattern b, 2 1 for 2 imx 2 m area, 2 2 for 4 ⁇ m x 4 m area, 2 3 and 2 4 for wafer pattern , 2 5 is a 6 4 Mb DRAM contact layer pattern, 2 6 is a ( ⁇ 0 0) silicon substrate, and 2 6 'is a silicon thin film,
  • 2 7 is a silicon dioxide film
  • 2 8 is a gold thin film
  • 2 9 is a dielectric layer of 0, 30 is an open pattern
  • 3 1 is a backside open pattern
  • 3 2 , 3 2 ' is a silicon nitride film
  • 3 3 is a resin
  • 3 4 shows the silicon thin film part, respectively.
  • the pattern shown in Fig. 2 is the switch of the switching M ⁇ S standard transistor that constitutes the memory cell of 64 Mb ⁇ RAM. It is Here, a 2 m x 2 m area 2 1 Assuming that, it is possible to incorporate a pattern element of 2 bits. Since the reduction ratio of the electron beam writer shown in Fig. ⁇ is 25 minutes ⁇ , the pattern shape of the above two bits and its arrangement are multiplied by 25 times to obtain the pattern. I made it on Ya 1. Here, the minimum dimension on the aperture is 7.5 m, and because it has a complicated shape including diagonal lines, it has excellent micro-fabrication. We processed the excellent silicon single crystal as a specialty material.
  • the structural diagram of this aperture is shown in Figs. 1 and 9, Fig. 1 (b) is a plan view of the aperture, and 9 is a sectional view of the aperture.
  • the reference numeral 2 in Fig. 1 (b) is the opening for the employment of employment.
  • 3 is the wiring layer
  • 7 is the opening for exposing the area of 4 m X 4 m of the wiring ⁇ ) ' ⁇ ]
  • 4 is for the wiring connection hole (contact hole).
  • the opening ⁇ 8 is the opening for the contact hole of the portion where the Sd position is different
  • the reference numerals 5 and 9 are the openings for the aluminum wiring and 5 is 2 W m. It corresponds to X 2 m and 9 corresponds to 4 m X 4 m.
  • Reference numeral 4 4 is a rectangular opening similar to the conventional one, which is used for a large area.
  • the first shaded area (b) is the opening.
  • the square line that faces each opening indicates the area (2 u 1 ⁇ 2 1 ⁇ or 4 1 ⁇ 4 111) corresponding to the object to be exposed.
  • the openings 2, 3, 4 and 5 in Fig. (B) (b) are the minimum repeating units according to the present invention. These openings are the units that can expose a complete pattern simply by exposing repeatedly. Based on the results shown in Fig. 8, the thickness of the silicon thin film part can be 20 m in the case of the electron beam source 1 with an accelerating voltage of 50 kV used this time. For the patterning, using the dry etching, it was possible to machine with a dimensional accuracy of 0.5 m or less. I will describe how to create this part.
  • a silicon substrate a bonded silicon substrate including a silicon dioxide film 27 inside the surface 20 / m from the surface, or Is a thin film part 2 6 ′, when a silicon substrate having a high-concentration layer 29 in which ions such as fluorine are implanted from the surface to 20 ⁇ m is used.
  • a silicon substrate having a high-concentration layer 29 in which ions such as fluorine are implanted from the surface to 20 ⁇ m is used.
  • Figure ⁇ 4 shows the process of making a bonded substrate
  • Figure ⁇ 5 shows the process of making a wafer with an ion-implanted substrate.
  • the etching stops at the silicon dioxide film 27 or the ion-implanted film 29. Therefore, it is possible to easily control the film thickness of the silicon thin film portions 26 'and 29.
  • the oxide film 27 is finally removed with hydrofluoric acid as shown in Fig. 14 (e). In both cases, the same as in Fig. 13
  • the patterns other than the Ge layer are included in the surface layer that shines like a sunbeam and the rectangular pattern for variable molding that has been used in the past.
  • the lanes 4 and 4 were also created in the same aperture 1.
  • a pattern 2 which is one of the patterns of this patcher 1 was selected by the deflector 13 and exposure was performed on the wafer I 9.
  • the pattern of 1 shot using this method is equivalent to the 20 shot of the conventional variable molding method shown in Fig. 4. .. Therefore, it was possible to reduce the number of memory units in the memory area to 20 minutes compared to the conventional model.
  • the pattern shape and its array included in the 4 x 4 Aim area of the Mb DRAM pattern are then multiplied by 25 to create all layers and rectangular patterns. It was The gate layer pattern 6 was selected by the deflector 1 3 and exposure was performed. As shown in Fig. 7, the exposure time in the case of exposure of 8 times or ⁇ 0 0 chips is 3 hours or more h> with the conventional variable molding method. However, with the exposure according to the present invention, the entire chip could be exposed in 1.5 minutes.
  • the second wafer was exposed with a different contact heater from the above-mentioned gate layer.
  • Contact layer Since the pattern 25 (Fig. 1 8) has already been created in the aperture 1, the pattern cannot be changed by the deflector 13 without changing the aperture.
  • Select option 8 This pattern is an example of the simplest pattern. With this pattern, in the case of conventional variable molding, one pattern can be used to expose one pattern. Since this pattern has ⁇ chips and 3.2 ⁇ 10 ′ patterns, the exposure by the conventional method has 1 chip only for the memory area. The total number of shots is 3.2 x
  • Fig. 6 there are 6 shot patterns in the 4 x 4 m area 2 22 according to the conventional technique, and therefore, according to the method of the present invention.
  • the total number of shots per memory chip in the memory area is the same as the total number of shots during the exposure of the gate layer 5.3 X 10 ° It is a shot.
  • the exposure time in the case of wafer exposure and ⁇ 0 0 chip exposure is 7.5 minutes in the case of the conventional variable molding method, but it is the actual time. With the exposure according to the invention, the entire chip could be exposed in ⁇ .5 minutes.
  • the pattern is obtained by specializing the aperture pattern (opening) for the target pattern layer. It is possible to realize high throughput without depending on the density.
  • the resistance sensitivity (S) is ⁇ CZ CTJ 2
  • the electron beam current density (J) is ⁇ 0 A ⁇ 2
  • the waiting time (t) of the electron optics is 100 ns
  • Figures 16 and 17 show the throughput (t 0 ) of 160 s when the overhead was set, and the sloping curve when only the memory part was exposed was obtained.
  • the horizontal axis shows the exposure light density
  • the vertical axis shows the loop density, and shows the adjusted results of the influence on the loop when each parameter changes. It is.
  • Figure 16 (a) shows the resister sensitivity (S) changed to 0.5, 1, and 2.5 C 2
  • Figure 16 (b) shows the current density (J). 2 0, 1 0,
  • the ones that have the largest effect on the throughput are the ones that are the density of the shots, that is, the total number of shots (N).
  • N the total number of shots
  • Reference numeral 3 5 is an aperture layer aperture for 2 5 6 M b D R A M
  • reference number 3 6 is an aperture aperture for a 2 5 6 M b D R AM support layer
  • Reference numeral 3 7 is a contact layer-purpose patcher of 2 5 6 M b D R A M,
  • Reference numeral 3 8 is a 2 5 6 M b D R A M aluminum aperture aperture and reference numeral 3 9 is a variable shaping rectangular aperture,
  • Reference numeral 40 indicates a 4 m x 4 m corresponding area on the wafer.
  • the throughput of the 2 5 6 Mb DRAM is about the same as that of the 6 4 M b DRAM. It was
  • the loop density does not change due to the pattern density (that is, the complexity of the pattern).
  • a good throughput is carried around. Therefore, when exposing a highly integrated device, not only the performance is maintained in any layer, but also the throughput is high in any generation. Has the effect of being maintained.
  • the above-mentioned characteristics are not so good that the area that can be exposed at one time is large and that the effect is also negligible.
  • the present invention provides a method for manufacturing a semiconductor device, in particular, a highly integrated, dynamic random access memory, and a status random access memory. , And is useful in manufacturing various types of logic, icons, and the like. It is industrially applicable in that it can improve the throughput, which is the biggest drawback of the electron beam exposure method, and can use the electron beam exposure method in actual production. There is a big thing.

Abstract

Procédé d'exposition à un faisceau d'électrons et dispositifs relatifs dans un processus de production de circuits intégrés à très grande échelle. Jusqu'à présent, on a effectué l'exposition par étapes séparées. La présente invention utilise un diaphragme d'ouverture dont l'agencement dans une zone déterminée présente une configuration à film mince de silicium monocristallin, et l'exposition s'effectue en une seule étape pour une zone déterminée. Selon l'invention, l'exposition est complétée en un nombre d'étapes quelques centaines de fois plus petit qu'auparavant, ce qui contribue à un accroissement considérable de la productivité. En outre, il n'y a virtuellement aucune différence dans le nombre d'étapes d'exposition, indépendamment de la complexité de la configuration, ce qui permet d'effectuer chaque processus en un laps de temps pratiquement constant.
PCT/JP1990/000388 1989-03-24 1990-03-23 Procede d'exposition a un faisceau charge, installation relative, diaphragme d'ouverture et procede de production de celui-ci WO1990011614A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2504990A JP2945471B2 (ja) 1989-03-24 1990-03-23 荷電ビーム用マスクおよびこれを用いた荷電ビーム露光方法および装置
DE4090437T DE4090437T1 (de) 1989-03-24 1990-03-23 Belichtungsverfahren und -vorrichtung mit einem Strahl geladener Teilchen sowie Aperturblende und Herstellverfahren einer solchen
US07/613,746 US5334845A (en) 1989-03-24 1990-03-23 Charged beam exposure method and apparatus as well as aperture stop and production method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1/70685 1989-03-24
JP7068589 1989-03-24

Publications (1)

Publication Number Publication Date
WO1990011614A1 true WO1990011614A1 (fr) 1990-10-04

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PCT/JP1990/000388 WO1990011614A1 (fr) 1989-03-24 1990-03-23 Procede d'exposition a un faisceau charge, installation relative, diaphragme d'ouverture et procede de production de celui-ci

Country Status (2)

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DE (1) DE4090437T1 (fr)
WO (1) WO1990011614A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6511048B1 (en) 1998-07-16 2003-01-28 Hitachi, Ltd. Electron beam lithography apparatus and pattern forming method
JP2016046385A (ja) * 2014-08-22 2016-04-04 株式会社ニューフレアテクノロジー アパーチャ部材製造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53144676A (en) * 1977-05-23 1978-12-16 Nippon Telegr & Teleph Corp <Ntt> Electron beam mask and production of the same
JPS5471992A (en) * 1977-11-18 1979-06-08 Cho Lsi Gijutsu Kenkyu Kumiai Electron beam shaping aperture mask
JPS55107780A (en) * 1979-02-07 1980-08-19 Hitachi Ltd Etching method
JPS5824009B2 (ja) * 1978-10-23 1983-05-18 日本電子株式会社 電子線露光装置
JPS6273713A (ja) * 1985-09-27 1987-04-04 Toshiba Corp 荷電ビ−ム照射装置
JPS63110635A (ja) * 1986-10-27 1988-05-16 Sharp Corp 電子ビ−ム描画装置用アパ−チヤ

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4213053A (en) * 1978-11-13 1980-07-15 International Business Machines Corporation Electron beam system with character projection capability
JPS62260322A (ja) * 1986-05-06 1987-11-12 Hitachi Ltd 可変成形型電子線描画装置
JPH06273713A (ja) * 1993-03-18 1994-09-30 Ricoh Co Ltd 画像投影装置および画像投影用画像形成装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53144676A (en) * 1977-05-23 1978-12-16 Nippon Telegr & Teleph Corp <Ntt> Electron beam mask and production of the same
JPS5471992A (en) * 1977-11-18 1979-06-08 Cho Lsi Gijutsu Kenkyu Kumiai Electron beam shaping aperture mask
JPS5824009B2 (ja) * 1978-10-23 1983-05-18 日本電子株式会社 電子線露光装置
JPS55107780A (en) * 1979-02-07 1980-08-19 Hitachi Ltd Etching method
JPS6273713A (ja) * 1985-09-27 1987-04-04 Toshiba Corp 荷電ビ−ム照射装置
JPS63110635A (ja) * 1986-10-27 1988-05-16 Sharp Corp 電子ビ−ム描画装置用アパ−チヤ

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6511048B1 (en) 1998-07-16 2003-01-28 Hitachi, Ltd. Electron beam lithography apparatus and pattern forming method
JP2016046385A (ja) * 2014-08-22 2016-04-04 株式会社ニューフレアテクノロジー アパーチャ部材製造方法

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