WO1989000313A1 - Perfectionnement relatif au transfert par identification rapide - Google Patents

Perfectionnement relatif au transfert par identification rapide Download PDF

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Publication number
WO1989000313A1
WO1989000313A1 PCT/US1988/002146 US8802146W WO8900313A1 WO 1989000313 A1 WO1989000313 A1 WO 1989000313A1 US 8802146 W US8802146 W US 8802146W WO 8900313 A1 WO8900313 A1 WO 8900313A1
Authority
WO
WIPO (PCT)
Prior art keywords
buffer
microprocessor
unit
controller
tag
Prior art date
Application number
PCT/US1988/002146
Other languages
English (en)
Inventor
Daniel W. Tortorelli
Nicholas M. Warner
Joseph Glider
Original Assignee
Unisys Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisys Corporation filed Critical Unisys Corporation
Publication of WO1989000313A1 publication Critical patent/WO1989000313A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device

Definitions

  • This disclosure relates to disk drive control means, and particularly to techniques for transferring instructions ("tags”) to and from such.
  • a drive microprocessor receiving and acknowledging command information is the limiting factor In the speed of transfer.
  • the microprocessor could be used with a faster basic clock speed; but a faster microprocessor clock reduces reliability by introducing more noise into the system.
  • the disclosed ⁇ rodime ⁇ t proposes solving this problem by establishing a special "low order tag" (tag 0A) with the format shown in FIG. 1A and proposes adding hardware to implement this tag by providing for the reception and temporary storage of the (three or four) parameters to be passed. Additional hardware would be required for the direct loading of the head address register (HAR) by the MPU.
  • tag 0A special "low order tag”
  • HAR head address register
  • FIG. 1 shows a block diagram of a logic block for controlling one actuator, e.g., of the type described aoove.
  • interface stage DINT is advised by the microprocessor DMPU that the controller CC is "ready" to input data.
  • the microprocessor DMPU is known to be relatively “slow” as compared with the controller CC, e.g. , it will take the order of 80 microseconds to validate all data bits, etc. , as known in the art. This forces the faster controller CC to either wait and waste valuable computer time, or else turn away from DINT* emporarily and divert to other tasks — in any event delays and complications result.
  • the. time involved in a "handshake" with the DMPU (that is, 80+usec. assumed) is relatively long and wasteful, since the CC is so fast (e.g., about 8 usec. ) .
  • the disclosed errixdi ⁇ eTt proposes modifying things so that there is essentially no wait when controller CC makes a data transfer to a drive unit — allowing it to transfer at maximum speed via a "fast tag buffer" FTB
  • FIG. 2 there are two data paths to each actuator so that either of the two controllers can communicate with either actuator by either of two paths — cf. two actuators per HDA or spindle; two HDAs or four independent actuators per box; and four boxes per 3682 disk drive: a total of 16 actuators and 16 associated controllers.
  • commands from a controller CC to a given actuator can involve “hardware tags” or “processor commands” (the MPU gets involved in the latter, e.g. , during a seek motion) .
  • processor commands the MPU gets involved in the latter, e.g. , during a seek motion
  • this buffer FTB allows controller CC to access the unit (DINT) any time, regardless of what the associated DMPU is doing, as long as the buffer FTB is "empty.” Further, once buffer FTB has been emptied, it may be re-filled with the next command from the controller.
  • a controller CC to send information to a given actuator (DINT) at any time and as fast as possible, also to spend a minimum time contacting this DINT — thus it can be redirected to other tasks without delay.
  • DINT actuator
  • This improvement obviously frees-up controllers and microprocessors, to do other work and operate with less restriction.
  • Buffered FTB may, for instance, comprise a four-byte
  • pipeline register chip (e.g., by AMD Corp.).
  • FIG. 1 is a schematic idealized block diagram o a control arrangement for a given disk drive actuator serving an associated disk stack;
  • FIG. 1A is an exemplary arrangement of command information ( -parameters) as used with a subject embodiment; while FIG. 1AA illustrates a like arrangeme for a 3-parameter embodiment; FIG. 2 schematically indicates control data between an exemplary string controller and a pair of actuators served thereby;
  • FIGS. 3A, 3B, and 4A, 4B, and 5 are block diagram details of respective DINT, DMPU, and DRWC units of the arrangement in FIG. 1;
  • FIG. 7 is an exemplary circuit implementation of a 3-parameter embodiment.
  • FIG. 7 schematically illustrates a fast tag buffer FTB and associated means constructed according to principles of this invention (implemented in the circuit of FIGS. 3A, 3B, and 6) .
  • This, and other means discussed herein, will generally be understood as constructed and operating as presently known in the art, except where otherwise specified. And, except as otherwise specified, all materials, methods and devices and apparatus herein will be understood as implemented by known expedients according to present good practice.
  • Tag Description (four parameter) :
  • the first parameter passed would be HAR bits (only four HAR bits are needed here; the remaining bits could be special, "tag-modified” bits as discussed below) .
  • the remaining three parameters would be the same as for a conventional "seek-to-target" (tag 1A).
  • the second parameter would be the high-order cylinder address (CAR high), SA track identification and sector window definition.
  • the third parameter would contain cylinder address low (CAR low).
  • the fourth parameter would contain the target sector information.
  • the special "tag-modified" bits in the first parameter change the meaning in execution of the tag; for example to indicate: 1. "Ignore HAR" (do seek and sector search but don't switch heads).
  • FIG. 7 shows a block diagram of our buffer FTB and associated counter BC and other exemplary hardware in a preferred embodiment.
  • buffer FTB may be viewed as a • "pipeline register” which is preferably configured as a "one byte-by-four" shift register.
  • Register FTB is used to receive and store the incoming parameters. Data is clocked-in by "tag valid”. The configuration can then be changed so that the MPU can read any one of the four registers in einy order.
  • the associated counter BC is used to count the number of parameters passed and to generate a "buffer full" signal which tells the' MPU that all four parameters have been transferred and to start processing the tag data.
  • Various MPU register bits are needed to allow the MPU to change "pipeline register” mode, to se ⁇ ect which register to read, and to detect status. Direct MPU loading of HAR would be required.
  • this arrangement in FIG. 7 would function as follows. Upon selection, parameters would be passed as with any conventional low-order tag. Parameters would be clocked-in (via “tag valid, " equals tag gate and no interface check). "Bus out” would be echoed to "bus in.” When the "buffer full” signal is generated, it will cause a "drive busy” status to be posted. The “buffer full” signal will also cause the MPU to proceed to execute the tag. At the appropriate time in the cycle, the MPU will reset the "buffer full” signal and post the current drive status.
  • the third parameter would contain the target sector information.
  • the special "tag-modified" bits in the first parameter change the meaning in execution of the tag; for example to indicate: 1. "Seek to Target” with window parameter.
  • a disk drive can receive new "seek” or “sector search” commands, while executing present commands — a capability not presently provided in the art.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Moving Of Head For Track Selection And Changing (AREA)

Abstract

Techniques permettant le transfert rapide de données entre une unité de commande multiple de disques (cf. contrôleur de chaine) et une pluralité de fichiers sur disques, chaque fichier comprenant un microprocesseur, une phase de commande lecture/écriture, une phase à asservissement et une unité d'interface adaptée pour communiquer avec l'unité de commande multiple. Une caractéristique principale réside dans le fait que l'unité d'interface est dotée d'un tampon d'identification rapide adapté pour procurer un stockage de données spécial et un potentiel de transfert rapide, et ainsi communiquer directement avec l'unité de commande multiple.
PCT/US1988/002146 1987-07-01 1988-06-27 Perfectionnement relatif au transfert par identification rapide WO1989000313A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US6838687A 1987-07-01 1987-07-01
US068,386 1987-07-01

Publications (1)

Publication Number Publication Date
WO1989000313A1 true WO1989000313A1 (fr) 1989-01-12

Family

ID=22082236

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1988/002146 WO1989000313A1 (fr) 1987-07-01 1988-06-27 Perfectionnement relatif au transfert par identification rapide

Country Status (3)

Country Link
EP (1) EP0321555A1 (fr)
JP (1) JPH01501661A (fr)
WO (1) WO1989000313A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0593174A2 (fr) * 1992-10-08 1994-04-20 International Business Machines Corporation DASD avec deux activateurs
EP0784272A1 (fr) * 1990-09-20 1997-07-16 Fujitsu Limited ContrÔleur d'entrée/sortie
US6286061B1 (en) 1998-06-02 2001-09-04 Philips Electronics North America Corporation System for applying a tag to a frame based on certain characteristics of the frame and transferring the frame as a function of the tag

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4183084A (en) * 1977-06-06 1980-01-08 Digital Equipment Corporation Secondary storage facility with serial transfer of control messages
EP0145594A2 (fr) * 1983-12-09 1985-06-19 Fujitsu Limited Système de commande de mémoire tampon
EP0165915A2 (fr) * 1984-06-21 1985-12-27 Cray Research, Inc. Système d'interface périphérique

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55112664A (en) * 1979-02-22 1980-08-30 Nec Corp Disc access time optimizing unit
JPS55143637A (en) * 1979-04-25 1980-11-10 Hitachi Denshi Ltd Data transfer unit
JPS59132027A (ja) * 1983-01-17 1984-07-30 Fujitsu Ltd 装置間制御方式

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4183084A (en) * 1977-06-06 1980-01-08 Digital Equipment Corporation Secondary storage facility with serial transfer of control messages
EP0145594A2 (fr) * 1983-12-09 1985-06-19 Fujitsu Limited Système de commande de mémoire tampon
EP0165915A2 (fr) * 1984-06-21 1985-12-27 Cray Research, Inc. Système d'interface périphérique

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
COMPON'81, 22nd Computer Society International Conference, 23-26 February 1981, San Francisco, CA (US) IEEE Computer Society D. Hopkins: "Eight inch Winchester disk system design considerations" pages 19-24 *
IBM Technical Disclosure Bulletin, vol. 21, no. 11, April 1979 (New York, US) E.W. Alcock et al.: "Disk adapter-system interface" pages 4628-4629 *
IBM Technical Disclosure Bulletin, vol. 24, no. 2, July 1981 (New York, US) W.A. Larson et al.: "Tape drive attachment support", pages 971-975 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0784272A1 (fr) * 1990-09-20 1997-07-16 Fujitsu Limited ContrÔleur d'entrée/sortie
US5826003A (en) * 1990-09-20 1998-10-20 Fujitsu Limited Input/output controller providing preventive maintenance information regarding a spare I/O unit
US6324655B1 (en) 1990-09-20 2001-11-27 Fujitsu Limited Input/output controller providing preventive maintenance information regarding a spare I/O unit
EP0593174A2 (fr) * 1992-10-08 1994-04-20 International Business Machines Corporation DASD avec deux activateurs
EP0593174A3 (en) * 1992-10-08 1996-09-04 Ibm Dual actuator dasd
US6286061B1 (en) 1998-06-02 2001-09-04 Philips Electronics North America Corporation System for applying a tag to a frame based on certain characteristics of the frame and transferring the frame as a function of the tag

Also Published As

Publication number Publication date
JPH01501661A (ja) 1989-06-08
EP0321555A1 (fr) 1989-06-28

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