Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
  • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

Definitions

• the disclosed invention relates to the provision of conductive paths between devices and a metallization layer or between metallization layers of integrated circuits, and is more particularly directed to the formation of electrically conductive plugs for interconnecting devices and metallization layers of integrated circuits.
• the devices or elements formed in the substrate are interconnected with metallic (e.g. , aluminum) leads which are typically formed by the sequential processes of masking and deposition.
• the processes of masking and deposition shall be referred to as metallization, and generally provides for a layer of metallization on top of a layer of insulating oxide or glass.
• the insulating oxide or glass on which the metal ⁇ lization is deposited generally includes openings or windows for the formation of (a) metallized contacts to silicon or polysilicon, or (b) metallized vias to another layer of metallization.
• the contact and via openings or windows must be selectively located for two and three layer metallization. Such selectivity is required due to photolithographic and deposition processing limitations.
• planariz- ing refers to smoothing the surface of an insulating layer prior to deposition of metal.
• the planarized surface may comprise a substantially continuous planar surface, or may include planar areas of different levels. In any event, the top surfaces of the insulating layer are smoothed.
• non-planarized processing only one opening over a given region is allowed. In other words, only one layer is allowed to have an opening over a given region.
• openings have to be at least a predetermined distance from another opening. The actual distance depends on whether an adjacent opening is in the immediately adjacent oxide layer.
• planarized processing With planarized processing, the limitations are not as stringent. More than one opening over a given region is allowed so long as the openings are not on adjacent oxide layers. However, due to processing limitations, the tops of the deposited metal over the openings include indentations and minimum spacing between adjacent openings is required. Such spacing requirements are less stringent than for non-planarized processing. As a result of the design rules associated with known non-planarized and planarized processing of metal ⁇ lization layers, routing is necessarily complex and difficult. Further, such design rules limit device density, although greater density is achieved with planarized processing as compared to non-planarized processing.
• a further consideration with known processing of metallized contacts and vias is the limitation on minimum size of the openings. Specifically, if the openings are made too small, the deposited metallization at the edges of the openings will be too thin and may crack. The limitation on minimum opening size also affects device density.
• Still another advantage would be to provide for conductively filled integrated circuit structure contact and via openings which allow for greater device densities.
• a further advantage would be to provide for conduc ⁇ tively filled integrated circuit structure contact and via openings which are planarized.
• the foregoing and other advantages are provided by the invention in a process for filling contact or via openings in an integrated circuit with electrically conductive plugs.
• the process includes the steps of (a) forming one or more openings in an planarized oxide layer, the one or more openings being disposed over and exposing semi-insulating or conductive regions; and (b) filling the one or more openings with conductive material to substan ⁇ tially the same level as the adjacent surfaces of the oxide layer to form respective planarized conductive plugs.
• a further aspect of the invention is directed to a process which includes the steps of (a) forming first one or more openings of a first predetermined depth in a planarized oxide layer, the first one or more openings being disposed over and exposing respectively associated semi-insulating or conductive regions; (b) partially filling the first one or more openings with conductive material to a level corresponding to a second predetermined depth; (c) forming second one or more openings of the second predetermined depth in the planarized oxide layer, the second one or more openings being disposed over and exposing respectively associated semi-insulating or conductive regions; and (d) filling the first and second one or more openings to substantially the same level to form respective planarized plugs in the openings.
• FIGS. 1A through ID schematically illustrate an embodiment of the process of the invention.
• FIGS. 2A through 2C schematically illustrate another embodiment of the process of the invention.
• FIGS. 3A through 3D schematically illustrate still another embodiment of the process of the invention.
• FIGS. 4A through 4E schematically illustrate a further embodiment of the process of the invention.
• FIGS. 5A through 5E schematically illustrate a further embodiment of the process of the invention.
• openings 11, 13 of differ ⁇ ent depths are formed, for example by appropriate masking and etching, in a planarized oxide layer 15.
• the sides of the openings 11, 13 are vertical while the bottoms of the openings and the tops of the areas between and adjacent the openings 11, 13 are horizontal.
• the openings 11, 13 are preferably of the same diameter.
• the oxide layer 15 is shown as being formed on a thin gate oxide layer 16 which merges into a thicker field oxide layer 21.
• the gate oxide 16 and the field oxide 21 are formed on a substrate 17.
• the opening 11 exposes a portion of the substrate 17, while the opening 13 exposes a portion of a polysilicon layer 19 which is formed on the field oxide 21.
• the portion of the substrate 17 exposed by the opening 11 may be part of a doped region of a device, while the polysilicon layer 19 may form the gate of the device.
• Poly or amorphous silicon is chemically vapor deposited on the structure of FIG. 1A to provide a thin (about 100A to 1000A) deposited blanket layer of silicon 23 as shown in FIG. IB.
• the structure of FIG. IB is then subjected to an anisotropic silicon etch which removes the deposited silicon layer 23 from the horizontal surfaces of the structure, while substantially leaving the deposited silicon layer 23 on the vertical surfaces.
• An over-etch is appropriate so that the deposited silicon layer 23 in the upper portions of the openings 11, 13 is removed to result in the structure of FIG. 1C.
• the over-etch pre ⁇ vents overfilling the openings 11, 13 with tungsten, which is selectively deposited in the next step.
• tungsten is then deposited by chemical vapor deposition.
• Tungsten selectively deposits to silicon and metal, and therefore the chemically vapor deposited tungsten will only deposit on the silicon at the bottom of the openings 11, 13 and on the deposited silicon layer 23 on the sides of the open ⁇ ings 11, 13. Since tungsten will deposit on metal, it would also deposit appropriately for via openings to a layer of metallization.
• the deposition of tungsten is controlled to provide deposited planarized tungsten plugs 25, 27 which fill the openings 11, 13 as shown in FIG. ID. Optimally, the tops of the resulting tungsten plugs 25, 27 should only be slightly above the surrounding horizontal surfaces so that the top of the structure remains planarized.
• the tungsten plugs 25, 27 of FIG. ID include centrally located vertical boundaries which schematically represent the merger of the conformal deposition growth of the tungsten. Further embodiments of the invention are also schematically shown with vertical boundaries within deposited regions for the same reason. It should be appreciated that such boundaries eventually cease to be identifiable when the deposited structures are subjected to the heating of further processing. Referring now to FIGS. 2A through 2C, illustrated therein is a further technique in accordance with the invention for metallizing via or contact openings which are of different depths and which may be of different diameters. Each of the openings contemplated by this technique have bottoms that are silicon or metal as discussed above relative to FIGS. 1A through ID.
• FIG. 2A illustrates a structure having an opening 111 in a planarized oxide layer 115.
• the opening 111 is formed by appropriate masking and etching.
• An opening 213 of shallower depth will be formed pursuant to subsequent processing, and its future location is shown in dashed lines.
• Tungsten is then chemically vapor deposited which causes the opening 111 to be filled from the bottom.
• the tungsten chemical vapor deposition is controlled to provide a tungsten plug 125 so that the depth of the partially filled opening 111 is the same as the contemplated depth of the future opening 113, as illustrated in FIG. 2B.
• the opening 113 is then formed, for example by masking and etching, and tungsten is then chemically vapor deposited. Pursuant to such deposition, the openings 111, 113 are filled with deposited planarized tungsten plugs 125, 127. The chemical vapor deposition is controlled so that the tops of the deposited tungsten plugs 125, 127 are only slightly above the surrounding horizontal surfaces so that the top of the structure remains planarized. The resulting structure is illustrated in FIG. 2C.
• FIGS. 2A through 2C may be advantageously utilized in applications where there are a number of different depths and diameters of contact or via openings. Such technique would utilize a specific mask and etch procedure for each contact or via opening of a given depth, which would then be followed by a chemical vapor deposition of tungsten.
• the foregoing use of separate mask, etch, and partial fill steps for openings of different depths and diameters allows better alignment relative to previous layers since the use of separate masks allows for more precise control of the size and depth of the openings. For example, about a 40% improvement in alignment registration may be achieved.
• partial filling of the openings of greater depth may provide for more planarized plugs since the openings are all uniformly filled from the bottom.
• the openings 111, 113 may be of different diameters, which would still provide for planarized plugs since the open ⁇ ings are filled from the bottom.
• openings 211, 213 of the same diameter are formed (for example, by masking and etching) in a planarized oxide layer 215.
• the bottoms of the openings 211, 213 may be silicon or metal.
• the resulting structure is illustrated in FIG 3A.
• a selected material to which tungsten will deposit is then chemically vapor deposited on the structure of o o FIG. 3A to provide a thin (100A - 1000A) deposited blanket layer of such selected material, as shown in FIG. 3B.
• the material may comprise a refractory metal silicide; or may comprise silicon, titanium nitride, titanium, tungsten disilicide, a titanium-tungsten alloy, tungsten nitride or other material on which tungsten will deposit.
• Tungsten is then chemically vapor deposited on the structure, and the deposited layer 229 functions as an adhesive layer for the tungsten.
• the contact or via openings 211, 213 are filled from the sides, and the resulting structure includes a deposited tungsten layer 231 which fills the openings 211, 213 and extends upwardly from the tops of the openings 211, 213, as illustrated in FIG. 3C.
• FIG. 3C The structure of FIG. 3C is then uniformly etched until only the tungsten in the contact or via openings 211, 213 remains. " The resulting structure includes planarized tungsten plugs 225, 227 in the openings 211, 213, as illustrated in FIG. 3D.
• FIGS. 4A through 4E illustrated therein is a technique contemplated by the invention for filling contact or via openings with doped polysilicon plugs. Openings 311, 313 of the same diameter, which may be of different depths, are formed in an oxide layer 315.
• the resulting structure is shown in FIG. 4A.
• a selected material is chemically vapor deposited or sputtered on the o o structure of FIG. 4A to provide a thin (100A - 1000A) blanket deposited layer 329, as shown in FIG. 4B.
• the selected material functions as a diffusion barrier, and may comprise a refractory metal silicide; or may comprise titanium, titanium tungsten, titanium nitride, or tungsten nitride.
• the resulting structure for such deposited material is shown in FIG. 4B.
• the deposited material may also be tungsten, but in the case of tungsten the resulting structure is different than that for the other materials and is discussed relative to FIGS. 5A-5E
• the deposited layer 329 which is of a material other than tungsten, covers the horizontal and vertical surfaces of this structure. Silicon is then chemically vapor deposited to provide a deposited polysilicon layer 331 as illustrated in FIG. 4C.
• the deposited polysilicon layer 331 fills the openings 311, 313 and extends upwardly from the tops of such openings.
• the deposited polysilicon 331 is then doped by ion implantation, as shown in FIG. 4D.
• the doped polysilicon is activated by heating, and the structure is then etched to provide for planarized doped silicon plugs 325, 327 in the openings 311, 313 as shown FIG. 4E.
• Openings 411, 413 of the same diameter are formed, for example by masking and etching, in an oxide layer 415 as shown in FIG. 5A.
• Tungsten is chemically vapor deposited, and selectively deposits to the bottoms of the openings 411, 413 since the bottoms are silicon or metal. The deposition is controlled to provide thin deposited tungsten layers 429 at the bottom of the openings 411, 413 as shown in FIG. 5B.
• Silicon is then deposited by chemical vapor deposition to result in the structure of FIG. 5D, which includes a deposited polysilicon layer 431.
• the deposited polysilicon layer 431 fills the openings 411, 413 and extends upwardly from the tops of these openings.
• the deposited polysilicon 431 is then doped by ion implantation, as illustrated in FIG. 5D.
• the doped polysilicon is activated by heating, and the structure is then etched to provide the structure of FIG. 5E which includes planarized polysilicon plugs in the openings 411, 413.
• FIGS. 5A through 5E is somewhat simpler in that the etching required to planarize the plugs in the openings only has to etch through one type of material.
• FIGS. 4A through 4E and FIGS. 5A through 5E may be appropriate only for filling (a) contact openings, and (b) via open ⁇ ings which have high temperature metals. This results from the high temperatures required for the vapor deposi ⁇ tion of polysilicon.
• the deposited diffusion barrier layers are needed only when the openings are contact openings.
• the barrier layer prevents counter doping of oppositely doped regions.
• no barrier is required, and the step of chemically vapor depositing a barrier layer is not necessary.
• the metal at the bottom of the via openings must have a sufficiently high melting temperature (e.g., tungsten) so that it will not melt when the silicon is vapor deposited.
• the invention is not limited to openings to silicon or metal, and generally contemplates openings to appropriate semi-insulating or conductive regions.

Landscapes

• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Priority Applications (1)

Applications Claiming Priority (2)

Publications (1)

Family

ID=25481791

Family Applications (1)

Country Status (4)

Cited By (4)

Families Citing this family (3)

Citations (3)

• 1987
  • 1987-10-23 EP EP88901167A patent/EP0298110A1/en not_active Withdrawn
  • 1987-10-23 JP JP63501394A patent/JPH01501588A/ja active Pending
  • 1987-10-23 WO PCT/US1987/002767 patent/WO1988004831A1/en not_active Application Discontinuation
  • 1987-10-23 KR KR1019880701007A patent/KR910006975B1/ko active IP Right Grant

Patent Citations (3)

Also Published As

Similar Documents

Legal Events