Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
  • G06T1/00—General purpose image data processing
  • G06T1/60—Memory management
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2340/00—Aspects of display data processing
  • G09G2340/12—Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels

Definitions

• the present invention relates to a method for saving surface image information for displaying another image on one image. Background technology
• Fig. 2 shows this example.
• 10 is a display screen
• 11 is a first image
• 12 is numerical data to be newly displayed on the first image.
• the hatched part of the first image is temporarily returned to data memory, part of the frame memory that temporarily stores the image information, and is newly displayed in an empty part of the frame memory.
• a method for inputting image information such as numerical data to be performed is known.
• It has a frame memory for storing image information and a high-speed image calculation buffer memory for performing image calculation, and is used to display a second image on the first image.
• Image information evacuation method
• the image information evacuation method is characterized by
• FIG. 1 is a block diagram of one embodiment of the present invention.
• Fig. 2 is an explanatory diagram for displaying another image on one image,
• FIG. 3 is a diagram showing the details of the transfer of the information of the frame memory and the image calculation ban memory.
• FIG. 1 shows a block diagram of an embodiment of the present invention.
• 1 is a main CPU
• 2 is a data memory storing image information and programs
• 3 is a bus arbitration circuit
• 4 is a CPU for calculating a surface image.
• Reference numeral 5 denotes a frame memory for storing image information
• reference numeral 6 denotes a gate.
• the data transfer between the frame memory 5 and the image memory buffer memory 7 is commanded by the image processing CP 4.
• Control based on Reference numeral 7 denotes a buffer memory for image calculation, which is a buffer memory for performing image processing such as conversion of image data and spatial filtering.
• the capacity is generally smaller than the frame memory, but the capacity is determined according to the content of the performance.
• Reference numeral 8 denotes a monitor, which is a display device for displaying the contents of the frame memory. Generally, a CRT display device 0 is used.
• Reference numeral 9 denotes a camera, which captures the required image, processes the image information according to the plane image presentation CP # 4, and transfers it to the data memory.
• the necessary image information is selected from the data memory 2 by the main CPU i, stored in the frame memory 55, and displayed on the monitor 8 by the image calculation CPU 4. i.
• the main CPU 1 transfers a part of the preceding image from the frame memory 5 to the buffer for image rendering. It issues a command to CPU 4 for the transfer of the statue Nishikata to transfer it to LI 7.
• the CPU 4 for image execution opens the gate 6 and saves a part of the data in the frame memory to the image calculation buffer memory 7.
• the main CPU 1 transfers a part of another image from the data memory to the empty part of the frame memory 5.
• the contents of the frame memory 5 include a part of the previous image information and a part of the other image information, and the monitor 8 superimposes another image on the previous image.
• the CPU 4 for image rendering saves the image information in the buffer memory 7 for image rendering and returns the image information of the destination to the frame memory 5, and the data in the frame memory 5 is Only the image information of the previous image is displayed on the monitor 8. 5
• the frame memory 5 and the image memory buffer memory 7 are configured so that they can be transferred at a higher speed for image processing than the data memory 2 and the frame memory 5. Because of this, the previous image information can be quickly returned.
• Figure 3 shows the details of the transfer of information between the frame memory 5 and the image calculation buffer memory 7.
• 5 is a frame memory
• 6 is a gate
• 7 is an image calculation buffer memory.
• a counter 13 for counting up the address is stored in the frame memory 5, and an address is also stored in the buffer memory 7 for the image ⁇ image.
• the counters 13 and 14 are controlled by a microprogram 15 of the image processing CPU 4 shown in FIG. That is, when an instruction to save a part of the data in the frame memory 5 from the main CP 1 to the buffer memory for image execution is issued, the CP 4 for image operation is caught.
• the first address of the data to be saved to the counter 13 is set, and the first address of the image memory buffer memory to be transferred to the counter 14 is set. Each time one byte of data is transferred, the addresses of counters 13 and 14 are counted up. In this way, the necessary data is read from the frame memory 5 and the image display. To buffer memory 7. Therefore, all data transfers are handled by the microprogram.
• the present invention is configured to save the previous image information in the image memory buffer memory when another image is superimposed and displayed on one plane image.
• the burden on the main CPU can be reduced.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Computer Hardware Design (AREA)
• Digital Computer Display Output (AREA)
• Controls And Circuits For Display Device (AREA)
• Processing Or Creating Images (AREA)
• Image Input (AREA)

Applications Claiming Priority (2)

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ID=14685735

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Citations (2)

Family Cites Families (1)

• 1986
  • 1986-05-21 JP JP61116386A patent/JPS62272370A/ja active Granted
• 1987
  • 1987-05-16 WO PCT/JP1987/000308 patent/WO1987007411A1/ja not_active Application Discontinuation
  • 1987-05-16 EP EP19870903405 patent/EP0268687A1/en not_active Withdrawn

Patent Citations (2)

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