WO1987004854A2 - Liquid epitaxial process for producing three-dimensional semiconductor structures - Google Patents
Liquid epitaxial process for producing three-dimensional semiconductor structures Download PDFInfo
- Publication number
- WO1987004854A2 WO1987004854A2 PCT/EP1987/000064 EP8700064W WO8704854A2 WO 1987004854 A2 WO1987004854 A2 WO 1987004854A2 EP 8700064 W EP8700064 W EP 8700064W WO 8704854 A2 WO8704854 A2 WO 8704854A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- layer
- epitaxial
- layers
- silicon
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02395—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02433—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02576—N-type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02623—Liquid deposition
- H01L21/02625—Liquid deposition using melted materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02623—Liquid deposition
- H01L21/02628—Liquid deposition using solutions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19863604260 DE3604260A1 (de) | 1986-02-11 | 1986-02-11 | Fluessigkeitsepitaxieverfahren |
DEP3604260.9 | 1986-02-11 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1987004854A2 true WO1987004854A2 (en) | 1987-08-13 |
WO1987004854A3 WO1987004854A3 (fr) | 1988-03-24 |
Family
ID=6293866
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP1987/000064 WO1987004854A2 (en) | 1986-02-11 | 1987-02-11 | Liquid epitaxial process for producing three-dimensional semiconductor structures |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0255837A1 (de) |
JP (1) | JPS63502472A (de) |
DE (1) | DE3604260A1 (de) |
WO (1) | WO1987004854A2 (de) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4863877A (en) * | 1987-11-13 | 1989-09-05 | Kopin Corporation | Ion implantation and annealing of compound semiconductor layers |
FR2629636A1 (fr) * | 1988-04-05 | 1989-10-06 | Thomson Csf | Procede de realisation d'une alternance de couches de materiau semiconducteur monocristallin et de couches de materiau isolant |
EP0651447A1 (de) * | 1993-10-29 | 1995-05-03 | Texas Instruments Incorporated | Resonantes Tunneln in Silizium |
US5453153A (en) * | 1987-11-13 | 1995-09-26 | Kopin Corporation | Zone-melting recrystallization process |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3016432B2 (ja) * | 1989-09-21 | 2000-03-06 | 沖電気工業株式会社 | 半導体基板の製造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4028147A (en) * | 1974-12-06 | 1977-06-07 | Hughes Aircraft Company | Liquid phase epitaxial process for growing semi-insulating GaAs layers |
EP0143957A1 (de) * | 1983-10-28 | 1985-06-12 | Siemens Aktiengesellschaft | Verfahren zur Herstellung von A3B5-Lumineszenzdioden |
US4551394A (en) * | 1984-11-26 | 1985-11-05 | Honeywell Inc. | Integrated three-dimensional localized epitaxial growth of Si with localized overgrowth of GaAs |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51126048A (en) * | 1975-01-31 | 1976-11-02 | Hitachi Ltd | Hetero epitaxial growth method of iii-v group semi-conductors |
JPS51138180A (en) * | 1975-05-26 | 1976-11-29 | Nippon Telegr & Teleph Corp <Ntt> | Distributed feedback type semi-conductor laser and the method of manuf acturing it |
JPS6040719B2 (ja) * | 1979-03-30 | 1985-09-12 | 松下電器産業株式会社 | 半導体レ−ザ装置 |
-
1986
- 1986-02-11 DE DE19863604260 patent/DE3604260A1/de not_active Withdrawn
-
1987
- 1987-02-11 JP JP50245187A patent/JPS63502472A/ja active Pending
- 1987-02-11 WO PCT/EP1987/000064 patent/WO1987004854A2/de not_active Application Discontinuation
- 1987-02-11 EP EP19870902458 patent/EP0255837A1/de not_active Ceased
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4028147A (en) * | 1974-12-06 | 1977-06-07 | Hughes Aircraft Company | Liquid phase epitaxial process for growing semi-insulating GaAs layers |
EP0143957A1 (de) * | 1983-10-28 | 1985-06-12 | Siemens Aktiengesellschaft | Verfahren zur Herstellung von A3B5-Lumineszenzdioden |
US4551394A (en) * | 1984-11-26 | 1985-11-05 | Honeywell Inc. | Integrated three-dimensional localized epitaxial growth of Si with localized overgrowth of GaAs |
Non-Patent Citations (6)
Title |
---|
Applied Physics Letters, Band 38, Nr. 5, Marz 1981, (New York, US), P.C. CHEN et al.: "Embedded Epitaxial Growth of Low-Threshold GaInAsP/InP Injection Lasers", seiten 301-303 siehe das ganze dokument * |
IBM Technical Disclosure Bulletin, Band 15. Nr. 3, August 1972, (New York, US), J.M. BLUM et al.: "Integrated Light Emitting pnpn and npn Devices", seiten 951-952 siehe das ganze dokument * |
Japanese Journal of Applied Physics, Band 6, Nr. 7, Juli 1967, (Tokyo, JP), T. NAKANO: "Preparation and Properties of GaAs-Si Heterofunctions By Solution Growth Method", seiten 854-863 * |
Journal of the Electrochemical Society, Band 12., Nr. 12, Dezember 1982, (Manchester, New Hampshire, US), B. Jayant Baliga: "Refilling Silicon Grooves by Liquid Phase Epitaxy", seiten 2819-2823 siehe seiten 2820-2822: "Experimental Procedure and results", abbildungen 1-10 * |
Journal of the Electrochemical Society, Band 133, Nr. 1, Januar 1986, (Manchester, New Hampshire, US), B. JAYANT BALIGA: "Silicon Liquid Phase Epitaxy", Seiten 5C-14C siehe abschitt: "Apparatus and Experimental Procedure"; seite 9C; abschnitt: "Epixal Refill"; seiten 12C-13C; abbildungen 12-14 * |
Solid State Technology, Band 27, Nr. 9, September 1984, (Port Washington, New York, US), L. JASTRZEBSKI: "Silicon CUD for SOI: Priciples and Possible Applications", seiten 239-243 * |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4863877A (en) * | 1987-11-13 | 1989-09-05 | Kopin Corporation | Ion implantation and annealing of compound semiconductor layers |
US5453153A (en) * | 1987-11-13 | 1995-09-26 | Kopin Corporation | Zone-melting recrystallization process |
FR2629636A1 (fr) * | 1988-04-05 | 1989-10-06 | Thomson Csf | Procede de realisation d'une alternance de couches de materiau semiconducteur monocristallin et de couches de materiau isolant |
EP0336830A1 (de) * | 1988-04-05 | 1989-10-11 | Thomson-Csf | Verfahren zur Herstellung einer alternierenden Folge monokristalliner Halbleiterschichten und Isolierschichten |
EP0651447A1 (de) * | 1993-10-29 | 1995-05-03 | Texas Instruments Incorporated | Resonantes Tunneln in Silizium |
Also Published As
Publication number | Publication date |
---|---|
WO1987004854A3 (fr) | 1988-03-24 |
EP0255837A1 (de) | 1988-02-17 |
DE3604260A1 (de) | 1987-08-13 |
JPS63502472A (ja) | 1988-09-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE60101069T2 (de) | Siliziumkarbid und Verfahren zu seiner Herstellung | |
DE2416550C2 (de) | Verfahren zum Herstellen eines Halbleiterbauelements mit versetzungsfreiem Übergitterstrukturkristall | |
EP1739210B1 (de) | Verfahren zur Herstellung von dotierten Halbleiter-Einkristallen, und III-V-Halbleiter-Einkristall | |
DE4138121C2 (de) | Verfahren zur Herstellung einer Solarzelle | |
DE69631662T2 (de) | GaAs-SUBSTRAT MIT GRADIERT ZUSAMMENGESETZTEM AeGaAsSb-PUFFER ZUR HERSTELLUNG VON FELDEFFEKTTRANSISTOREN MIT HOHEM INDIUM-GEHALT | |
DE19510922A1 (de) | Verfahren zur Herstellung eines Halbleiterbauelements, Verfahren zur Reinigung einer Kristalloberfläche eines Halbleiters sowie Halbleiterbauelement | |
DE3446961A1 (de) | Verfahren zur herstellung einer sic-halbleitervorrichtung | |
DE2030805A1 (de) | Verfahren zur Ausbildung epitaxialer Kristalle oder Plattchen in ausgewählten Bereichen von Substraten | |
DE10247017A1 (de) | SiC-Einkristall, Verfahren zur Herstellung eines SiC-Einkristalls, SiC-Wafer mit einem Epitaxiefilm, Verfahren zur Herstellung eines SiC-Wafers, der einen Epitaxiefilm aufweist und eine elektronische Vorrichtung aus SiC | |
DE1564191B2 (de) | Verfahren zum herstellen einer integrierten halbleiterschaltung mit verschiedenen, gegeneinander und gegen ein gemeinsames siliziumsubstrat elektrisch isolierten schaltungselementen | |
DE1223951B (de) | Verfahren zur Herstellung von Halbleiter-bauelementen mit einem oder mehreren PN-UEbergaengen | |
DE3422750A1 (de) | Verfahren zum herstellen einer schicht aus einem mehrbestandteilmaterial | |
DE102019108754A1 (de) | Halbleitervorrichtung mit einem porösen bereich, waferverbundstruktur und verfahren zum herstellen einerhalbleitervorrichtung | |
DE1961225A1 (de) | Integrierte Halbleiterschaltung und Verfahren zu ihrer Herstellung | |
DE2207056A1 (de) | Verfahren zum selektiven epitaxialen Aufwachsen aus der flüssigen Phase | |
DE3634140C2 (de) | ||
DE3514294A1 (de) | Mit indium dotierte halbisolierende galliumarsenideinkristalle und verfahren zu ihrer herstellung | |
DE4427715C1 (de) | Komposit-Struktur mit auf einer Diamantschicht und/oder einer diamantähnlichen Schicht angeordneter Halbleiterschicht sowie ein Verfahren zu deren Herstellung | |
EP1701386B1 (de) | Verfahren zur Integration von zwei Bipolartransistoren in einem Halbleiterkörper, Halbleiteranordnung in einem Halbleiterkörper und Kaskodenschaltung | |
WO1987004854A2 (en) | Liquid epitaxial process for producing three-dimensional semiconductor structures | |
DE3300716A1 (de) | Verfahren zum bilden von monokristallinem silicium auf einer maskenschicht | |
DE2154386A1 (de) | Verfahren zum Herstellen einer epitaktischen Schicht auf einem Halbleitersubstrat, bei dem das Selbstdotieren beim Aufwachsen der Schicht auf ein Mindestmaß verringert wird | |
DE2163075C2 (de) | Verfahren zur Herstellung von elektrolumineszierenden Halbleiterbauelementen | |
DE3124456A1 (de) | Halbleiterbauelement sowie verfahren zu dessen herstellung | |
DE3334236C2 (de) | Verfahren zum Herstellen einer Halbleiteranordnung |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): JP US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH DE FR GB IT LU NL SE |
|
CR1 | Correction of entry in section i |
Free format text: IN PAT.BUL.18/87,UNDER PUBLISHED REPLACE "A1" BY "A2" |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1987902458 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1987902458 Country of ref document: EP |
|
AK | Designated states |
Kind code of ref document: A3 Designated state(s): JP US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): AT BE CH DE FR GB IT LU NL SE |
|
WWR | Wipo information: refused in national office |
Ref document number: 1987902458 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1987902458 Country of ref document: EP |