WO1987003716A3 - Systeme de memoire insensible aux defaillances - Google Patents

Systeme de memoire insensible aux defaillances Download PDF

Info

Publication number
WO1987003716A3
WO1987003716A3 PCT/GB1986/000760 GB8600760W WO8703716A3 WO 1987003716 A3 WO1987003716 A3 WO 1987003716A3 GB 8600760 W GB8600760 W GB 8600760W WO 8703716 A3 WO8703716 A3 WO 8703716A3
Authority
WO
WIPO (PCT)
Prior art keywords
ram
serial
clock pulses
pulses
memory
Prior art date
Application number
PCT/GB1986/000760
Other languages
English (en)
Other versions
WO1987003716A2 (fr
Inventor
Neal Macdonald
Original Assignee
Anamartic Ltd
Neal Macdonald
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anamartic Ltd, Neal Macdonald filed Critical Anamartic Ltd
Publication of WO1987003716A2 publication Critical patent/WO1987003716A2/fr
Publication of WO1987003716A3 publication Critical patent/WO1987003716A3/fr
Priority to KR870700729A priority Critical patent/KR880700970A/ko

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/86—Masking faults in memories by using spares or by reconfiguring in serial access memories, e.g. shift registers, CCDs, bubble memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

Un ordinateur numérique (15) peut écrire un bloc de données dans une mémoire vive (RAM) (10), ou lire un bloc de données à partir de cette mémoire, via un convertisseur série/parallèle (17) qui est en série par mots et en parallèle par bits du côté de l'ordinateur et en série par bit du côté de la mémoire vive. Cette dernière est adressée par un conpteur d'adresse (18) tournant librement, cadencé par les impulsions d'horloge WCK. Un circuit de masquage de défaillance (19) permet d'éliminer par masque les cellules défaillantes dans une mémoire vive (10). Les données spécifiques à la mémoire vive (10) provoquent le déclanchement sélectif des impulsions d'horloge WCK afin d'appliquer des impulsions d'horloge à cadence binaire GCK au convertisseur (17). Ces impulsions sont divisées pour produire des impulsions BCK à une cadence de mots. L'invention est particulièrement utile dans un circuit intégré sur tranche comprenant un grand nombre de mémoires vives (10) désservies par un seul circuit de masquage de défaillance (19), avec des données tabulées définissant les cellules de mémoire destinées à être éliminées par masquage, et ceci mémoire par mémoire.
PCT/GB1986/000760 1985-12-13 1986-12-12 Systeme de memoire insensible aux defaillances WO1987003716A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR870700729A KR880700970A (ko) 1985-12-13 1987-08-13 폴트 허용 메모리 시스템

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8530770A GB2184268B (en) 1985-12-13 1985-12-13 Fault tolerant memory system
GB8530770 1985-12-13

Publications (2)

Publication Number Publication Date
WO1987003716A2 WO1987003716A2 (fr) 1987-06-18
WO1987003716A3 true WO1987003716A3 (fr) 1987-07-16

Family

ID=10589724

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1986/000760 WO1987003716A2 (fr) 1985-12-13 1986-12-12 Systeme de memoire insensible aux defaillances

Country Status (6)

Country Link
US (1) US4868789A (fr)
EP (1) EP0248875A1 (fr)
JP (1) JPS63502147A (fr)
KR (1) KR880700970A (fr)
GB (1) GB2184268B (fr)
WO (1) WO1987003716A2 (fr)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2184268B (en) * 1985-12-13 1989-11-22 Anamartic Ltd Fault tolerant memory system
WO1989000728A1 (fr) * 1987-07-17 1989-01-26 Ivor Catt Circuits integres
US5146571A (en) * 1988-03-28 1992-09-08 Emc Corporation Remapping defects in a storage system through the use of a tree structure
JPH0290816A (ja) * 1988-09-28 1990-03-30 Hitachi Ltd 誤り訂正方法および回路
GB8903180D0 (en) * 1989-02-13 1989-03-30 Anamartic Ltd Fault masking in semiconductor memories
EP0389203A3 (fr) * 1989-03-20 1993-05-26 Fujitsu Limited Dispositif de mémoire à semi-conducteur comportant de l'information indiquant la présence de cellules de mémoire défectueuses
US5077737A (en) * 1989-08-18 1991-12-31 Micron Technology, Inc. Method and apparatus for storing digital data in off-specification dynamic random access memory devices
JP2617026B2 (ja) * 1989-12-22 1997-06-04 インターナショナル・ビジネス・マシーンズ・コーポレーション 障害余裕性メモリ・システム
US5105425A (en) * 1989-12-29 1992-04-14 Westinghouse Electric Corp. Adaptive or fault tolerant full wafer nonvolatile memory
JPH03214500A (ja) * 1990-01-18 1991-09-19 Sony Corp メモリ装置
US5128737A (en) * 1990-03-02 1992-07-07 Silicon Dynamics, Inc. Semiconductor integrated circuit fabrication yield improvements
JP2781658B2 (ja) * 1990-11-19 1998-07-30 日本電気アイシーマイコンシステム株式会社 アドレス生成回路とそれを用いたｃｄ―ｒｏｍ装置
US5377148A (en) * 1990-11-29 1994-12-27 Case Western Reserve University Apparatus and method to test random access memories for a plurality of possible types of faults
GB9305801D0 (en) * 1993-03-19 1993-05-05 Deans Alexander R Semiconductor memory system
JP3059076B2 (ja) * 1995-06-19 2000-07-04 シャープ株式会社 不揮発性半導体記憶装置
FR2754100B1 (fr) * 1996-09-30 1998-11-20 Sgs Thomson Microelectronics Memoire a acces serie avec securisation de l'ecriture

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4066880A (en) * 1976-03-30 1978-01-03 Engineered Systems, Inc. System for pretesting electronic memory locations and automatically identifying faulty memory sections
US4070651A (en) * 1975-07-10 1978-01-24 Texas Instruments Incorporated Magnetic domain minor loop redundancy system
US4074236A (en) * 1974-12-16 1978-02-14 Nippon Telegraph And Telephone Public Corporation Memory device
GB2014767A (en) * 1978-02-17 1979-08-30 Hitachi Ltd Memory devices

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1377859A (en) * 1972-08-03 1974-12-18 Catt I Digital integrated circuits
GB2083929B (en) * 1980-08-21 1984-03-07 Burroughs Corp Branched labyrinth wafer scale integrated circuit
GB2089536B (en) * 1980-12-12 1984-05-23 Burroughs Corp Improvement in or relating to wafer scale integrated circuits
JPS59214952A (ja) * 1983-05-20 1984-12-04 Nec Corp 障害処理方式
GB2166273A (en) * 1984-10-29 1986-04-30 Thesys Memory Products Corp Fault avoidance in semiconductor memories
US4706216A (en) * 1985-02-27 1987-11-10 Xilinx, Inc. Configurable logic element
GB2177825B (en) * 1985-07-12 1989-07-26 Anamartic Ltd Control system for chained circuit modules
GB2181870B (en) * 1985-10-14 1988-11-23 Anamartic Ltd Control circuit for chained circuit modules
GB2184268B (en) * 1985-12-13 1989-11-22 Anamartic Ltd Fault tolerant memory system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4074236A (en) * 1974-12-16 1978-02-14 Nippon Telegraph And Telephone Public Corporation Memory device
US4070651A (en) * 1975-07-10 1978-01-24 Texas Instruments Incorporated Magnetic domain minor loop redundancy system
US4066880A (en) * 1976-03-30 1978-01-03 Engineered Systems, Inc. System for pretesting electronic memory locations and automatically identifying faulty memory sections
GB2014767A (en) * 1978-02-17 1979-08-30 Hitachi Ltd Memory devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE Journal of Solid-State Circuits, Vol. SC-13, No. 3, June 1978 (IEEE, New York, USA), R.C. AUBUSSON et al., "Wafer-Scale Integration - a Fault- Tolerant Procedure", pages 339-344, see page 342, left-hand column, line 8 - right-hand column, line 40 *

Also Published As

Publication number Publication date
KR880700970A (ko) 1988-04-13
GB2184268A (en) 1987-06-17
WO1987003716A2 (fr) 1987-06-18
JPS63502147A (ja) 1988-08-18
GB2184268B (en) 1989-11-22
US4868789A (en) 1989-09-19
GB8530770D0 (en) 1986-01-22
EP0248875A1 (fr) 1987-12-16

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