GB2166273A - Fault avoidance in semiconductor memories - Google Patents

Abstract

Semiconductor memories employing shared row and column input lines and having faulty memory cells or sense amplifiers are usable at their normal speed and without delay losses with the circuitry of the invention which separates input row and column addresses, and transmits the row addresses through a gated buffer (52) to the shared input lines (A0-A8) of the memory during the first state of a gating signal for use during a row enable signal. The circuitry includes a column address changing PROM (54) which has been programmed to skip addresses of columns having faulty cells or sense amplifiers and redirect the addresses to good columns. The PROM completes its address translations during the first state of the gating signal and transfers the corrected column addresses to the shared input lines during the second state of the gating signal for use during a column enable signal. <IMAGE>

Description

SPECIFICATION Fault avoidance in semiconductor memories This invention relates generally to semiconductor random access computer memory arrays, and particularly to novel circuitry that permits the use of memory devices having defective bit locations which would normally require the manufacturer's rejection and scrapping of the device.

In the manufacture of semiconductor circuit chips, there are many "good" chips and many more "bad" chips on a wafer. A high percentage of the so-called bad chips have one or a very few defective components and these "partials" can be purchased from the manufacturer at a very low cost for use in certain circuits not requiring the particular component in the chip that is defective.

In high capacity dynamic random access memory (DRAM) chips such as, for example, the Western Electric WCM41256-17 having a memory capacity of 21s bits, a single defective bit in the total of 262,144 renders the entire chip defective and, unless circuitry were developed that could use these partials, there would result a scrapping of the entire memory chip.

In the late 1960's the inventor herein developed a technique for using partials (partially defective memory chips) in a memory system. The technique was implemented and demonstrated on the ILLIAC IV main memory system and consisted of testing, sorting and classifying the partial chips into sixteen groups where the defective bit positions in a specific group were concentrated in a given one-sixteenth of the addressing space. A printed circuit board was designed to have sixteen areas, one for each of the respective classifications, and a seventeenth area where all good chips were used. The addressing system was designed in the hardware to bypass the addresses of defective areas in the partial groups and to substitute therefor the equivalent good areas at that same chip address in the seventeenth group.Since that first memory using partially defective semiconductors circuit chips, others have been designed using the basic technique. Some skipped one-half of the chip, others skipped one-quarter or one-eighth, and some one-sixteenth.

In another technique for using partials in a memory system, the packaged chips were inserted at random in a printed circuit board, the board was tested and a "map" developed to record where the defective bits and areas were located. This map was converted to logic elements in the addressing system and when the associated computer sent an address to the memory, it was sent to the map as a map address. Stored in that location in the map was the address of a known good memory bit or area, and this map address was accessed and used as a substitute address for the one called out by the computer.

A variation of this mapped addressing technique stores a map of a portion of the memory address space in a nonvolatile memory and adds to the original computer address the value of the data contained in the mapped location. The data group thus developed is used as an address to a good bit or area. This technique involves the use of an arithmetic unit or a microprocessor as well as the nonvolatile memory. If a zero is stored in the map, the memory is addressed at its original good location. If other than a zero, the incremental amount stored in the map is added to the address to convert it to the location of a good bit of area.

A block diagram of this prior art technique of skipping from a defective memory location to a good section is illustrated in Figure 1. The addresses from an external microprocessor are received and sent to both an arithmetic unit and a mapping PROM that was previously programmed to store the incremental amounts necessary to convert the address from a defective bit position of the memory array to the location of a good bit or area. The addresses sent to the PROM thus cause an access and the value stored at that location in the PROM is sent to the arithmetic logic unit (ALU).

Note, in Figure 1 that it is necessary to delay the timing of both the "Not-row address strobe" (RAS*) signals and the "Not-column address strobe" (CAS*) signals to match the time lost in the various gates of the ALU. Also note that, to simplifying printing, a "Not-" symbol throughout the specifications and drawings is shown, not by the conventional overlying bar, but by a following asterisk.

The invention described and claimed herein is an improvement over the above discussed technique.

A plurality of semiconductor random access memory chips partials are assembled randomly on a printed circuit boards, tested, and a map of the defective areas in each is developed and converted into a table which is transferred into a nonvolatile memory component, a PROM, which then contains patterns that provide the map to direct the system to skip from defective address areas in the RAM to the locations of good bits or areas.

Certain types of memory components employ the same input lines to address both the rows and columns of the memory. The inputting device, such as a computer, may first apply a row address which is entered into the memory upon the occurance of a "row address" strobe signal (RAS) and then, a short time later, apply to the same shared input lines a "column address" which is entered into the memory upon the occurance of a "column address" strobe signal (CAS).

The specific technique employed by this invention takes advantage of two characteristics of semiconductor devices. First, there is an available time available between the application of the above mentioned row and column address strobe signals (RAS and CAS) to the DRAM that is quite adequate for translating a column address to a new mapped address by high speed PROMs without delaying or in any way affecting the CAS strobe signal at its proper time. Second, there are very fast PROMs available that have a large capacity and an eight bit output. The high PROM speed eliminates the need for an arithmetic unit and the delay circuits of the prior art system shown in Figure 1.The large capacity, high speed capabilities of currently available PROMs for translating addresses from defective to functional column locations during the short time period between the applications of row addresses and column addresses, coupled with the elimination of the prior requirement for arithmetic and delay circuits, therefore results in a semiconductor memory fault avoidance system that operates at full speed even while correcting the addresses from faulty to good areas in the memory.

In the drawings which illustrate the preferred embodiment of the invention: Figure I is a block diagram of a prior art fault avoidance system; Figure 2 is a block diagram of a commercially available large capacity semiconductor dynamic random access memory such as used with the invention; Figure 3 illustrates timing diagrams for a typical DRAM such as the memory of Figure 2; Figure 4 is a block diagram of the fault avoidance circuitry for addressing and correcting column addresses of the DRAM of Figure 3; Figure 5 is a sectional block drawing of a portion of the DRAM of Figure 2 and illustrates the translation from a defective bit position to a good position; Figure 6 is a block diagram of two groups of memory chips forming a large memory array with an 8-bit plus parity bit output; and Figure 7 is a block diagram of the fault avoidance circuitry for DRAM group selection and for addressing and correcting addresses in the DRAM array of Figure 6.

Figure 1 is a block diagram of the prior art circuitry for skipping defective areas to good areas in a dynamic partial memory, one having areas containing defective bit locations. In this system, memory addresses from an associated computer are directed to both an ALU 10 and a PROM 12 which had to be programmed to redirect addresses from known faulty locations to good areas in the associated memory array 14. As previously discussed, time lost in the gates of the ALU require compensation by time delaying the row address strobe input signals, RAS*, and the column address strobe input signals, CAS*, in delay circuits 16 and 18, respectively.While the required delays may be only 80 - 120 nanoseconds, the delay materially slows the memory access time and reduces and advantages of using partials and the translation circuitry for redirecting an address from defective to good areas in a memory chip. The present invention eliminates the delay circuits and redirects memory addresses with the normal access times so that the memory can operate at full speed while correcting addresses.

As previously mentioned, certain types of memory components employ addressing techniques which share the same input lines to address both the rows and columns of the memory. The memory illustrated in the block diagram of Figure 2 employes such a shared input and represents a commercially available 262,144 bit dynamic random access memory manufactured by Western Electric, as type 41256-17. The circuit chip of this DRAM is divided into four bit array groups 20,21,22,23. Seven row address lines, RADD-1 :7, are used to address one of 128 cell locations in each column of the four groups, and eight column address lines, CADD-0:7 address one of 256 in each horizontal row in all four groups. Each memory group contains 256 cells per row and 256 sense amplifiers which are coupled to the 256 column lines in each group.As best illustrated in the group 22, each of the 256 sense amplifiers is associated with two column lines 24, 25. Read and write signals from and to the memory are transmitted through selection circuitry including the one-of-two circuit 26 which,enabled by a row address signal RADD-0 or RADD-04F selects either the right or left line in each of the four groups. The four lines from the circuit 26 are then applied to a one-of-four selection circuit 27 which,enabled by two of the four possible states of RADD-8 and CADD-8 selects one of the four groups for connection to the read or write circuits, 28 or 29, respectively.

Figure 3 illustrates typical timing signals necessary for the operation of a DRAM such as that described above. The timing line 30 labelled ADDRESS indicates time provided for a nine bit row address, RADD-0:8, to be sent over the shared address lines to the memory device during the application of a row address strobe signal, RAS*, 31 as shown in line 32. A second nine bit column address, CADD-0:8, is later sent over the same address lines at CAS* time 33 on line 34 to complete the eighteen bit address needed to address a 256K memory device. Note that the asterisk following RAS and CAS indicate a NOT function and that the signals are active only when in the low states.

During the RAS* portion of an address cycle, the memory device will latch the address signals so that the same lines may later be used for the column address. At a predetermined later time, a column address strobe, CAS*, 33 is sent over another signal line to indicate that the signals on the shared address lines are now intended for column addresses. The memory device can then accept the column address and then continue the cycle to locate the selected bit at the junction of the row and column address thus to perform the read or write function at that location in accordance with the state of an applied WRITE signal, W* or W, as indicated in timing line 36 and applied to the read or write circuits 28 or 29, respectively, of the DRAM of Figure 2. A multiplexing signal is normally used ahead of the dynamic memory to direct the row and column addressing signal groups into the shared common address input lines. Thus, a cycle begins with a row address, RAD, and a row address strobe, RAS*, followed at a predetermined later time by a column address, CADD, and a column address strobe, CAS*, with both the row and column addresses normally being multiplexed to the dynamic memory over the same common set of lines in accordance with the state of a multiplex signal, TMUX* In the invention, the period of time extending from the beginning of the row address, RADD-0:8, 38 through a normal circuit settling time 40, and up to the column address, CADD-0::8, 41 in line 30, is utilized by a high-speed mapping PROM for translating the address of those DRAM columns containing bad memory cells or inoperative sense amplifiers to columns containing usable memory cells. System line 42 of Figure 3 illustrates the timing of such a column translation period 44 followed by the normal time period required to apply the corrected or translated address, CADD-0:8, 46.

In the fault avoidance circuitry to be described, this address translation period 44 may be in the order of 70 nanoseconds and this is very adequate for a high speed programmable ROM, such as a type 74LS5472, to perform the column address corrections and thereby permit the random access memory to operate at its normal speed.

Figure 4 is a block diagram illustrating the circuitry of the invention for addressing a "partial" DRAM. An associated computer employing the memory system provides an 18-bit address, 0-17, to a system address register 50 where it is separated into both rows address and column addresses. As illustrated, the nine addresses 0:8 in the register 50 are applied to a gated buffer 52 to be transmitted therefrom by a multiplexing signal, Thus, to the associated memory device over the nine output lines, A0:A8, and used as row addresses, RADD when enabled by a row address strobe (RAS) signal.The nine addresses 9:17, in the register are applied as column addresses CADD, to a high speed programmable read-only memory or PROM 54 which has been previously programmed to translate the column address of faulty columns in the associated memory device to the address of good memory locations. The translated column addresses are gated from the PROM 54 over the same nine output lines, A0:A8, by a multiplex signal Thus*, and received into the memory device during CAS time. Again, note that the asterisk denotes a "Not-" term similar to the conventional overlying bar.

The use of the gated buffer 52 and PROM 54 serve the input function of applying only one load on the address lines as well as the function of having tri-state outputs so that then multiplex the RADD and CADD addresses without requiring additional multiplexers.

In practice, the memory device or DRAM is first tested to determine whether it meets the specified criteria for a "partial" that is usable in the system.

The memory may have only a single bit failure or multiple bit errors in a single column such as those caused by a sense amplifier failure which, in the memory of Figure 2, may involve 256 memory cells or bits. In testing, any failure up to and including a quarter column is treated as a full quarter column failure and more comprehensive failures are treated as multiple quarter column failures which may equate to half or full column failures. Memory chips having no more than six quarter column failures are deemed to pass the test and are then assembled randomly on a circuit board, retested to map the location of those columns having defective cells, and the map converted into a table which is then transferred to the PROM.The table provides for the skipping of columns containing one or more bad memory cells or a faulty sense amplifier and translates the address of that faulty column to one have all good cells.

It will be noted that the programming of the mapping PROM 54 must match the specific memory device pattern. If the memory subsequently requires replacement in the field, the necessary service can be accomplished by replacing the defective DRAM with an "all-good" DRAM or, in the alternative, by creating a new PROM that has been programmed to match the new defective pattern Figure 5 illustrates a portion of a memory device such as one quadrant of the DRAM illustrated in Figure 3. If, for example, there is a bad bit in a column 56, or if the entire quadrant column is faulty because of a defective sense amplifier 58, the preprogrammed PROM map will substitute the address of a new column 60 where the corresponding bit on the same row is good. Thus, in Figure 5 a defective bit in the fourth column 56 may be re-addressed by the PROM to skip to the DRAM column 60.Normally, only 512 bits are skipped by each address substitution in a 256S DRAM.

The preceding description has been limited to the addressing of a single DRAM. In useful computer memory systems, many DRAM chips are often connected into an array to provide a larger addressing capacity and to provide multiple input' output streams of multi-bit bytes or computer words. Figure 6 illustrates such a multi-bit stream memory array comprising two groups 62, 64 of DRAM devices, each group containing nine DRAMs such as that illustrated in Figure 2 and providing eight bits plus a parity bit for data input/output operations.

In Figure 6 the addresses A0:A8 of all DRAMs are connected together and, at proper times, provide row addresses 0:8 and column addresses 0:8 to all DRAMs in a selected group. The data input line is shared with a data output line in each individual DRAM and the eight common or shared lines, D0:D7, plus the Parity line, DP, provide for the transmission of input/output signals from and to a 9-bit data bus. A desired one of the memory groups 62,64 is addressed by one of two applied signals identified as CAS-0* or CAS-1*, the origin of which will be subsequently described, together with a common row address strobe signal, RAS*, and a common read/write signal W or W*. As illustrated in Figure 6 the DRAM groups are selected by a RAS* signal together with a CAS-0* signal for group 62 and together with a CAS-1* signal for selecting group 64.If desired, it is permissible to activate the groups with a CAS* signal and to select a particular column by the application of a RAS-O* and RAS-1*. The development of these strobes signals will be subsequently described.

Figure 7 is a block diagram illustrating the fault avoidance circuitry for the selection of a memory group, for translating column addresses and for providing proper timing signals to the DRAM array of Figure 6.

Since the DRAM chips employed in the preferred embodiment require nine row and nine column addresses over shared input lines, the correction circuitry of Figure 7 requires 19 address input lines, 0:18, from the associated computer: nine row ad dress lines, nine column address lines, and an additional line for the development of the strobe signals, CAS-0* and CAS-1*, that is used for the selection of the DRAM groups 62 or 64 of Figure 6.

In Figure 7 the 19 address input lines from the computer are presented to a systems address input register 66. It has been arbitrarily assumed that a DRAM partial will have most of the faulty memory cells concentrated in a few columns because of the possibility of inoperative column sense amplifiers, and the associated fault avoidance circuitry of Fig ure 7 must therefore translate only the column ad dresses. If desired, the input assignments may be reversed and row addresses may be translated into non-defective areas of the memory chip.

As described in connection with Figure 4, the nine address input lines 0:8 in the register 66 are applied to a tri-state buffer 68 for gating at time TMUX to the selected DRAM group. In the preferred embodiment a type 74LS244 tri-state buffer is used to pass the eight row addresses 1:8 in the input register 66 to the eight row address outputs Al :A8.

The ninth row address, A0, is obtained by gating the lowest order, or zero, input address register bit through one section of a separate type 74LS125 tri state quad buffer 70. It is preferred that input regis #ter bit, i0, is used for providing the row address, A0, to insure DRAM chip refreshing, which occurs on row addresses, RADD-0:7, during RAS* time.

The tenth bit, position 9 in the input register 66, is coupled into one input of an OR gate 72, and also through an inverter 74 to one input of a second OR gate 76. The second inputs of both gates 72, 76 are coupled to a system timer 78 and re ceive therefrom the strobe signal, CAS*. The OR gate 76 generates the DRAM group selection signal CAS-0*, and the gate 72 generates the selection signal, CAS-1*, both of which were discussed in connection with Figure 6. Thus, when the input register bit in position 9 is high, CAS-1* will be active and will enable DRAM group 64 of Figure 6; when input register bit 9 goes to its low state, CAS-O* becomes active and enables the DRAM group 62.Note that the system will cycle through all the row addresses, first of group 62 and then group 64, before advancing to the next column address which are presented on the nine input register locations 10:18.

The PROM 79 used in the preferred embodiment for the translation of column addresses is a high speed 512 word of 8-bit PROM, type S472, having eight output lines and coupled to receive from input register 66 locations, 10:18, the nine binary in put bits required for translating 512 8-bit words.

The nine binary column address bits admitted to the PROM 79 from the input register are translated into eight of the column addresses of good bit locations in the following DRAMs and are gated to the eight address terminals, A1-A8, by the application of a Thus* signal, and into the CADD inputs of the DRAMs at CAS* time.

The ninth bit of the DRAM column address, A0, is obtained by gating the bit in input register position 10 through one section of a type 74LS125 tristate quad buffer 80 by the application of the Thus' signal. The signal on this input register position is the lowest order bit of the column address and is used as a DRAM chip address A0 to insure the best random distribution of chip faults since the likelihood of adjacent localised failures is greater than the likelihood of failures in different quadrants of the DRAM chips.

In a computer system, there are usually several memory boards and it is therefore necessary to provide signals so that each board may be selectively activated when required. The preferred embodiment of the invention therefore includes a timing circuit 78 which is responsive to the system clock and to a timer selection signal, SEL, and which produces the correctly timed output strobe signals, RAS*, CAS*, to the associated DRAM chips, and the multiplexing signal Thus*, that alternatively transfers the contents of the row buffer and translating PROM to the AO-A8 chip addressing terminals. The circuitry also receives from the associated computer a Read/Write signal which is applied directly through a buffer 82 to provide the read and write signals, W and W*, to the DRAM chips.

Claims (23)

1. A method for translating the addresses from faulty memory cell locations to functional bit locations in a partially defective semiconductor memory having row input lines and column input lines, said method comprising the steps of: testing the partially defective memory to determine the location of faulty memory cells therein; tabulating said determined locations of faulty cells into a map that translates an address of each column containing a faulty cell into a map address of a column containing good cells; storing said map into a non-volatile memory device that receives at its input column address signals from an associated input device and which transfers said map address to the column input lines of said partially defective memory upon the application of the first state of a gating signal having a first and second states; and providing a gated buffer register for receiving row address signals from said associated input device and for transferring said row address signals to the row address input lines of said partially defective memory upon the application of the second state of said gating signal.

2. The method claimed in claim 1, wherein said partially defective memory employs shared row and column address input lines and receives into the memory from said shared input lines said row address signals during the application of a row enable signal and said column address signals during the application of a column enable signal, said row and column enable signals being alternately applied during one cycle of operation of said partially defective memory.

3. In combination with a semiconductor memory array having partially defective components and having shared input lines for admitting to said memory array row and column addresses upon alternately applied row and column enabling signals and avoidance circuitry interposed between an associated addressing input device and said memory array, said error avoidance circuitry comprising; first means for receiving from the associated addressing input device a portion of a memory address signal group representing a row address signal group and for transmitting said row address group to the shared input lines of said memory array during the first period initiated by the application of a first state of a multiplexing signal having first and second states;; programmable means for receiving from said associated addressing input device during said first period a portion of a memory address signal group representing a column address signal group, said programmable means having been programmed, after the testing of the memory partial, to convert the input address signal groups of columns containing a faulty memory cell to map output addresses of columns in said partially defective memory containing functional cells said programmable means transmitting said map addresses to said shared input lines during said second period initiated by the second state of said multiplexing signal.

4. The error avoidance circuitry claimed in claim 3, wherein said first means is gated buffer circuitry having a plurality of buffer stages corresponding to the number of signal bits in said row address signal group, and said programmable means is a programmable read-only memory programmed to convert column input addresses into map addresses of columns in said memory array that contain a functional sense amplifier and functional memory cells.

5. The error avoidance circuitry claimed in claim 3, further including timing circuit responsive to a system clock signal for generating said multiplexing signal, a row enabling signal, and a column enabling signal for said memory array and said avoidance circuitry.

6. The error avoidance circuitry claimed in claim 5, wherein memory array is one of a plurality of memory arrays in one of at least two groups of memory arrays for providing multi-bit parallel output signals and wherein said error avoidance circuitry includes means for enabling a selected one of said groups, said enabling means comprising, a first gate responsive to a selection signal at a group selection terminal of said associated addressing input device and to the column enabling signal of said timing circuit for generating an out put signal for enabling a first one of said groups, and a second gate responsive to the inverted state of said selection signal and to said column ena bling signal for generating an output signal for enabling a second one of said groups.

7. The error avoidance circuitry claimed in claim 4, wherein said gated programmable memory receives row addresses from said associated addressing input device and is programmed to skip from the addresses of rows containing faulty memory cells to the addresses of rows containing functional memory cells and transmits the map addresses therefrom to said shared input lines for entering into said memory array upon the application of a said row enable signal, and wherein said gated buffer circuitry receives column addresses and transmits them to said shared input lines for entering into said memory array upon the application of said column enable signal.

8. In a random access memory array in which an address signal group includes a first portion applied at a first period of time to said memory array and a second portion applied at a second period of time to said memory array, the method of addressing said memory arrays comprising the steps of: identifying defective memory array component sections in relation to said second address signal group; and altering said second address signal group portions during said first period of time to address functional memory array component.

9. The method of addressing a random access memory array claimed in claim ô, wherein the first step relating to identification of defective memory arrays components includes the step of storing functional memory array sections in a memory unit address by defective memory array component section first portion address signal groups; and wherein the second step includes applying said defective memory array component section first portion address signal group to said memory unit.

10. Apparatus for avoiding defective sections in a memory array comprising: addressing means for applying a first portion of an address signal group to said memory array during a first period of time and for applying a second portion of said address signal group during a second period time, and translation means for providing a second portion addressing a functional memory array section in response to a second portion addressing a defective memory array section.

11. The defective section avoidance apparatus claimed in claim 10, wherein said translation means includes a memory for providing said second functional portion in response to said second defective portion.

12. The defective section avoidance apparatus claimed in claim 10 wherein said memory array is comprised of dynamic random access memory elements.

13. A memory array module comprising: an array of memory elements; means for receiving an address signal group; means for applying a first portion of said address signal group to said array during a first period of time; means for applying a portion of said address signal; means for substituting a third portion for said second portion for application to said memory array during said second period of time when said second portion addresses a section of said memory array having at least one defective element.

14. The memory array module claimed in claim 13, wherein said memory elements are comprised of dynamic random access components.

15. The memory array module claimed in claim 13 wherein said first portion addresses preselected rows of said memory array and wherein said second and third portions address predetermined column of said memory array.

16. The memory array module claimed in claim 13, wherein said array of memory elements is comprised of a plurality of memory elements.

17. In a memory system in which a first portion of an address signal group is applied to a memory element array during a first period of time and a second portion of an address signal group is applied to said memory element array during a second period of time; the process for avoiding defective portions of said memory element array comprising the step of: substituting second address portions addressing functional memory array elements for second address portions addressing defective memory array elements prior to said second period.

18. A method for translating address locations in a semiconductor memory substantially as hereinbefore described with reference to Figures 3 to 7 of the accompanying drawings.

19. Error avoidance circuitry substantially as hereinbefore described with reference to Figures 3 to 7 of the accompanying drawings.

20. A random access memory array substantially as hereinbefore described with reference to Figures 3 to 7 of the accompanying drawings.

21. A method of addressing a random access memory array substantially as hereinbefore described with reference to Figures 3 to 7 of the accompanying drawings.

22. Apparatus for avoiding defective sections in a memory, substantially as hereinbefore described with reference to Figures 3 to 7 of the accompanying drawings.

23. A memory array module substantially as hereinbefore described with reference to Figures 3 to 7 of the accompanying drawings.