JPS61104499A - Apparatus and method for avoiding defect in semiconductor memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates generally to semiconductor random access Fujiviator memory arrays, and more particularly to semiconductor random access Fujiviator memory arrays that generally require the manufacturer to reject and discard the device. The present invention relates to a novel circuit that enables the use of memory devices having defective pit locations.

(Prior Art) In the manufacture of semiconductor circuit chips, there are many "good" chips and many "bad" chips on one wafer. Many of the so-called defective chips have only seven or a very small number of defective components. Chips or "partials" with such defective components can be purchased from manufacturers at very low cost and used in circuits that do not require the defective component within the chip. For example, Western Electric has a 2-bit memory capacity.
In a high profile dynamic random access memory (DRAM) chip such as the model number W CM ll/, 2 tallow/li chip from RIC), the total number is 26 = 7.
Even if there are 7 defective bits out of 94, the entire chip becomes defective, and unless there is a circuit that can use these chips, the entire memory chip becomes scrapped.

In the late 1990s, the inventor developed a method for using partials (partially defective memory chips) in memory devices. This method can be applied to Iliatsuk (
ILLIAc) IV This was demonstrated using the main memory defect. In this method, the partial chips are tested, sorted, and sorted into 76 groups. That is, the defective pit locations in a particular group are concentrated within a space that is 76/76th of the addressing space. A printed circuit board, one area for each of the above princes/
The 77th uses the AM area and chips that are all good quality.
It was designed to have a second area. bypassing the address of the defective area in the group of partials and replacing it with an equivalent good area at the same chip address as above in the group of 17th defects;
The addressing device was designed in hardware.

Since the first memory described above using partially defective, chipped semiconductor circuit chips, other memories have been designed using this basic method. That is, the two of them consist of
+'s / was skipped, others skipped 7's / or g's /, and others skipped 76's /.

Another method for using partials in memory devices is to randomly insert caged chips into a printed circuit board and test them this time, noting where the defective pits and areas are. Matupu J
made. This map was translated into logic elements in the addressing device, and when the associated computer sent the address to memory, this address was sent to the map as a map address. A known good memory bit or memory area is stored at that location in the above map.
This map address was accessed and used as an alternative address for those called by the computer.

A variation of this map-type address pointing method is to store a map of a portion of the memory address space in non-volatile memory, and then transfer the value of the data contained in this mapped location to the original computer address (assigned). The data group thus created is used as an address for a good pit or area. In this method, an arithmetic unit or microprocessor and a non-volatile memory are used. When a zero is stored in the above map, the above memory is addressed at its original good location. If non-zero, the increment stored in the map is appended to the address to convert it to a good bit or region location. .

A block diagram of this conventional method of skipping from a defective memory location to a good area is illustrated in Figure 1.
Addresses from the external microprocessor are received and sent to the arithmetic unit and mapping PR, OM.

The FROM is preprogrammed to store the incremental amount required to convert an address from a defective bit location in the memory array to a good bit or region location. An address sent to FROM in this manner causes an access and the value stored at that location in the PROM is sent to the arithmetic logic unit R (ALU). In FIG. 1, the "non-row address strobe" (RAS half) signal and the "non-column address strobe J
It is necessary to delay the timing of the (CAS) signal to accommodate the time losses in the various f-) of AI-IJ. In order to simplify the description, the notation "Non..." is used in the specification and drawings of this application, and the symbol is indicated by an asterisk added later, instead of using the usual bar line above it. It is.

(Problems to be Solved by the Invention) The present invention seeks to provide a device and method that are improved over the conventional methods and devices described above.

(Means for Solving the Problems) In the present invention, a plurality of semiconductor random access memory chips or chips are randomly assembled on a printed circuit board, tested, and a map of defective areas within each is created. and transmitting the table into a non-volatile memory component, PROM. Therefore, the above FRO
M must contain a Z-turn that provides a map for instructing the device to skip from a defective address area to a good bit or area location in RAM.

Some types of memory components can be connected using the same input line.
addresses both the row and column of the file.

An input device, such as a computer, first provides a row address, which address is triggered by a "Row Address" strobe signal (
RAS) is entered into the memory as it occurs. Then,
The input device, after a short time, provides a ``column address'' on the same shared input line as above, which address is entered into the memory upon the occurrence of the ``column address'' strobe signal (CA!3).

The method of the present invention utilizes two characteristics of semiconductor devices. First, there is limited available time available between the application of the aforementioned row and column address strobe signals (RAS and CAS) to the DRAM; It is perfectly sufficient to translate the column address into a newly mapped address by the high speed FROM at the appropriate time without giving any shadows. Second, an extremely fast FROM with large capacity and g-bit output can be utilized.
The need for the arithmetic unit and delay circuit of the conventional device shown in the figure is eliminated. During the short period between the application of the row address and the application of the column address, the fault location 7.
As a result of the large-capacity, high-speed capabilities of OM and the elimination of the need for arithmetic units and delay circuits that were previously required, addresses can be corrected from defective areas in memory to non-defective areas while still being able to operate at full speed. A semiconductor memory defect avoidance device that operates in the following manner was obtained.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to embodiments thereof and the drawings.

Embodiment FIG. 1 is a block diagram showing a conventional circuit for converting a defective area into a good area in a dynamic partial memory having a defective bit location. In this circuit, memory addresses from the associated computer are directed to ALUIO and PR,0M12. The ALU and PROMFi are preprogrammed to redirect addresses from known defective locations to good areas within the associated memory array 14. As mentioned above, the time loss in the ALUCI dart is caused by the time delay of the row address strobe input signal RA S'' and the column address strobe 1 input signal CAS in the delay circuits 16 and 18, respectively. Although the required delay is only gO~720 nanoseconds, this delay significantly slows down memory access times, and using nocucials and addressing This reduces the benefit of using translation circuitry to redirect memory addresses from defective areas to good areas within the memory. This, however, allows the memory to operate at full speed while correcting addresses.

As previously mentioned, some types of memo IJ a component are
An addressing scheme is used that shares the same input lines to address rows and columns of memory. The memory shown in the block diagram of FIG.
, this memory is manufactured by Western Electric (WES
ternεIectr Ic) company is model number 4L/2!
Commercially available 21,.rl,-/7. 2. /
'I'l pit dynamic random access memory (DRAM). The circuit steps of this DRAM consist of q bit array groups 20, 21, 22 .
It is divided into 28 parts. Seven row address lines RADD7/:7 are used to address one of the /2r cell locations in each column of these t groups, and the column address, JCADD-0 near, is The whole group'! Address one of the 23 in each horizontal row in the AK. Each memory group has 236 cells and 256 sense amplifiers per seven rows, which are connected to the 256 column stripes within each group. As shown in group 2z, each of the two sense amplifiers is associated with two column lines 24,25. The solicitation and write signals to and from the memory are routed through an address selection circuit 26 which selects one of the row address signals RADD-0 or RADD.
- Enabled by door to select the right or left line abbreviation in each of the above groups. The nine lines from circuit 26 are connected to a selector circuit 27 which selects seven of the lines, and said circuit goes to RA['ID- and cAoo-
is enabled by one of the q possible states of f and selects one of the q groups to read out the circuit 2.
8 or write circuit 29.

Typical timing signals required for operation of a DRAM such as those described above are shown in FIG. [Address J (ADD
Timing line 80, labeled RESS), is line 82.
Row address strobe signal (RAS”) 3 as shown in
1 indicates that a given time R'ADD-0:g for a 9-pit row address is sent to memory on the shared address line while a 1 is being given. The second 9-bit column address CADO-0:g is then applied to CAS on line 84.
88 U.S. time and is sent on the same address line as above,
Complete the 7g pit address needed to address the memory device at 2.5″6. The asterisk appended after RAS and CAS indicates “non” functionality;
Also, the signal is active only when in a low level state.

During the RAS of an address cycle, the memory device latches the address signal so that the same line can be used for subsequent column addresses.

At a predetermined time thereafter, the column address strobe (C
A") 33 is sent on the other signal line to indicate that the signal on the address line for # is now for the column address. The memory g tr< then accepts the column address and then starts this cycle. Continuing, the selected bit can be located at the junction of the row and column addresses, as shown in timing line 86 and readout circuit z8 of DRA F/1 in FIG. Alternatively, depending on the state of the applied write (WRITE) signal vt' or W applied to the daytime circuit z9, the read or write status at that location can be performed.Usually, a multiplexed signal is used before the dynamic memory. , thereby directing the row and column addressing signals to a shared common address input line.Thus, one cycle includes row address RADD and row address strobe RA.
Starting with S, followed after a predetermined time by column address CADD and column address strobe CAS, each of these row and column addresses is typically stored in dynamic memory in the same common B4 field according to the state of multiplexing signal TMUx. Multiplexed.

In the present invention, on line 81, the row address (RA
Column address (CADD-0:g) 41 from the beginning of DD-0:g) 88 through normal circuit settling time 40
The period extending up to 100 ms is utilized by the fast mapping FROM to translate the address of a DRAM column containing a defective memory cell or inactive sense amplifier to a column containing a usable memory cell. The system line 42 in FIG.
D-0:, followed by the normal period required to apply 46. In the defect avoidance circuit described below, this address translation period 44 is on the order of 70 nanoseconds, which provides column address correction and allows the random access memory to operate at its normal speed. For example, model number 7! LS! 4t72
It is extremely suitable for high-speed grog maple ROMs such as ROM.

Figure 1 is a block diagram illustrating a circuit of the present invention for addressing partial JDRAM.
The address 0:/7 is applied to the system address register 50 where it is divided into a row address and a column address. As shown, the nine addresses 0:g in register 50 are applied to an r-ted buffer 52 from which, by means of a multiplexed signal T, 9LJX outputs 19AQ:Ag are applied to the associated memory devices. and row address strobe (RAS)
When enabled by the signal, the row address RADD
used as. 9 addresses 9 in the register above
:/ is provided to the high speed programmable read only memory or PROM 54 as the column address CADD. The FROM is preprogrammed to translate the column address of a defective column in the associated memory device to the address of a good memory location. The translated column address is gated out of the PROM 54 by the multiplexing signal "MUX*" on the same nine output lines AO:Af as above, and is received into the memory device during CA3 time.

Again, the asterisk is similar to the usual bar above the
...indicates the word publication.

The use of gated buffer 52 and PROM 54 provides the function of providing only one load to the address line and having a tri-state output, which eliminates the need for an additional multiplexer for the RADD address line. and CA()D addresses can be multiplexed.

In practice, a memory device or DRAM is first tested to determine whether the DRAM complies with prescribed criteria for usable "partials" within the device. Such memories have, for example, only a single bit defect or multiple pit errors, such as those caused by sense amplifier defects, within a single column. The memory, for example, in the memory of FIG. 2, has S memory cells or bits. In the exam,
Defects of less than 1 row are treated as % full row defects, and defects larger than 1 row are treated as defects in multiples of 3 row defects, such as half row defects or full row defects.

Memory chips with six times or fewer defects in the y column are considered to have passed the test, and then randomly assembled on the circuit board and tested again to map the location of the column with defective cells. This map is then converted to a table, which is then transferred to the PROMK. The above table is created for skipping columns with seven or more defective memory cells or defective sense amplifiers, and translates the address of this defective column into an address with all good cells.

Mapping FROM 54 programming must conform to a defined memory device pattern. memory,
If it later becomes necessary to replace the defective DRAM in the field, the required service is to replace the defective DRAM with a ``all good'' DRAM.
Either replace it with RAM or write a new FROM that is programmed to match this new defect pattern.
It is to create.

FIG. 5 shows a portion of a memory device, such as the seven quadrants of DRAM shown in FIG. For example, a bottle base that has a defective pit in column 56 or an entire quadrant column defective due to a defective sense amplifier 58 may have a reprogrammed FROM map with a corresponding value on the same order of magnitude. The pit replaces the address of the new column 60 which is good. That is, in FIG. 3, a defective pit in column 56 is addressed by the FROM and skipped to column 60 of the DRAM.

In general, each address permutation in 2 A; is K D RA tA causes only D=&/2(i! pits to be skipped.

The above description is limited to single DR+%M addressing. In a useful computer memory device, a large number of DRAM chips are connected together into an array, thereby increasing addressing capacity and providing multiple input/output streams of multi-bit bytes or computer words. is often performed. 6th
The figure shows a multi-bit stream memory array as described above comprising one group 62.154 of DRAM devices, each group having nine DRAMs as shown in FIG. Provides t pits and one parity pit for output operation.

In FIG. 6, the addresses of all DRAMs are connected together, and at the appropriate time all DRAMKs in the selected group have row addresses 0:g and column addresses O.
: Provide g. The data input line is shared with the data output line in each individual DRAM, and the common or shared line 00:0 and parity line OP carry out the transmission of input/output signals to the 9-pit data bus. It has become. A desired one of the memory groups 62, 64 is CAS
- or c AS-(lk), which are addressed by one of the two applied signals, denoted by λ; for the sources of said signals, a common row address strobe signal RA S'' and a common read/write signal This will be explained later along with W or -.

As shown in FIG. 6, the DRAM group receives the RAS" signal,
Selected by the CAS-door signal for group 62 and the cAs-(lk multiplication signal for selecting group 64.If necessary, activate said group with the CAS signal and select RAS-〆 or RA3-( A specific column can also be selected by applying an ik multiplied signal.Generation of these STRO-1 signals will be explained later.

FIG. 7 shows the D of FIG. 6 for selecting memory groups, for translating column addresses, and for appropriate timing signals.
FIG. 2 is a block diagram illustrating a defect avoidance circuit for providing a RAM array.

Since the DRAM chip used in this example requires 9 rows and 9 columns of addresses on the shared input line, the correction circuit of FIG. 7 requires 79 address inputs 1111ilo:ig from the associated computer. shall be. namely, nine row address lines, nine column address lines, and seven more lines for generation of strobe signals CAS-- and CAS-/', this latter line being the sixth line. It is used to select the DRAM group 62 or 64 in the figure. In FIG. 7, the 79 address input lines from the computer are connected to a system address input register 66. −
If I could give you an example. [)RAM/#--The chassis is concentrated within the column of number (II) due to the occurrence of inactive column sense amplifiers, and the defect avoidance circuit of FIG. Only the following will be translated.

If desired, the input assignments may be reversed and the row addresses translated to non-defective areas of the memory chip.

As discussed with respect to FIG. 9, the nine address input lines o:g in register 66 are connected to tri-state buffer 68 for darting UX at time T for the selected DRAM group. In this example, model number 74 L, S 2'll
g row addresses in the input register 66 /:g''!tI!i'
The row address output terminals A/:Ag are made to pass through. The 9th row address AQ sets the lowest order or zero input address register bit to a separate type 4
7! LS/, 2! r) Right state quad buffer 70
Obtained by darting through one area of . To ensure refresh of the DRAM chip, the R.A.
Input register bit # to provide row address AO occurring on row address RADD-0:7 during time S”
Preferably, 0 is used.

10th bit in input register 66, position 9
is connected to one input terminal of the 0Rf-door 2 and to one input terminal of the third OR date 76 via the imper-tuff 4I. ? -) The 82 input terminals of 7z and 76 are connected to a system timer 78 from which they receive the strobe signal CAS. 0Rf-476
generates the DRAM group selection signal CAS-/p, r-47
2 generates a selection signal c As -7''k. Both selection signals were described above with respect to FIG.

Therefore, when the input register bit at location 9 goes high, the CAS-bar becomes active 9 and the DRA of FIG.
MRAM total 64-bit. input register bit 9 power 5
When it goes to a low level state, the CAS becomes active and all 62-bit DRAM RAM is disabled. The canopy cycles through all row addresses, first in group 62 and then in group 64, and then advances to the next column address located on the nine input register locations io:ig.

The body of the column address (P used in this example for translation)
ROM79 is a high-speed evening/2 candy g-bit FROM, model number'
172, which has g output lines and is connected to receive from locations 10:7g of input register 66 the nine binary input bits necessary to translate the 572 g pit words. ing. PR from the above input register
The nine binary column address bits given to OM79 are:
The column address of the location of a good bit in the subsequent DRAM is translated into one of the column addresses, and is connected to the address terminal A/:Ag by application of the MLJX signal, and the CAS time open time is applied to the DRUM. CA of
Enter the DD input terminal.

The ninth bit AO of the DRAM column address is “ML
Applying the IX*- signal sets the bit in position 10 of the input register to type 74tLS/2! is obtained by gating K through one area of the tri-state quad buffer 80; The signal on this input register location is the lowest order bit of the column address and is used as the DRAM chip address AO to randomly distribute the chip defects. That is, the probability of adjacent local defects is greater than the probability of defects within different quadrants of the DRAM chip.

In computer systems, it is common to have several memory disks, and it is therefore necessary to provide signals so that each disk can be selectively disabled as needed. Accordingly, this embodiment of the invention includes a timing circuit 78 which is responsive to the system clock and timer selection signal SEL and is properly timed for the associated DRAM chip. Output strobe signal RA
S'.

CAS, and generates a multiplex signal “MUX”, which multiplexes the row buffer and translates the contents of the ROMO
: Transfer alternately to the Ag chip address designation terminal. The circuit also receives read/half-load signals from the associated computer. This signal is applied directly through the buffer 82, and the offset and write signals W and - are applied to the DRAM chip by 6°.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional defect avoidance device, and FIG. 2 is a block diagram of a conventional commercially available large-capacity semiconductor dynamic random access memory as used in the present invention.
3 is a timing diagram for a typical RAM such as the memory of FIG. 2; FIG. 7 is a block diagram of a defect avoidance circuit for addressing and correcting the column address of the DRAM of FIG. 3; The figure on the left shows good quality 1 from the defective bit position.
A cross-sectional block diagram of a part of the DRAM shown in FIG. 2 shows the translation to the office, and FIG. 7 is a block diagram of the DRAM group selection and defect avoidance circuitry for addressing and correcting addresses within the DRAM array of FIG. 6; FIG. 66...--System address input reno star, 68.
-... Tri-state buffer, 70.80...
... Tri-state Katno 9 Sofa, 72,
76 ----OR dart, 74... Inverter, 78... System timer, 79 ----F ROM. 82...Buffer. Figure 5 Figure 6

Claims (1)

Claims: 1. An apparatus for avoiding defective areas in a memory array, comprising: for applying a first portion of a group of address signals to the memory array during a first period; addressing means for applying a second portion of said group of address signals during the period; and a second portion for addressing the functional memory array in response to the second portion for addressing the defective memory array area. A defect avoidance device characterized by comprising: translation means for providing. 2. a first portion of the group of address signals is applied to the array of memory devices during a first period, and a second portion of the group of address signals is applied to the array of memory devices during a second period; In the method for avoiding a defective portion of the memory element array in a memory device having a functional memory device, prior to the second period, a functional memory A defect avoidance method comprising the step of replacing a second address portion that addresses an array element.