WO1986002214A1 - Amplificateur haute frequence - Google Patents

Amplificateur haute frequence Download PDF

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Publication number
WO1986002214A1
WO1986002214A1 PCT/JP1985/000541 JP8500541W WO8602214A1 WO 1986002214 A1 WO1986002214 A1 WO 1986002214A1 JP 8500541 W JP8500541 W JP 8500541W WO 8602214 A1 WO8602214 A1 WO 8602214A1
Authority
WO
WIPO (PCT)
Prior art keywords
emitter
circuit
frequency
amplifier
grounded
Prior art date
Application number
PCT/JP1985/000541
Other languages
English (en)
Japanese (ja)
Inventor
Akira Usui
Tadashi Yamada
Kazuhiko Kubo
Hiroyuki Nagai
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP20581684A external-priority patent/JPS6184104A/ja
Priority claimed from JP3200285A external-priority patent/JPS61192106A/ja
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Priority to DE3590480A priority Critical patent/DE3590480C2/de
Publication of WO1986002214A1 publication Critical patent/WO1986002214A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/191—Tuned amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/083—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only

Definitions

  • the present invention relates to a high-frequency amplifier used for amplifying a high-frequency signal in a television tuner circuit, a satellite broadcast receiver, and the like.
  • a multistage connection circuit of an emitter-grounded amplifier as shown in FIG. 1A is often used to obtain a high gain.
  • the high frequency signal is supplied than the input terminal 1 N, is amplified two stages by the preparative transistor and Q 2, are outputted Ri by an output terminal OUT.
  • L G 1 In order to Wa Lee Ya Ichii Ndakutan scan L G 1 by grounding the emitter jitter of ⁇ to the ground of the ic is present, Ri and grounding potential instability of the circuit, L G 1 is one Although there was no problem, the multistage connection had the disadvantage that the oscillation state could not be removed.
  • An object of the present invention is to provide a high-frequency amplifier capable of obtaining a stable operation in which an oscillation phenomenon occurs in such a multi-stage connected high-frequency integrated device.
  • Another object of the present invention is to provide a high-frequency amplifier capable of easily performing steepening of band characteristics and phase shift operation.
  • Another object of the present invention is to provide a high-frequency amplifier capable of improving the gain without increasing the number of elements and current consumption.
  • Still another object of the present invention is to provide a high-frequency amplifier capable of eliminating image disturbance with a simple configuration.
  • the high-frequency amplifier according to the present invention uses a grounded emitter amplifier directly.
  • An integrated circuit consists of at least two-stage circuits connected by current junction, and the emitter of the second-stage amplifier is connected with an emitter resistor between the ground and the two-stage amplifier. Out of the integrated circuit through at least one emitter of the eye amplifier through the integrated circuit bonding wire
  • a filter circuit including the inductance of the bonding wire is formed between this terminal and the ground, and a specific frequency is applied to the integrated circuit by this filter circuit. It is grounded outside to prevent feedback by the above-mentioned emitter resistance and to increase the gain.
  • FIG. 1 A, B and C are circuit diagrams of a conventional high-frequency amplifier
  • Fig. 2 is a circuit diagram of a high-frequency amplifier according to an embodiment of the present invention
  • Figs. 3 and 5 are devices of Fig. 2
  • FIG. 4 is a specific circuit diagram of the filter circuit 12 in FIG. 2
  • FIG. 6 is a block diagram of a high-frequency amplifier according to another embodiment of the present invention
  • FIG. The figure is
  • Fig. 6 is a specific circuit diagram of Fig. 8
  • Figs. 8A and 8B are specific circuit diagrams of the filter circuit 25 in Fig. 7
  • Fig. 9 is a block diagram of a converter using a high-frequency amplifier as a first intermediate frequency amplifier. click view, the 1 O diagram block diagram of a converter for solving the structure of the drawbacks of Fig. 9, first 1 FIG specific circuit diagram of a main part of the 1 O view, first 2 FIG part 1 1
  • Fig. 13 is a characteristic diagram of a 20-pass circuit
  • Fig. 13 is a characteristic diagram of a band-pass filter using a surface acoustic wave filter
  • Figs. 14A and B are circuit diagrams showing another example of a trap circuit.
  • FIG. 2 shows an embodiment of the present invention.
  • the wave amplifier includes an integrated circuit chip, a package, and a bonding wire connecting the chip and the package.
  • Ic in the figure has a pin configuration, and a wire-inductance formed by a bonding wire is formed between each pin and a terminal of the package. In the figure, it is due representation in ⁇ L T this by an equivalent circuit.
  • the wire inductance is usually about 2.5iiH to 5nH, though it depends on the thickness and distance of the wire.
  • An input signal is supplied from an input terminal IN, supplied to a terminal ⁇ ⁇ through a coupling capacitor, and further transmitted through a wire inductance 1 ⁇ to an amplifying device which is a grounded-type amplifier in an integrated circuit.
  • E mission-Tagachi Tsu is: connected to the inner ground, Chi Tsu blanking in the ground is connected to the terminal 2 through Wa Lee Ya uniquely inductor Nsu L 2, is further connected to the external ground.
  • the collector of the Matato La Njisuta Q 1 is load resistance! ⁇ Through the Dzu it is connected to the regulated electric ffi v cons t Rai down in the chip.
  • the signal amplified by the transistor is output from the collector to a terminal ⁇ through a line inductance 1 ⁇ 3 , and further supplied to a terminal ⁇ ⁇ ⁇ ⁇ through an external filter circuit 12.
  • ya - is supplied to the base of the inductor Nsu 1 »4 for amplifying an emitter jitter grounded amplifier via preparative transistor Q 2.
  • the high-resistance 2 is supplied to the base of the inductor Nsu 1 »4 for amplifying an emitter jitter grounded amplifier via preparative transistor Q 2.
  • Collector DOO lunge Star Q 2 is connected to the regulated voltage V const line via a load resistor 6.
  • the collector of transistor Q 2 is Is connected to the terminal 3 through Yai inductor cis L 6, is supplied to the outside through the capacitor C 3 for binding.
  • Emi jitter of capital transistor Q 2 is divided into three directions. Its one direction by terminal 5 through Wa Lee Yain Dakutan are grounded to an external ground through a capacitor C 2 and the resistor R 20 for damping the resonance.
  • the second direction is connected to the ground in the chip via the resistor 3 , and the third direction is the potential divided by the resistors R 14 and R 15 .
  • the transistors 0 and Q 2 are configured so as to provide DC negative feedback.
  • the on-chip stabilization voltage V eonst is determined by the transistor Q 3 and the resistor
  • the here bets la Njisuta the collector, a current flows through the by-stabilized voltage Vconst line resistance i, the current is diverted to the base of the preparative run Star Q 2.
  • the bets transistor Q single collector, stabilized voltage V c. current is supplied through the ns t La Lee down by resistance R 1 2.
  • the city of La Njisuta Q 2 E Mi jitter, the sum current of the current flowing through the base current and resistance 6 of the capital La Njisuta Q 2 Flow through the resistor R 1 3, to flow to the ground (GND), the potential determined by the product of E Mi jitter current bets run-register Q2 through the resistor 1 ⁇ 3 and the value of the resistor 11 13 is generated.
  • the input signal is amplified by preparative run-register, Q 2, has can be the preparative La Njisuta Q 2 of E Mi jitter resistor R ⁇ j 3 to high frequency to obtain a gain . Therefore, where the preparative run-to ⁇ the filter over circuit 1 1 between register 0 2. E Mi Ttayo ground, to reduce the feedback amount of frequency specific., To stabilize the circuit operation I have. Note that the resistor R 15 in the figure is inserted to adjust the amount of direct current fed back by the collision R 14 .
  • bonding wires Nsu L 2, L 5 is small and also that it not only allows one. Therefore, in this example, the stability of the circuit is ensured by taking a means for removing one of the wire inductances 1 and 5 . It established the full I filter first circuit 1 1 to urchin outside IC Pas Tsu cage by the illustrated, to resonate with the word i ya unique Ndaku data Nsu L 5, to have a function of absorbing Wa Lee Ya Ichii inductance component I have.
  • the effect of the emitter resistance o is eliminated.
  • the 3 ⁇ 4 characteristic as shown by the broken line B in FIG. 3 can be obtained, and the gain in the low frequency band can be suppressed.
  • the second special feature of the circuit of FIG. 2 lies in the resistor R 12 and the filter—circuit 12.
  • the high-frequency amplifier shown in Fig. 2 needs to have a sharp band characteristic, and when a feedback oscillation circuit using a solid-state filter is used, the phase characteristic of the solid-state element is fixed. Therefore, it is necessary to introduce a phase shifter to adjust the frequency.
  • the resistor 12 and the filter-circuit 12 are inserted so that the steepness of the band characteristic and the phase shift operation can be easily performed.
  • the filter one circuit 12 can take the form shown in FIG.
  • the capacitor (0 1 1 can constitute a band full I filter over between the I Ndaku data Nsu (1 2), the band characteristic becomes steep good urchin in Figure 5 B.
  • the phase characteristic The change also steeply near the peak frequency 3 ⁇ 4, move the peak frequency by a small amount •
  • the phase characteristic can be changed simply by turning it on, and the effect as a phase shifter can be obtained. Therefore, it is effective when the circuit of FIG. 2 is used as a feedback oscillation circuit using a solid-state filter.
  • the input terminal IN and the output terminal is absorbed by the C 1 2, O resonance point] becomes ⁇ of the 3 lower place.
  • the capacitor (0 1 1 can constitute a band full I filter over between the I Ndaku data Nsu (1 2), the band characteristic becomes steep good urchin
  • the high-frequency amplifier shown in Figs. 6 and 7 solves this problem.
  • 2 1 are those in preparative run-register Q «j, Q 2.
  • the first amplifier circuit configured by, for amplifying a high-frequency signal inputted by the input terminal IN. 2 2 is a second amplifier circuit.
  • a signal of a desired frequency input from the output terminal of the amplification circuit 21 1 through the filter circuit 23 is further amplified.
  • the first amplifier circuit In addition to 2 1, the required gain is obtained to be 0.
  • a high-frequency output signal is obtained from the output terminal of the second amplifier circuit 22.
  • a filter circuit 25 is connected to the emitter. And lower the impedance of the emitter. 24 is a regulated voltage source
  • FIG. 6 shows the specific configuration of FIG.
  • FIG. 7 shows a case where an integrated circuit having eight terminals is used, and a bonding wire 1 ⁇ 1 , which is formed by a bonding wire between the package terminal and the chip.
  • 1 1 2, 1 « ⁇ 1» 1 0 is ⁇ have respective 2.5 inductor Nsu values of nH ⁇ 5 nH.
  • the high-frequency input signal is supplied from the input terminal IN to a terminal ⁇ via a coupling capacitor, and via a wire inductance 1 ⁇ , the first transistor, which is an emitter-grounded amplifier. Supplied to the base of the register.
  • the emitter of the transistor is connected to the ground in the chip, the ground in the chip is connected to the terminal via the wire inductance L 2 , and the ground is further connected to the external ground. Connected to.
  • Co Lek data DOO La Njisuta is connected to preparative La emitter jitter of Njisuta Q 3 supplies a constant voltage power supply via a load resistor.
  • Preparative run THIS data 0 2 co Lek motor is connected to the appraised jitter of the preparative La Nji Star Q 3 through a load resistor R 1 2.
  • Preparative run-register Q ⁇ of E Mi jitter is divided into three directions, one through the resistor R 14 divided potential of the resistors R 15 and supplied to the base of bets la Njisuta, multiplied by the DC negative feedback ing. Second direction bets la emissions register Q ⁇ E Mi jitter is connected to the ground of the chip via a resistor R 13.
  • Third direction bets la Njisu data Q 2 E Mi jitter is grounded to an external ground through a capacitor C 2 and the damping resistor 5 R 2Q for resonance via a follower Lee Yai Ndaku data Nsu L 5 Have been.
  • First output signal amplified by the amplifier times 3 ⁇ 4 1 of the bets La Njisuta through co Lek data by word y ya unique Ndaku data Nsu L 6 Q 2 'terminal 4 Yo is, to issue preparative desired signal After passing through an external filter circuit 23, it is supplied to the base of a transistor Qo via a terminal 1 and a wire inductance 1 ⁇ 5 .
  • the bets transistor Q 3 total over scan, and a constant voltage is applied through a high resistance R 1 8.
  • Matato La Njisuta Q 3 ⁇ collector is connected to a load resistor via the R 19 power V cc (+ 1 about 2 V) La y down.
  • Based capital La Njisu data Q 3 is, due to be fixed in a DC-constant potential, appraised jitter of the capital La Njisuta Q 3 is fixed to the direct current to a constant potential.
  • Emi jitter bets transistor Q 3 are load resistors 1 ⁇ , is connected to R 1 6, wire Ya yew inductor Nsu 1 ⁇ 9 via a terminal 7 by Rigaibu 'filter over circuit is set to 2 Grounded via 5. This ensures that, for the desired frequency, Emi jitter of the capital La Njisuta Q 3 is 3 ⁇ 4 Ru by sea urchin set to a low fin pin one dance.
  • FIGS. 8A and B ' show another example of the filter circuit 25.
  • FIG. A constant voltage to be supplied to the base of the door transistor ⁇ 3 3 are created by resistance R 5 and the door transistor Q 4 ⁇ Q 7 I made stabilization voltage source 2 to 4 in.
  • this potential third door La Njisuta Q K ⁇ Q 7 is used as a die Sai-de-coupled the collector and the base It is added to the base of the door La Njisuta Q s are allowed to Tsuniyo increase.
  • a bias is applied from the power supply V cc through the resistor 1.
  • the stabilization potential of this via a high resistor 8 is not being supplied to the capital La Njisuta Q 3 a total of one nest.
  • the output signal of the capital La Njisuta Q 3 — 1 Output from the collector through the wire inductance L 10 , terminal 8, and external coupling capacitor c 3 in that order.
  • the good amplifier configured Te Unishi is compared to FIG. 2, the sum of the current flowing through the Doo transistor, Q 2 of FIG. 2, i.e. the total value 1 with I s, and FIG. 7 bets transistor the total value of the current 1 3 and I 4 flowing in Q 2, can be set to less than the sum of the two diagrams iota 3 + 1 4. In this case, I s + I 4
  • the preparative La register used for the amplification - I current sump flows in, the preparative run register 0. It is extremely easy to secure a gain of 1 od B or more, and a sufficient gain can be obtained together with the gain of the first amplifier circuit 1.
  • FIG. 9 shows the circuit configuration when the above high-frequency amplifier is used as the first intermediate frequency amplifier in a CA-V converter.
  • a signal input from a terminal A is mixed in a first mixer 31 with a signal from a first local oscillator 32, and a first first intermediate frequency signal (hereinafter referred to as a first IF signal). signal hereinafter), for example it is frequency-converted into 800MH Z ⁇ 1 GH z band signal.
  • This first IF signal is omitted when the loss of the filter connected to the preamplifier 2 and the filter at the next stage is small.
  • 3 4 Van Dopasufu I filter attenuates frequencies other than the first IF signal.
  • the first IF signal is amplified by the first IF amplifier 35. As the first IF amplifier 35 ⁇ ⁇
  • the circuit shown in Figure 2 or Figure 2 can be used.
  • the amplified signal is mixed with signal from the second local oscillator 3 7 in the second mixer 3 6, is converted into a second intermediate frequency signal (hereinafter referred to as the second IF signal).
  • the second IF signal a second intermediate frequency signal
  • the signal is converted to a 5- wave number, amplified by the second IF amplifier 6, and output to the terminal ⁇ .
  • the first mixer 31 when an image signal, that is, a signal of f d +2 i 2 is input, the first mixer 31
  • FIG. 10 The circuit shown in Fig. 10 solves this problem.
  • This circuit introduces a trap circuit between the second IF amplifier and the second mixer to remove image interference.
  • reference numeral 39 denotes an image trap circuit which is inserted between the first IF amplifier 35 and the second mixer 36.
  • this Lee Mejito wrap circuit 3 9 shows Der Ru more specific circuit structure which removes a frequency of H -2 / J2 to the first 1 FIG.
  • the first third characteristic shown in FIG bandpass off Lee torque using Table S-wave element also R 39, C 39, C 40, L 39 is I main one Jitora-up circuit 39
  • R 39 is a resistor
  • C 39 and C 40 are capacitors
  • L 39 is an inductance.
  • the trap circuit 39 is connected to a second differential mixer 36 of the next stage.
  • c 39 a capacitance of the capacitor c 39
  • C 40 a capacitance of the capacitor c 40
  • V 39 teeth 40 as they may take traps characteristic shown in the first 2 Figure, fl ⁇ -STr C / i If you choose to take a ii, a series resonance trap is taken at the image frequency.
  • the first intermediate frequency £ 1 can pass through the signal line because of the parallel resonance at the intermediate frequency ii.
  • trap circuit 3 ⁇ 4 configured to indicate to the first 4 Figure a between the signal la 'Lee down and ground, series resonance points in the first 4 Figure b
  • ⁇ ⁇ ⁇ ⁇ -2. ⁇ ⁇ 2 _, and if the constant is selected so that the anti-resonance point ⁇ is between ⁇ 2 (i 2) and ⁇ 1, a trap is taken at the image frequency and The first intermediate frequency passes through the signal line because it is inductive at higher frequencies, and the second intermediate frequency is inductive but low in impedance at the lower frequency of the second intermediate frequency /, so that the second intermediate frequency is low. The signal of the frequency falls to the ground through the trap circuit. Therefore, an image filter for normally attenuating i2 can be simultaneously formed for the second mixer 36- connected to the next stage.
  • the first IF amplifier 35 and the second mixer 36 are composed of ICs, and if the mixer input is pulled out as an IC pin, a trouble can be configured.
  • a circuit in which at least two stages of grounded emitter amplifiers are connected by direct current coupling is configured as an integrated circuit, and the emitter of the second stage amplifier is formed as an integrated circuit. Connect the emitter resistor between the ground and the output of the emitter of the second stage amplifier to the outside of the integrated circuit via the bonding wire of the integrated circuit.
  • a filter circuit that includes the inductance of the ng wirer is configured between the ground and a specific frequency that is grounded outside the integrated circuit by this filter circuit to prevent feedback due to the emitter resistance. Eliminates the unstable state of causing oscillation • It is suitable especially for high frequency signal amplification of television tuner circuits and satellite broadcasting receivers.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

Amplificateur haute fréquence utilisé pour amplifier des signaux haute fréquence dans un circuit syntonisateur de télévision ou un récepteur de transmissions par satellite. Des amplificateurs (Q1, Q2) dont l'émetteur est à la terre sont couplés par courant continu dans au moins deux étages pour constituer un circuit intégré. Une résistance d'émetteur (R13) est reliée entre la terre et l'émetteur de l'amplificateur mis à la terre par l'émetteur (Q1) du dernier étage, ledit émetteur de l'amplificateur (Q2) mis à la terre par l'émetteur est relié par l'intermédiaire d'un câble de liaison à un terminal de liaison externe du circuit intégré, et un circuit de filtre (11) est placé entre ce terminal et la terre à l'extérieur, le circuit de filtre (11) contenant une inductance du câble de liaison de manière à présenter une petite impédance pour des fréquences particulières.
PCT/JP1985/000541 1984-10-01 1985-09-30 Amplificateur haute frequence WO1986002214A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE3590480A DE3590480C2 (de) 1984-10-01 1985-09-30 Verstärker für ein Hochfrequenzsignal

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP59/205816 1984-10-01
JP20581684A JPS6184104A (ja) 1984-10-01 1984-10-01 高周波増幅装置
JP60/32002 1985-02-20
JP3200285A JPS61192106A (ja) 1985-02-20 1985-02-20 コンバ−タ

Publications (1)

Publication Number Publication Date
WO1986002214A1 true WO1986002214A1 (fr) 1986-04-10

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1985/000541 WO1986002214A1 (fr) 1984-10-01 1985-09-30 Amplificateur haute frequence

Country Status (4)

Country Link
US (1) US4764736A (fr)
DE (2) DE3590480T1 (fr)
GB (1) GB2177274B (fr)
WO (1) WO1986002214A1 (fr)

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FR2646574B1 (fr) * 1989-04-28 1991-07-05 Alcatel Transmission Amplificateur a gain reglable, utilisable dans le domaine des hyperfrequences
US5036292A (en) * 1990-02-16 1991-07-30 Audio Research Corporation Decoupled electrolytic capacitor
US5379456A (en) * 1991-02-05 1995-01-03 Whistler Corporation Multiplying saw phase shift envelope detector
US5146227A (en) * 1991-05-03 1992-09-08 Whistler Corporation Sweeping receiver
US5272450A (en) * 1991-06-20 1993-12-21 Microwave Modules & Devices, Inc. DC feed network for wideband RF power amplifier
US5325192A (en) * 1992-07-24 1994-06-28 Tektronix, Inc. Ambient light filter for infrared linked stereoscopic glasses
DE4410560A1 (de) * 1994-03-26 1995-09-28 Philips Patentverwaltung Schaltungsanordnung zum Liefern eines Signalwechselstromes
DE19536431C1 (de) * 1995-09-29 1996-09-26 Siemens Ag Integrierter Mikrowellen-Silizium-Baustein
JP3309898B2 (ja) * 1997-06-17 2002-07-29 日本電気株式会社 電源回路
US6011439A (en) * 1997-09-02 2000-01-04 Ford Global Technologies, Inc. Low power RF amplifier
DE69937770T2 (de) * 1998-04-30 2008-12-24 Nxp B.V. Verstärkerausgangsstufe mit Begrenzer für parasitäre Ströme
US6628170B2 (en) * 1998-06-04 2003-09-30 Analog Devices, Inc. Low noise amplifier
FR2813148B1 (fr) * 2000-08-21 2003-08-15 St Microelectronics Sa Preamplificateur lineaire pour amplificateur de puissance radio-frequence
DE102005056486A1 (de) * 2005-11-20 2007-05-31 Atmel Germany Gmbh Eingangsfilter zur Spiegelfrequenzunterdrückung
DE602006018675D1 (de) * 2006-12-22 2011-01-13 Nokia Corp Verstärkungsvorrichtung

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JPS50118684A (fr) * 1974-03-01 1975-09-17
JPS50152549U (fr) * 1974-06-06 1975-12-18

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US3441865A (en) * 1965-05-14 1969-04-29 Rca Corp Inter-stage coupling circuit for neutralizing internal feedback in transistor amplifiers
JPS50152549A (fr) * 1974-05-29 1975-12-08
JPS548955A (en) * 1977-06-23 1979-01-23 Fujitsu Ltd Grounding system for transistor amplifier
DE2741675B1 (de) * 1977-09-16 1979-01-25 Fte Maximal Fernsehtechnik Und Elektromechanik Gmbh & Co Kg, 7130 Muehlacker Kanalverstärker für Antennenanlagen
FR2484171A1 (fr) * 1980-06-04 1981-12-11 Commissariat Energie Atomique Amplificateur lineaire hybride ultra-rapide

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JPS50118684A (fr) * 1974-03-01 1975-09-17
JPS50152549U (fr) * 1974-06-06 1975-12-18

Also Published As

Publication number Publication date
US4764736A (en) 1988-08-16
GB2177274B (en) 1988-10-26
DE3590480C2 (de) 1995-06-29
GB2177274A (en) 1987-01-14
GB8612724D0 (en) 1986-07-02
DE3590480T1 (fr) 1987-01-29

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