WO1983003065A1 - Procede et appareil de fabrication de plaques multi-couches de circuits - Google Patents

Procede et appareil de fabrication de plaques multi-couches de circuits Download PDF

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Publication number
WO1983003065A1
WO1983003065A1 PCT/US1983/000292 US8300292W WO8303065A1 WO 1983003065 A1 WO1983003065 A1 WO 1983003065A1 US 8300292 W US8300292 W US 8300292W WO 8303065 A1 WO8303065 A1 WO 8303065A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive
layer
circuit board
insulator material
printed circuit
Prior art date
Application number
PCT/US1983/000292
Other languages
English (en)
Inventor
Inc. Economics Laboratory
Peter P. Pelligrino
Original Assignee
Economics Lab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Economics Lab filed Critical Economics Lab
Priority to JP58501241A priority Critical patent/JPS59500341A/ja
Publication of WO1983003065A1 publication Critical patent/WO1983003065A1/fr
Priority to DK502783A priority patent/DK502783A/da

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09118—Moulded substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/068—Features of the lamination press or of the lamination process, e.g. using special separator sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0726—Electroforming, i.e. electroplating on a metallic carrier thereby forming a self-supporting structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive

Definitions

  • This invention relates to a method for manufac- turing dense, fine line printed circuit boards and multiple layer printed circuit board packages.
  • these methods include the steps of cladding a base of an electrically insulating material with a conductive copper foil, placing a photoresist material in intimate contact therewith, developing the photo ⁇ resist material to define a conductive circuit pattern thereon, and etching away any . exposed foil which is not covered with photoresist to provide a raised conductive circuit pattern.
  • the conductor patterns are not flush with the surface of the circuit board, a conductor line can be easily scratched during handling, resulting in an open circuit. Also, the copper conductor may sliver and bridge across adjacent conductors, causing short circuits.
  • the etching step in the prior art method may also create a variety of irregularities and defects in the printed circuitry. Etching may result in a conductor being over-etched near its base, thereby undercutting the conductor causing a nonuniform, mush ⁇ room-shaped cross-section. Also, photoresist may become trapped beneath the mushroom ledges, preventing foil hidden beneath the trapped photoresist from being etched away. Over-etching, therefore, makes fine line stability and line width control extremely difficult to achieve as line and spacing widths and tolerances grow smaller. Thus, etching fabrication methods can result in multiple conductor line defects, significantly reducing board yields, with a consequent upsurge in rejected printed circuitry which increases final pro ⁇ duction costs.
  • Board flatness and dimensional stability are important characteristics for insuring that printed circuitry maintains continuous conductive intercon ⁇ nection with component leads and adjacent boards.
  • temperature and pressure fluctuations that occur during lamination cause the board to warp, causing considerable stresses to develop in circuitry mounted on equipment rails. These stresses cause conductors to break and/or to "swim" off the substrate fabricated by prior art methods because they have poor ductility and do not lay flush with the circuit board.
  • the lamination bonding layers and board substrates may be of different material composi ⁇ tion since they are often supplied by different manu ⁇ facturers, may be made of different resins, or come from differnt manufacturing runs. Consequently, the finished -. Q multilayer package is not homogeneous. Lack of homoge ⁇ neity makes it difficult to set proper drill speeds, and drill angles in the fabrication of holes through the multilayers. In some cases the drill speed will be too fast to cut through the copper, causing it to tear, but • j _5 will be the proper speed to cut through the insulation. Thus, some of the layers will have tears and others will be smooth, and some will be extremely uneven, contributing to degraded board quality while increasing unit cost.
  • the present invention is a method of manufacturing fine line, high density printed circuit boards and printed circuit board pcakages.
  • a flash layer of conductive material preferably copper, is electrode- posited onto a rigid metal or metallized substrate that has a low coefficient of thermal expansion.
  • a thick ⁇ ness of photosensitive resist is deposited onto the first layer by silkscreening or other methods known in the art.
  • a mask is placed over the resist to define a conductive circuit pattern on the surface of the resist. The mask is exposed to light, and the resist is devel ⁇ oped. Channels having straight and parallel walls of resist will be formed defining the conductive circuit pattern duplicating the photomask thereby exposing the flash layer.
  • a second layer of conductive material is built up on the physically exposed portions of the flash layer of conductive material within the channels, forming a raised conductive circuit pattern having a thickness not exceeding the depth of the channels. The remaining photosensitive resist is then removed from the flash layer.
  • the flash layer and the second layer defining a raised conductive circuit pattern are completely covered with a uniform layer of insulator laminate material. Pressure is applied to fully embed the raised conduc ⁇ tors in the insular material, such that the flash layer of conductive material remains in intimate and contin ⁇ uous contact with the insulator material.
  • the flash layer integrated with the raised conduc- tive circuit pattern and the insulator material, is separated from the rigid substrate.
  • OMP tive layer is then etched away, so that the conductive circuit pattern embedded in the insulator material is exposed as laying flush and coplanar with * the surface of the insulator material.
  • Printed circuit boards may be formed having embed ⁇ ded conductors exposed on a single side. However, a double sided board may be fabricated if desired, by heat pressing two such printed circuit boards together, back to back or by embedding the conductors on both sides of a single board.
  • the completed circuit boards are stacked with a layer of insulator laminate bonding material interposed between each printed circuit board layer.
  • the multiple layers of printed circuitry and interposed insulator material are heat-pressed together to form a homogeneous package of insulator material with conductive circuit patterns embedded therein.
  • holes' " are drilled through the homogeneous package.
  • the holes are coated with a thin layer of conductive material, preferably copper, using an elec ⁇ troless coating method so as to provide a conductive substrate for electrodepositing additional conductive material thereon.
  • a high impingement speed electrodepositing apparatus a continuous and uniform thickness of conductive maerial is plated onto the walls of the holes.
  • a primary object of this invention is to provide a method for manufacturing fine line, high density printed circuitry whereby the conductive circuit pattern lays flush and aligned with its insulative substrate.
  • Figure 1 is a side view of a substrate with a flash layer deposited thereon.
  • Figure 2 is a side view of the substrate in Figure 1, having a layer of photoresist deposited thereon.
  • Figure 3 is a perspective view of the assembly in Figure 2 with a photomask aligned thereon.
  • Figure 4 is a perspective view taken along line 4-4 of Figure 3 illustrating rectangular channels defining a conductive circuit pattern developed in the photoresist layer after the photomask is removed.
  • Figure 5 is a side view of raised conductor lines deposited within the photoresist channels onto the flash layer taken along 4-4 of Figure 3.
  • Figure 6 is a perspective view of the raised conductive circuit pattern pf Figure 5 after the remain ⁇ ing photoresist is removed.
  • Figure 7 is a view taken along line 4-4 of Figure 3 showing an insulator laminate layer covering the raised conductive circuit pattern and flash layer of Figure 6.
  • Figure 8 is a view taken along line 4-4 of Figure 3 showing the assembly of Figure 7 removed from the rigid substrate.
  • Figure 9 is a top plan view of the printed circuit board assembly of Figure 8 with the flash layer etched away thereby exposing the conductive circuit pattern embedded in and aligned flush with the insulator lami ⁇ nate.
  • Figure 10 is a cross-section of the printed circuit board assembly taken along lines 9-9 of Figure 9.
  • Figure 11 is a side view of a printed circuit board assembly with registration holes drilled therethrough.
  • Figure 12 is a perspective cross-sectional view illustrating multiple printed circuit boards and insula ⁇ tor laminate layers interposed therebetween stacked upon a conventional press.
  • Figure 13 is a perspective view illustrating a homogeneous multi-layer printed circuit board package of the present invention.
  • Figure 14 is a partial perspective v ew illustra- ting electrodeposited and electroless plating layers built up on an interconnect or lead hole of the present invention.
  • a substrate 10 is comprised of a material such as stainless steel having a metallized surface for receiving a flash layer of electrodeposited material.
  • the substrate is comprised of a rigid metal or a metallized plate.
  • a metallized glass material for example, metallized Pyrex, having a very low coefficient of thermal expansion.
  • the substrate - 8 - must have a low coefficient of thermal expansion to insure that when a conductor is placed thereon, it will not shift or float from its design positions due to the thermal expansion of the substrate caused during a subsequent pressing step.
  • the copper flash 12 serves as a base layer upon which further electroplating of conductor lines may be applied. It also serves as a releasing material for separating the printed circuitry from the stainless steel substrate 10 after formation of the printed circuit board is complete, as will be described in detail hereinbelow.
  • the flash layer is as thin as can be since heat transfer characteristics of a very thin layer tend to rapid heat dissipation during heating, causing improved conductor line stability. Consequently, a flash layer of only .0001" to .0002" is deposited onto the substrate in the preferred embodiment. Furthermore, a very thin layer is less wasteful of copper.
  • the thin electro ⁇ plated coating is achieved by utilizing an electropla ⁇ ting apparatus commpnly known as a high impingement speed plating apparatus, such as is taught in United States Patent Number 4,174,261 known as RISP, available from Economics Laboratory, Inc. Osborn Building, St. Paul, Minnesota, 55102.
  • RISP United States Patent Number 4,174,261 known as RISP, available from Economics Laboratory, Inc. Osborn Building, St. Paul, Minnesota, 55102.
  • any conventional electroplating apparatus may be used for applying the copper flash to the substrate.
  • a conventional electroplating apparatus cannot plate the extremely thin coating "contemplated in the present invention without causng pinholes and other imperfections, and therefore is not preferred.
  • a low contact pressure is desired at the interface between the flash layer and the substrate to facilitate separating the flash layer from the substrate.
  • Low contact pressure may be accomplshed by using dissimilar materials for the flash and for the substrate, such as, ' but not limited to, using a copper flash with a stain ⁇ less steel substrate as in the preferred embodiment.
  • materials having similar surfaces may be used if either material is coated with an impurity for reducing adhesion at their interface.
  • the printed circuitry may be fabricated on one side of the stainless steel substrate, but for multilayer applica- tions may be fabricated on both sides of the substrate. This facilitates maximum production output, and allows optimal utilization of electroplating and other appara ⁇ tus used in the method.
  • the photoresist will be either positive, such that it. dissolves when exposed to light, or negative, i.e., it will not dissolve when exposed to light.
  • a photomask 16 defining a conductive circuit pattern 18, is placed on top of the photoresist layer 14, by techniques widely known in the art.
  • the photo ⁇ mask 16 is aligned and brought into continuous contact with the surface of the photoresist 14 to insure a high resolution of the conductive circuit pattern on the surface of the photoresist 14.
  • the photomask masks the surface of the photoresist such that when it is exposed to light only the areas in which the conductors are to be defined are left exposed.
  • the photoresist 14 is developed using a commercially available developer such as Resist Stripper manufactured by Dupont.
  • Resist Stripper manufactured by Dupont.
  • cavities 20 are formed in the areas where the photoresist 14 dissolved exposing the copper flash 12 previously covered by said photoresist 14 in a defined conductive circuit pattern - 10 - 18.
  • the cavities' walls 18 are parallel to each other and perpendicular to the substrate 10, amounting to essentially rectangular channels running throughout the remaining undissolved photoresist 14 according to the original conductive circuit pattern 18 defined by the photomask 16.
  • the electrodeposited material 26 is accumulated within the channels to a desired thickness of about 1.2 to about 15 mils (1.2 mils thickness of copper per sq. ft. to 15 mil thickness of copper per sq. ft.), the thickness being selected to prevent mushrooming of the electrodeposited material as happened in the prior art. At no time, however, should the thickness exceed the depth of the channels.
  • the additive electroplating step produces conductor lines 28 having straight and perpendicular walls of uniform cross-sectional width, facilitating fine line resolu- tion, and making it possible to easily control line widths and densities of extremely narrow dimension.
  • the use of the RISP apparatus enables the conductor lines to be plated with speed and uniformity that is considerably better than can be achieved with conventional electro- plating techniques. Additionally, rapid impingement speed electroplating produces, a very ductile conductor which is critical in preventing defects and failures in very narrow cross-sectioned conductor lines.
  • the photoresist layer 14 is chemically stripped away from the copper flash surface 12 exposing the raised electro ⁇ plated conductive circuit pattern 18.
  • Thermosetting insulator materials such as epoxy coated fiberglass are utilized because of their low cost and good temperature characteristics. If epoxy coated fiberglass is not used, alternative mate ⁇ rials, such as polypropylene, phenolics, or Teflon material manufactured by Dupont may be used.
  • the insulating layer 32 is laminated over the conductive circuit pattern and the copper flash layer 12 by the application of heat and pressure as required for laminate material chosen, accomplished with a rigid pattern laminating press such as manufactured by Pasa- dena Hydraulic of El Monte, California.
  • this lamination step can be performed at a pressure of approximately 50-250 pounds per square inch depending on the weave of the glass fabric (thicker -glass requires more pressure to set the epoxy into the weave) and at a temperature of approxi ⁇ mately 425 degrees Fahrenheit.
  • the insulating material 32 will thereby flow and completely 'fill all the voids between the raised conductor lines and wil also achieve a strong bond with the conductors.
  • the insulator material 32 should be of uniform thickness so that the conductor lines of the circuit pattern 38 will be completely covered by the insulator material.
  • the insulator material 32 in which the conductive circuit pattern 18 is molded and embedded and which is bonded to the copper flash layer 12, is manually separa ⁇ ted from the surface of the substrate 18..
  • the copper flash layer 12 is then removed from the insulator material 32 using conventional etching techniques or a rapid impingements speed etching apparatus, thereby exposing the conductive circuit pattern 18 embedded in the insulator material.
  • Figures 9 and 10 show the resulting printed circuit board. As illustrated in
  • the conductive circuit pattern 18 lays flush with the surface 34 of the insulator material 32, having no abutting, edges or protruding surfaces.
  • the conductive circuit pattern is totally restricted and cannot move. This contrasts with the floating or shifting tendencies that commonly plague printed circui ⁇ try which have been fabricated using prior art methods, having the conductive circuit patterns raised above an insulator- material base.
  • the embedded condutor config- uration that results from the present inventive method provides a durable and highly stable assembly, enabling large continuous sheets of printed circuitry to be manufactured at extremely close tolerances.
  • the oxide created on the copper conductors does not bond well to the insulation material. Therefore, the whole board 36 of the conductive circuit pattern 18 is immersed in a chemical bath, such as commercially available under the trademark Macublack from McDermott of Waterbury, Connecticut. * The chemical coating i - proves the adhesion qualities of the laminate, further insuring that, if the board is stacked, the copper surface of one board will adhere to the laminate surface of an adjacent board. This is particularly important for boards with surfaces exposing mostly copper and thus very little laminate, such as in ground and power boards.
  • a single layer of printed circuitry is complete. Having manu ⁇ factured printed circuitry with the desired conductor patterns, multiple layer printed circuit packages may be fabricted.
  • a layer of insulator material 44 is sand ⁇ wiched between each layer of printed circuitry 42.
  • This insulator material 44 is of the same composition as that used in the laminate structure of the printed circuitry.
  • a multiplicity of printed circuit board layers are stacked atop one another, with interposed layers of insulator material 44 sandwiched therebetween. Referring generally to Figures 11 through 13, registration holes 38 are drilled through each printed circuit board 42 and insulation layer 44 that will be included in the multiple layer prnted circuit package.
  • An optically guided sighting system such as that made by Sportonics, of Rockford, Illinois sites the target at which the hole should be made and then drills through the targets such that there is one hole per target.
  • the registration holes 38 provide mounting means for stack- ing the printed circuit boards and insulation layers 44 on mounting posts 46 so that the multiple layers of printed circuitry will align securely between a pair of pressure plates 48.
  • the multiple printed circuit board layers 42, with insulator material 50 sandwiched therebetween, are pressed together between the pair of pressure plates 48 in a conventional press at a temperature of 375 to 425 degrees Fahrenheit at a pressure of approximately 250 pounds per square inch.
  • a conventional press at a temperature of 375 to 425 degrees Fahrenheit at a pressure of approximately 250 pounds per square inch.
  • 50 psi when 50 psi is used to press a single layer, the same pressure will be used throughout the process.
  • Prior art multiple printed circuit packages often have layers that use insulator materials of different composition, or made in different manufacturing runs. Fabricating multiple-layer printed circuit board pack ⁇ ages in accordance with the present method, however, enables the sandwiched insulator material layers, as well as the laminate base of the printed circuit board layers, to be composed of the same meterial.
  • the combination of developing a homogeneous insulator material in the package, along with eliminating voids through the use of flush printed circuitry, substantially increases ' the number of printed circuit board layers that can be pressed into a single package.
  • the present method has been regularly prac ⁇ ticed on a maximum of 22 board layers, and on a maximum of 40 layers on a more limited basis. However, the method is not thereby limited / and it is possible that packages with even a greater number of boards may be fabricated using the inventive method.
  • Interconnect and component lead holes 52 are then drilled through the multilayer package .44 using conven ⁇ tional drilling means.
  • the holes are generally between .0115 and .093 inches in diameter.
  • the holes are then cleaned to remove drill smear using cleaning means well known in the art or by the rapid impingement speed plating apparatus.
  • a .000050 inch thickness of copper 56 is deposited on the hole walls 58 using a conventional electroless plating process.
  • the copper deposit serves as a base ' for providing sufficient conductivity to carry substantial current for electrolysis. It should be noted that if this copper layer is too thin, it will simply burn away due to the heat generated during electrolysis.
  • 0 copper 60 is then added electrolytically using the rapid impingement speed plating apparatus, to build up the desired conductive coating thickness along the walls of the hole 58. It is critical to this step that rapid impingement speed plating be used since conventional electroplating means cannot access the long and narrow diameter holes to provide a good conductive coating. Further, the use of the rapid impingement speed elec ⁇ troplating apparatus provides a copper coating having improved ductility characteristics. Thus, thermal or other expansion along the vertical axis of the hole will not cause a break in the conductor surface which could interrupt current flow.
  • the present invention is capable of fabricating line conductor widths and spaces as narrow as 2 mils, package layers numbering 40 or more having through holes as small as 5 mils in diameter.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Burglar Alarm Systems (AREA)

Abstract

Procédé et appareil (48) pour fabriquer des assemblages fonctionnels multi-couches de plaques de circuits imprimés (44). Selon le procédé de fabrication d'assemblages de plaques à circuits imprimés (44), une plaque à circuit imprimé (42) est formée avec un dessin de circuit conducteur (18) noyé dans un substrat en matériau isolant (32) et partie intégrante de celui-ci, de sorte que la surface du dessin de circuit conducteur est exposée le long d'une surface (34) du substrat, au ras et co-planaire de celle-ci. Au moins deux desdites plaques (42) sont empilées, une couche de matériau isolant (44) étant interposée entre chaque paire de plaques adjacentes (42). L'assemblage tout entier est pressé à chaud pour former un bloc homogène de matériau isolant, dans lequel des dessins de circuits conducteurs sont noyés et moulés pour faire partie intégrante de celui-ci.
PCT/US1983/000292 1982-03-04 1983-03-04 Procede et appareil de fabrication de plaques multi-couches de circuits WO1983003065A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP58501241A JPS59500341A (ja) 1982-03-04 1983-03-04 多層回路板を製造する方法及び装置
DK502783A DK502783A (da) 1982-03-04 1983-11-03 Fremgangsmaade og apparat til fremstilling af flerlags kredsloebsplader

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US35473682A 1982-03-04 1982-03-04
US354,736820304 1982-03-04

Publications (1)

Publication Number Publication Date
WO1983003065A1 true WO1983003065A1 (fr) 1983-09-15

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ID=23394704

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1983/000292 WO1983003065A1 (fr) 1982-03-04 1983-03-04 Procede et appareil de fabrication de plaques multi-couches de circuits

Country Status (8)

Country Link
EP (1) EP0103627A4 (fr)
JP (1) JPS59500341A (fr)
CA (1) CA1222574A (fr)
DK (1) DK502783A (fr)
IN (1) IN158376B (fr)
IT (1) IT1163136B (fr)
NO (1) NO834009L (fr)
WO (1) WO1983003065A1 (fr)

Cited By (11)

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EP0154564A2 (fr) * 1984-03-09 1985-09-11 Cirtel Inc. Méthode et appareil pour stratifier des plaquettes à circuits électrique multicouches contenant des parties rigides et des parties flexibles
GB2177851A (en) * 1985-06-05 1987-01-28 Spence Bate Laminated low power circuitry components
GB2212333A (en) * 1987-11-11 1989-07-19 Gen Electric Co Plc Method of fabricating multi-layer circuits
US4875966A (en) * 1988-09-12 1989-10-24 General Dynamics Corp., Pomona Div. Pressure transfer plate assembly for a heat bonding apparatus
US4927477A (en) * 1985-08-26 1990-05-22 International Business Machines Corporation Method for making a flush surface laminate for a multilayer circuit board
GB2240221A (en) * 1989-12-26 1991-07-24 Nippon Cmk Kk Method of forming an insulating layer on a printed circuit board
EP3007526A1 (fr) * 2014-10-08 2016-04-13 T-Kingdom Co., Ltd. Structure et procédé de fabrication de carte de circuit imprimé à lignes de circuit conductrices très fines
EP3197251A4 (fr) * 2014-07-18 2018-02-28 Mitsubishi Gas Chemical Company, Inc. Corps stratifié, substrat pour montage d'élément semi-conducteur, et procédé de fabrication desdits corps et substrat
US10332832B2 (en) 2017-08-07 2019-06-25 General Electric Company Method of manufacturing an electronics package using device-last or device-almost last placement
US11664240B2 (en) 2017-11-16 2023-05-30 Mitsubishi Gas Chemical Company, Inc. Method for producing laminate having patterned metal foil, and laminate having patterned metal foil
US11877396B2 (en) 2018-08-30 2024-01-16 Mitsubishi Gas Chemical Company, Inc. Laminate, metal foil-clad laminate, laminate having patterned metal foil, laminate having buildup structure, printed wiring board, multilayer coreless substrate, and method for producing same

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WO2019116927A1 (fr) 2017-12-14 2019-06-20 三菱瓦斯化学株式会社 Feuille de cuivre dotée d'une couche de résine isolante
JP7479596B2 (ja) 2019-03-29 2024-05-09 三菱瓦斯化学株式会社 絶縁性樹脂層付き銅箔、並びに、これを用いた積層体及び積層体の製造方法
TW202110617A (zh) 2019-05-31 2021-03-16 日商三菱瓦斯化學股份有限公司 附絕緣性樹脂層之基材、以及使用其之疊層體及疊層體之製造方法

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US3219749A (en) * 1961-04-21 1965-11-23 Litton Systems Inc Multilayer printed circuit board with solder access apertures
US3350250A (en) * 1962-03-21 1967-10-31 North American Aviation Inc Method of making printed wire circuitry
US3324014A (en) * 1962-12-03 1967-06-06 United Carr Inc Method for making flush metallic patterns
US3627902A (en) * 1970-02-02 1971-12-14 Control Data Corp Interconnections for multilayer printed circuit boards
US3972755A (en) * 1972-12-14 1976-08-03 The United States Of America As Represented By The Secretary Of The Navy Dielectric circuit board bonding
US4159222A (en) * 1977-01-11 1979-06-26 Pactel Corporation Method of manufacturing high density fine line printed circuitry
US4354895A (en) * 1981-11-27 1982-10-19 International Business Machines Corporation Method for making laminated multilayer circuit boards

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0154564A2 (fr) * 1984-03-09 1985-09-11 Cirtel Inc. Méthode et appareil pour stratifier des plaquettes à circuits électrique multicouches contenant des parties rigides et des parties flexibles
EP0154564A3 (fr) * 1984-03-09 1986-08-20 Cirtel Inc. Méthode et appareil pour stratifier des plaquettes à circuits électrique multicouches contenant des parties rigides et des parties flexibles
GB2177851A (en) * 1985-06-05 1987-01-28 Spence Bate Laminated low power circuitry components
US4927477A (en) * 1985-08-26 1990-05-22 International Business Machines Corporation Method for making a flush surface laminate for a multilayer circuit board
GB2212333A (en) * 1987-11-11 1989-07-19 Gen Electric Co Plc Method of fabricating multi-layer circuits
US4875966A (en) * 1988-09-12 1989-10-24 General Dynamics Corp., Pomona Div. Pressure transfer plate assembly for a heat bonding apparatus
GB2240221A (en) * 1989-12-26 1991-07-24 Nippon Cmk Kk Method of forming an insulating layer on a printed circuit board
GB2240221B (en) * 1989-12-26 1994-03-30 Nippon Cmk Kk Improvements relating to multi-layer printed circuit boards
EP3197251A4 (fr) * 2014-07-18 2018-02-28 Mitsubishi Gas Chemical Company, Inc. Corps stratifié, substrat pour montage d'élément semi-conducteur, et procédé de fabrication desdits corps et substrat
US10964552B2 (en) 2014-07-18 2021-03-30 Mitsubishi Gas Chemical Company, Inc. Methods for producing laminate and substrate for mounting a semiconductor device
EP3007526A1 (fr) * 2014-10-08 2016-04-13 T-Kingdom Co., Ltd. Structure et procédé de fabrication de carte de circuit imprimé à lignes de circuit conductrices très fines
US10332832B2 (en) 2017-08-07 2019-06-25 General Electric Company Method of manufacturing an electronics package using device-last or device-almost last placement
US11664240B2 (en) 2017-11-16 2023-05-30 Mitsubishi Gas Chemical Company, Inc. Method for producing laminate having patterned metal foil, and laminate having patterned metal foil
US11877396B2 (en) 2018-08-30 2024-01-16 Mitsubishi Gas Chemical Company, Inc. Laminate, metal foil-clad laminate, laminate having patterned metal foil, laminate having buildup structure, printed wiring board, multilayer coreless substrate, and method for producing same

Also Published As

Publication number Publication date
IT8319877A1 (it) 1984-09-03
EP0103627A4 (fr) 1985-09-18
JPS59500341A (ja) 1984-03-01
DK502783D0 (da) 1983-11-03
CA1222574A (fr) 1987-06-02
IT1163136B (it) 1987-04-08
NO834009L (no) 1983-11-03
IN158376B (fr) 1986-11-01
IT8319877A0 (it) 1983-03-03
EP0103627A1 (fr) 1984-03-28
DK502783A (da) 1983-11-03

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