USRE45035E1 - Verification circuits and methods for phase change memory array - Google Patents
Verification circuits and methods for phase change memory array Download PDFInfo
- Publication number
- USRE45035E1 USRE45035E1 US13/934,954 US201313934954A USRE45035E US RE45035 E1 USRE45035 E1 US RE45035E1 US 201313934954 A US201313934954 A US 201313934954A US RE45035 E USRE45035 E US RE45035E
- Authority
- US
- United States
- Prior art keywords
- memory cell
- signal
- reset state
- writing current
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
Definitions
- the present disclosure relates to a verification circuit, and more particularly to a verification circuit for a phase change memory array.
- a Phase Change Memory is a non-volatile memory with high speed, high capacity and low energy consumption, wherein a plurality of PCM cells of the PCM cell is formed by phase change material, such as chalcogenide etc.
- phase change material such as chalcogenide etc.
- the phase change material can be switched between two states, a crystalline state and an amorphous state, with the application of heat, wherein the phase change material has different resistances corresponding to the crystalline and amorphous states respectively, and the resistances respectively represent different stored data.
- Verification circuits and verification methods for a phase change memory array comprises: a sensing unit, sensing a first sensing voltage from a first memory cell of the phase change memory array according to an enable signal; a comparator, generating a comparing signal according to the first sensing voltage and a reference voltage, so as to indicate whether the first memory cell is in a reset state; a control unit, generating a control signal according to the enable signal; an operating unit, generating a first signal according to the control signal, so as to indicate whether the comparator is active; and an adjusting unit, providing a writing current to the first memory cell and adjusting the writing current according to the control signal until the comparing signal indicates that the first memory cell is in a reset state.
- an exemplary embodiment of a verification method for a phase change memory array is provided.
- a memory cell of the phase change memory array is read to obtain a sensing voltage.
- the sensing voltage is compared with a reference voltage.
- a writing current is provided to the memory cell and the writing current is gradually increased until the sensing voltage corresponding to the writing current is larger than or equal to the reference voltage.
- a writing current is provided to a first memory cell of the phase change memory array and the writing current is gradually increased until a first sensing voltage sensed from the first memory cell is larger than or equal to a reference voltage.
- the current magnitude of the writing current is recorded as a reference current magnitude when the first sensing voltage is larger than or equal to a reference voltage.
- a second memory cell of the phase change memory array is read to obtain a second sensing voltage. It is determined whether the second memory cell is in a reset state by comparing the second sensing voltage and the reference voltage.
- the writing current with the reference current magnitude is provided to the second memory cell to transform the second memory cell into a reset state when the second memory cell is in a non-reset state.
- FIG. 1 shows a verification circuit according to an exemplary embodiment
- FIG. 2 shows a waveform diagram of the signals of the verification circuit shown in FIG. 1 ;
- FIG. 3A shows a schematic diagram of a control unit according to an exemplary embodiment
- FIG. 3B shows a schematic diagram of a detecting unit according to an exemplary embodiment
- FIG. 3C shows a schematic diagram of a calculating unit according to an exemplary embodiment
- FIG. 4 shows a verification circuit according to another exemplary embodiment
- FIGS. 5A and 5B show a waveform diagram illustrating the verification circuit of FIG. 4 performing a verification procedure for different memory cells, respectively;
- FIG. 6 shows a verification method for a PCM array according to an exemplary embodiment
- FIG. 7 shows a verification method for a PCM array according to another exemplary embodiment.
- FIG. 1 shows a verification circuit 110 for verifying whether each memory cell of a phase change memory (PCM) army 150 is in a reset state according to an exemplary embodiment.
- the verification circuit 110 comprises a sensing unit 112 , a comparator 114 , a control unit 116 , an operating unit 118 , a delay unit 124 , a flip-flop 126 , a determining unit 128 , an adjusting unit 130 and two switches 120 and 122 .
- the operating unit 118 is coupled between the control unit 116 and the delay unit 124 , and the operating unit 118 is used to receive a control signal S ctrl to generate a signal S 1 , so as to indicate that the comparator 114 is active or not.
- the delay unit 124 receives and delays the signal S 1 to generate a signal S 2 and then provides the signal S 2 to a clock input terminal of the flip-flop 126 .
- the flip-flop 126 further comprises a data input terminal coupled to the switch 120 and a data output terminal coupled to the determining unit 128 .
- the sensing unit 112 may read a memory cell of the PCM array 150 to sense a resistance R cell of the memory cell, so as to obtain a sensing voltage V cell corresponding to the resistance R cell .
- the comparator 114 may compare the sensing voltage V cell with a reference voltage V ref , so as to generate a comparing signal S c to indicate the state of the read memory cell.
- the comparing signal S c indicates that the read memory cell is in a non-reset state when the sensing voltage V cell is smaller than the reference voltage V ref , and the comparing signal S c indicates that the read memory cell has be transformed into a reset state when the sensing voltage V cell is larger than or equal to the reference voltage V ref .
- the determining unit 128 also provides the enable signal S EN to the control unit 116 to generate the control signal S ctrl .
- the operating unit 118 generates the signal S 1 according to the control signal S ctrl , so as to control the comparator 114 to operate or not.
- the comparing signal S c may control the switches 120 and 122 to turn on or off.
- the switch 120 is coupled between the control unit 116 and the adjusting unit 130 and the switch 122 is coupled between a voltage VDD and the switch 120 , wherein the switches 120 and 122 are controlled by the comparing signal S c .
- the comparing signal S c may control the switches 120 and 122 to change the control signal S ctrl into a signal S clk and provide the signal S clk to the adjusting unit 130 and the flip-flop 126 .
- FIG. 2 shows a waveform diagram of the signals of the verification circuit 110 shown in FIG. 1 .
- the control signal S ctrl and the signal S clk are the pulse signals with identical frequencies but different duty cycles.
- the adjusting unit 130 comprises a writing current generator 132 and a calculating unit 134 .
- the calculating unit 134 may count/calculate the pulse number of the signal S clk to generate an adjusting signal D comprising a plurality of bits.
- the adjusting signal D comprises four bits D 0 , D 1 , D 2 and D 3 .
- the writing current generator 132 generates a writing current I write to the memory cell of the PCM array 150 according to the adjusting signal D, so as to transform the state of the memory cell.
- the writing current generator 132 may also adjust a current magnitude of the writing current I write according to the adjusting signal D, i.e. the writing current I write has the current magnitude corresponding to the adjusting signal D.
- the bit number of the adjusting signal D may determine accuracy of the current magnitude for the writing current I write .
- the sensing unit 112 may sense the sensing voltage V cell from the memory cell, i.e. the memory cell is read by the verification circuit 110 .
- the adjusting unit 130 may provide the writing current I write having the current magnitude corresponding to the adjusting signal D to the memory cell, so as to change the resistance of the memory cell.
- the verification circuit 110 may provide the writing current I write with the current magnitude corresponding to “0010” to the memory cell in a writing period T W .
- the verification circuit 110 may sense and determine whether the memory cell is in a reset state. If not, the verification circuit 110 may provide the writing current I write with the current magnitude corresponding to “0011” to the memory cell in a next writing period T W . Therefore, the verification circuit 110 may gradually increase the writing current I write until the memory cell is transformed from a non-reset state to a reset state. For example, for the duration that the data value of the adjusting signal D is “1000”, the verification circuit 110 may provide the writing current I write with the current magnitude corresponding to “1000” to the memory cell in a writing period T W .
- the verification circuit 110 may read the memory cell to obtain the sensing voltage V cell corresponding to the current magnitude “1000” in a reading period T R .
- the comparing signal S c may indicate that the read memory cell has been transformed into a reset state when the sensing voltage V cell corresponding to the current magnitude “1000” is larger than or equal to the reference voltage V ref .
- the flip-flop 126 may provide a verification signal S ver to the determining unit 128 , so as to provide a next enable signal S EN to the sensing unit 112 for verifying another memory cell.
- FIG. 3A shows a schematic diagram of a control unit according to an exemplary embodiment.
- the control unit comprises sixteen detecting units 310 , five NOR gates 320 and four inverters 330 .
- FIG. 3B shows a schematic diagram of a detecting unit according to an exemplary embodiment.
- the detecting unit comprises two delay units 340 and 350 , two XOR gates 360 and 370 , an inverter 380 and a flip-flop 390 .
- a period time of a writing period T W is determined by the delay unit 340
- an entire period time of a writing period T W and a reading period T R is determined by the delay unit 350 .
- FIG. 3C shows a schematic diagram of a calculating unit according to an exemplary embodiment.
- the calculating unit is an accumulator comprising four flip-flops.
- FIG. 4 shows a verification circuit 410 according to another exemplary embodiment.
- an adjusting unit 430 further comprises a register 436 .
- the flip-flop 126 may generate the verification signal S ver to the determining unit 128 to verify another memory cell. Simultaneously, the flip-flop 126 may also provide the verification signal S ver to the register 436 , so as to store an adjusting signal D corresponding to the present current magnitude of the writing current I write as a reference adjusting signal D ref .
- the determining unit 128 may provide a next enable signal S EN to the register 436 , so as to provide the reference adjusting signal D ref stored in the register 436 to the calculating unit 134 .
- the calculating unit 134 may set the data value of the adjusting signal D according to the data value of the reference adjusting signal D ref such that the writing current generator 132 may provide a writing current I write corresponding to the reference adjusting signal D ref to the another memory cell to be verified.
- FIGS. 5A and 5B show a waveform diagram illustrating the verification circuit 410 of FIG. 4 performing a verification procedure for different memory cells, respectively.
- the verification circuit 410 starts to verify a memory cell Cell 1 of the PCM array 150 .
- the verification circuit 410 senses that the memory cell Cell 1 has been transformed into a reset state.
- the register 436 may store “1000” as the data value of the reference adjusting signal D ref according to the verification signal S ver .
- the verification circuit 410 starts to verify another memory cell Cell 2 of the PCM array 150 .
- the register 436 may provide the reference adjusting signal D ref to the calculating unit 134 as an initial value of the adjusting signal D according to an enable signal S EN corresponding to the memory cell Cell 2 .
- the verification circuit 410 may read the memory cell Cell 2 .
- the verification circuit 410 may provide a writing current I write corresponding to the reference adjusting signal D ref , i.e. the calculating unit 134 may provide the adjusting signal D which has data value “1000” to the writing current generator 132 , so as to generate the writing current I write .
- the verification circuit 410 may read the memory cell 2 to obtain a sensing voltage V cell corresponding to “1000”.
- the comparing signal S c indicates that the memory cell Cell 2 has been transformed into a reset state when the sensing voltage V cell is larger than or equal to the reference voltage V ref .
- the flip-flop 126 generates the verification signal S ver to the determining unit 128 to notify that the memory cell Cell 2 has been completely verified.
- a next memory cell is verified until each memory cell of the PCM array has been completely verified. Accordingly, a verification time of a PCM memory array is decreased.
- the verification circuit 410 may provide the writing current I write with a current magnitude corresponding to the reference adjusting signal D ref to the memory cell Cell 2 .
- the verification circuit 410 may read the memory cell 2 to obtain a sensing voltage V cell corresponding to “1000”.
- the sensing voltage V cell is smaller than the reference voltage V ref (i.e.
- the verification circuit 410 may gradually increase the writing current I write according to the adjusting signal D until the memory cell Cell 2 is transformed into a reset state, as shown in FIG. 5B .
- the calculating unit 134 may use the data value “1000” of the reference adjusting signal D ref as the initial value of the adjusting signal D, and increase the data value of the adjusting signal D according to the pulse number of the signal S clk .
- FIG. 6 shows a verification method for a PCM array according to an exemplary embodiment.
- a memory cell of the PCM array is read to obtain a sensing voltage.
- a writing current is provided to the memory cell when the sensing voltage is smaller than the reference voltage (i.e. the memory cell is in a non-reset state), and the writing current is gradually increased until the sensing voltage corresponding to the writing current is larger than or equal to the reference voltage, i.e. the memory cell is in a reset state, thus the memory cell is completely verified.
- FIG. 7 shows a verification method for a PCM array according to another exemplary embodiment.
- a writing current is provided to a first memory cell of the PCM array, and the writing current is gradually increased until a sensing voltage sensed from the first memory cell is larger than or equal to a reference voltage, i.e. the first memory cell has been transformed into a reset state.
- a current magnitude of the writing current is recorded and stored as a reference current magnitude when the first memory cell has been transformed into a reset state (step S 704 ).
- a second memory cell of the PCM array is read to obtain a second sensing voltage (step S 706 ).
- step S 708 it is determined whether the second memory cell is in a reset state by comparing the second sensing voltage with a reference voltage (step S 708 ).
- a writing current with the reference current magnitude is provided to the second memory cell when the second memory cell is in a non-reset state, so as to transform the second memory cell from a non-reset state to a reset state (step S 710 ).
- the second memory cell is in a non-reset state when the second sensing voltage corresponding to the writing current is smaller than the reference voltage. Therefore, the writing current is gradually increased until the second sensing voltage corresponding to the writing current is larger than or equal to the reference voltage, such that the second memory cell is transformed into a reset state.
Landscapes
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Semiconductor Memories (AREA)
- Mram Or Spin Memory Techniques (AREA)
Abstract
Description
Claims (29)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/934,954 USRE45035E1 (en) | 2008-12-30 | 2013-07-03 | Verification circuits and methods for phase change memory array |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW097151378A TWI402845B (en) | 2008-12-30 | 2008-12-30 | Verification circuits and methods for phase change memory |
TW097151378A | 2008-12-30 | ||
US12/485,720 US7974122B2 (en) | 2008-12-30 | 2009-06-16 | Verification circuits and methods for phase change memory array |
US13/934,954 USRE45035E1 (en) | 2008-12-30 | 2013-07-03 | Verification circuits and methods for phase change memory array |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/485,720 Reissue US7974122B2 (en) | 2008-12-30 | 2009-06-16 | Verification circuits and methods for phase change memory array |
Publications (1)
Publication Number | Publication Date |
---|---|
USRE45035E1 true USRE45035E1 (en) | 2014-07-22 |
Family
ID=42284771
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/485,720 Ceased US7974122B2 (en) | 2008-12-30 | 2009-06-16 | Verification circuits and methods for phase change memory array |
US13/934,954 Active 2029-09-12 USRE45035E1 (en) | 2008-12-30 | 2013-07-03 | Verification circuits and methods for phase change memory array |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/485,720 Ceased US7974122B2 (en) | 2008-12-30 | 2009-06-16 | Verification circuits and methods for phase change memory array |
Country Status (2)
Country | Link |
---|---|
US (2) | US7974122B2 (en) |
TW (1) | TWI402845B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8982634B2 (en) * | 2012-07-11 | 2015-03-17 | Ememory Technology Inc. | Flash memory |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI347607B (en) | 2007-11-08 | 2011-08-21 | Ind Tech Res Inst | Writing system and method for a phase change memory |
US20090304775A1 (en) * | 2008-06-04 | 2009-12-10 | Joshi Ashok V | Drug-Exuding Orthopedic Implant |
TWI402845B (en) | 2008-12-30 | 2013-07-21 | Higgs Opl Capital Llc | Verification circuits and methods for phase change memory |
TWI412124B (en) | 2008-12-31 | 2013-10-11 | Higgs Opl Capital Llc | Phase change memory |
KR101652333B1 (en) * | 2010-02-10 | 2016-08-30 | 삼성전자주식회사 | Variable resistance memory device and program method thereof |
US8605531B2 (en) * | 2011-06-20 | 2013-12-10 | Intel Corporation | Fast verify for phase change memory with switch |
US8737120B2 (en) | 2011-07-29 | 2014-05-27 | Micron Technology, Inc. | Reference voltage generators and sensing circuits |
US9281061B2 (en) | 2012-09-19 | 2016-03-08 | Micron Technology, Inc. | Methods and apparatuses having a voltage generator with an adjustable voltage drop for representing a voltage drop of a memory cell and/or a current mirror circuit and replica circuit |
US9001553B1 (en) * | 2012-11-06 | 2015-04-07 | Adesto Technologies Corporation | Resistive devices and methods of operation thereof |
KR20140081027A (en) * | 2012-12-21 | 2014-07-01 | 에스케이하이닉스 주식회사 | Nonvolatile Memory Apparatus |
US10497430B2 (en) * | 2016-06-22 | 2019-12-03 | Samsung Electronics Co., Ltd. | Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on power supply voltage detection circuits |
CN110036444B (en) | 2016-09-21 | 2023-06-30 | 合肥睿科微电子有限公司 | Adaptive memory cell write conditions |
US10832770B2 (en) | 2019-03-13 | 2020-11-10 | Sandisk Technologies Llc | Single pulse memory operation |
KR20210047606A (en) * | 2019-10-22 | 2021-04-30 | 삼성전자주식회사 | Memory device |
US11615841B2 (en) * | 2019-10-22 | 2023-03-28 | Samsung Electronics Co., Ltd. | Memory device and operating method thereof |
US11900992B2 (en) * | 2022-02-03 | 2024-02-13 | Micron Technology, Inc. | Reference voltage adjustment for word line groups |
Citations (79)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4974205A (en) | 1988-10-24 | 1990-11-27 | Fujitsu Limited | Josephson memory and read/write circuit |
US5694363A (en) | 1995-04-28 | 1997-12-02 | Sgs-Thomson Microelectronics S.R.L. | Reading circuit for memory cell devices having a low supply voltage |
US5787042A (en) | 1997-03-18 | 1998-07-28 | Micron Technology, Inc. | Method and apparatus for reading out a programmable resistor memory |
US5883837A (en) | 1996-09-30 | 1999-03-16 | Sgs-Thomson Microelectronics, S.R.L. | Reading circuit for semiconductor memory cells |
JP2002246561A (en) | 2001-02-19 | 2002-08-30 | Dainippon Printing Co Ltd | Storage cell, memory matrix using the same, and their manufacturing methods |
US6487113B1 (en) | 2001-06-29 | 2002-11-26 | Ovonyx, Inc. | Programming a phase-change memory with slow quench time |
CN1455412A (en) | 2002-04-30 | 2003-11-12 | 惠普公司 | Resistance crosspoint storage array with charge injection differential read-out amplifier |
JP2004274055A (en) | 2003-03-04 | 2004-09-30 | Samsung Electronics Co Ltd | Storage cell for memory element, as well as phase change type memory element and its forming method |
US20050068804A1 (en) | 2003-09-25 | 2005-03-31 | Samsung Electronics Co., Ltd. | Phase-change memory device and method that maintains the resistance of a phase-change material in a reset state within a constant resistance range |
JP2005525690A (en) | 2001-08-31 | 2005-08-25 | オヴォニクス インコーポレイテッド | Phase change memory with higher pore position |
JP2006510220A (en) | 2002-12-13 | 2006-03-23 | オヴォニクス,インコーポレイテッド | Memory and access device |
JP2006108645A (en) | 2004-10-08 | 2006-04-20 | Ind Technol Res Inst | Multilevel phase change memory, method of operating the same, and method of manufacturing the same |
US7054213B2 (en) | 2000-12-28 | 2006-05-30 | Stmicroelectronics, Inc. | Method and circuit for determining sense amplifier sensitivity |
US7110286B2 (en) | 2004-02-04 | 2006-09-19 | Samsung Electronics Co., Ltd. | Phase-change memory device and method of writing a phase-change memory device |
US20060221678A1 (en) | 2005-03-30 | 2006-10-05 | Ferdinando Bedeschi | Circuit for reading memory cells |
JP2006295168A (en) | 2005-04-06 | 2006-10-26 | Samsung Electronics Co Ltd | Multivalued resistive memory element, and its manufacture and operating method therefor |
US7154774B2 (en) | 2005-03-30 | 2006-12-26 | Ovonyx, Inc. | Detecting switching of access elements of phase change memory cells |
US20070002654A1 (en) | 2005-06-30 | 2007-01-04 | Carlo Borromeo | Method and apparatus for sensing a state of a memory cell |
US7190607B2 (en) | 2004-06-19 | 2007-03-13 | Samsung Electronics Co., Ltd. | Phase-change memory element driver circuits using measurement to control current and methods of controlling drive current of phase-change memory elements using measurement |
JP2007103945A (en) | 2005-10-06 | 2007-04-19 | Samsung Electronics Co Ltd | Phase change memory devices using magnetic resistance effect, methods of operating and methods of fabricating same |
JP2007184591A (en) | 2006-01-02 | 2007-07-19 | Samsung Electronics Co Ltd | Phase change storage element including contact with multi-bit cell and diameter to be adjusted therein, its manufacturing method, and its program method |
US7259982B2 (en) | 2005-01-05 | 2007-08-21 | Intel Corporation | Reading phase change memories to reduce read disturbs |
US7324371B2 (en) | 2001-12-27 | 2008-01-29 | Stmicroelectronics S.R.L. | Method of writing to a phase change memory device |
CN101136452A (en) | 2006-08-31 | 2008-03-05 | 财团法人工业技术研究院 | Phase variation storage installation and its making method |
US7359231B2 (en) | 2004-06-30 | 2008-04-15 | Intel Corporation | Providing current for phase change memories |
CN101202326A (en) | 2006-12-14 | 2008-06-18 | 财团法人工业技术研究院 | Phase-change storage apparatus and method of manufacture |
TW200828506A (en) | 2006-12-29 | 2008-07-01 | Ind Tech Res Inst | Phase-change memory element and method for fabricating the same |
JP2008171541A (en) | 2007-01-12 | 2008-07-24 | Ind Technol Res Inst | Method and system for driving phase change memory |
JP2008193071A (en) | 2007-02-01 | 2008-08-21 | Ind Technol Res Inst | Phase change memory |
US7423897B2 (en) | 2004-10-01 | 2008-09-09 | Ovonyx, Inc. | Method of operating a programmable resistance memory array |
CN101266834A (en) | 2007-03-15 | 2008-09-17 | 财团法人工业技术研究院 | Writing drive method and system for phase change memory |
CN101271862A (en) | 2007-03-19 | 2008-09-24 | 财团法人工业技术研究院 | Memory element and manufacturing method thereof |
JP2008226427A (en) | 2007-03-08 | 2008-09-25 | Ind Technol Res Inst | Writing method and system for phase change memory |
CN101276643A (en) | 2007-03-28 | 2008-10-01 | 财团法人工业技术研究院 | Write-in method and system of phase variation memory |
US7447092B2 (en) | 2003-08-22 | 2008-11-04 | Samsung Electronics Co., Ltd. | Write driver circuit for controlling a write current applied to a phase change memory based on an ambient temperature |
TW200845443A (en) | 2007-05-14 | 2008-11-16 | Ind Tech Res Inst | Phase-change memory element |
US7457151B2 (en) | 2005-07-13 | 2008-11-25 | Samsung Electronics Co., Ltd. | Phase change random access memory (PRAM) device having variable drive voltages |
CN101312230A (en) | 2007-05-25 | 2008-11-26 | 财团法人工业技术研究院 | Phase change storage apparatus and method of manufacture |
TW200849278A (en) | 2007-06-13 | 2008-12-16 | Ind Tech Res Inst | A writing circuit for a phase change memory |
CN101330126A (en) | 2007-06-19 | 2008-12-24 | 财团法人工业技术研究院 | Phase variation storage unit structure and method for manufacturing the same |
CN101335045A (en) | 2007-06-27 | 2008-12-31 | 财团法人工业技术研究院 | Write circuit of phase-change memory |
TW200901196A (en) | 2007-06-25 | 2009-01-01 | Ind Tech Res Inst | Sensing circuits and methods of phase change memory |
TWI305042B (en) | 2006-08-16 | 2009-01-01 | Ind Tech Res Inst | Phase-change memory devices and methods for fabricating the same |
TW200908294A (en) | 2007-08-14 | 2009-02-16 | Ind Tech Res Inst | Phase-change memory |
CN101369450A (en) | 2007-08-17 | 2009-02-18 | 财团法人工业技术研究院 | Sensing circuit of phase-change memory |
CN101383397A (en) | 2007-09-04 | 2009-03-11 | 财团法人工业技术研究院 | Phase change memory device and fabrication method thereof |
TW200915318A (en) | 2007-09-21 | 2009-04-01 | Ind Tech Res Inst | Device controlling phase change storage element and method of increasing realibility of phase change storage elememt |
US7515460B2 (en) | 2005-01-25 | 2009-04-07 | Intel Corporation | Multilevel programming of phase change memory cells |
CN101414480A (en) | 2007-10-19 | 2009-04-22 | 财团法人工业技术研究院 | Control device for phase-change memory cell and method for adding phase-change memory cell reliability |
TW200921682A (en) | 2007-11-08 | 2009-05-16 | Ind Tech Res Inst | Writing system and method for a phase change memory |
US7535747B2 (en) | 2006-09-04 | 2009-05-19 | Samsung Electronics Co., Ltd. | Phase change random access memory and related methods of operation |
US7542356B2 (en) | 2006-11-01 | 2009-06-02 | Samsung Electronics Co., Ltd. | Semiconductor memory device and method for reducing cell activation during write operations |
CN101452743A (en) | 2007-12-05 | 2009-06-10 | 财团法人工业技术研究院 | Writing-in system and method for phase change memory |
TW200926186A (en) | 2007-12-03 | 2009-06-16 | Ind Tech Res Inst | Memory and method for reducing power dissipation caused by current leakage |
CN101471130A (en) | 2007-12-25 | 2009-07-01 | 财团法人工业技术研究院 | Phase-change memory device and its control method |
US7566895B2 (en) | 2006-11-24 | 2009-07-28 | Industrial Technology Research Institute | Phase change memory device and method for fabricating the same |
US20090189142A1 (en) | 2008-01-25 | 2009-07-30 | Industrial Technology Research Institute | Phase-Change Memory |
CN101504968A (en) | 2008-01-25 | 2009-08-12 | 财团法人工业技术研究院 | Phase-change memory and its production method |
CN101504863A (en) | 2008-02-05 | 2009-08-12 | 财团法人工业技术研究院 | Memory and method for suppressing energy consumption of memory leakage current |
US7609544B2 (en) | 2004-11-26 | 2009-10-27 | Renesas Technology Corp. | Programmable semiconductor memory device |
US20090296458A1 (en) | 2008-05-27 | 2009-12-03 | Samsung Electronics Co., Ltd. | Resistance variable memory device and method of writing data |
CN101599301A (en) | 2008-06-06 | 2009-12-09 | 财团法人工业技术研究院 | Storer and memory-writing method |
TW200951981A (en) | 2008-06-02 | 2009-12-16 | Ind Tech Res Inst | Memory and writing method thereof |
TW200952169A (en) | 2008-06-03 | 2009-12-16 | Ind Tech Res Inst | Phase-change memory devices and methods for fabricating the same |
US7639522B2 (en) * | 2006-11-29 | 2009-12-29 | Samsung Electronics Co., Ltd. | Method of driving multi-level variable resistive memory device and multi-level variable resistive memory device |
US7646627B2 (en) | 2006-05-18 | 2010-01-12 | Renesas Technology Corp. | Magnetic random access memory having improved read disturb suppression and thermal disturbance resistance |
CN101626060A (en) | 2008-07-11 | 2010-01-13 | 财团法人工业技术研究院 | Phase-change memory element |
US7670869B2 (en) | 2007-02-16 | 2010-03-02 | Industrial Technology Research Institute | Semiconductor device and fabrications thereof |
US20100117050A1 (en) | 2008-11-12 | 2010-05-13 | Industrial Technology Research Institute | Phase-change memory element |
TW201025573A (en) | 2008-12-31 | 2010-07-01 | Ind Tech Res Inst | Phase change memory |
TW201025326A (en) | 2008-12-30 | 2010-07-01 | Ind Tech Res Inst | Verification circuits and methods for phase change memory |
US7773411B2 (en) | 2007-12-06 | 2010-08-10 | Industrial Technology Research Institute | Phase change memory and control method thereof |
US7773408B2 (en) | 2005-11-30 | 2010-08-10 | Renesas Technology Corp. | Nonvolatile memory device |
CN101814323A (en) | 2009-02-23 | 2010-08-25 | 财团法人工业技术研究院 | Verification circuit and method of phase change memory array |
US7787281B2 (en) | 2007-07-05 | 2010-08-31 | Industrial Technology Research Institute | Writing circuit for a phase change memory |
CN101819816A (en) | 2009-02-27 | 2010-09-01 | 财团法人工业技术研究院 | Phase change memory |
TWI334604B (en) | 2007-06-25 | 2010-12-11 | Ind Tech Res Inst | Sensing circuits of phase change memory |
TWI336925B (en) | 2007-05-31 | 2011-02-01 | Ind Tech Res Inst | Phase-change memory cell structures and methods for fabricating the same |
TWI343642B (en) | 2007-04-24 | 2011-06-11 | Ind Tech Res Inst | Phase-change memory devices and methods for fabricating the same |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7280390B2 (en) * | 2005-04-14 | 2007-10-09 | Ovonyx, Inc. | Reading phase change memories without triggering reset cell threshold devices |
US7391664B2 (en) * | 2006-04-27 | 2008-06-24 | Ovonyx, Inc. | Page mode access for non-volatile memory arrays |
-
2008
- 2008-12-30 TW TW097151378A patent/TWI402845B/en not_active IP Right Cessation
-
2009
- 2009-06-16 US US12/485,720 patent/US7974122B2/en not_active Ceased
-
2013
- 2013-07-03 US US13/934,954 patent/USRE45035E1/en active Active
Patent Citations (116)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4974205A (en) | 1988-10-24 | 1990-11-27 | Fujitsu Limited | Josephson memory and read/write circuit |
US5694363A (en) | 1995-04-28 | 1997-12-02 | Sgs-Thomson Microelectronics S.R.L. | Reading circuit for memory cell devices having a low supply voltage |
US5883837A (en) | 1996-09-30 | 1999-03-16 | Sgs-Thomson Microelectronics, S.R.L. | Reading circuit for semiconductor memory cells |
US5787042A (en) | 1997-03-18 | 1998-07-28 | Micron Technology, Inc. | Method and apparatus for reading out a programmable resistor memory |
US7054213B2 (en) | 2000-12-28 | 2006-05-30 | Stmicroelectronics, Inc. | Method and circuit for determining sense amplifier sensitivity |
JP2002246561A (en) | 2001-02-19 | 2002-08-30 | Dainippon Printing Co Ltd | Storage cell, memory matrix using the same, and their manufacturing methods |
US6487113B1 (en) | 2001-06-29 | 2002-11-26 | Ovonyx, Inc. | Programming a phase-change memory with slow quench time |
JP2005525690A (en) | 2001-08-31 | 2005-08-25 | オヴォニクス インコーポレイテッド | Phase change memory with higher pore position |
US7324371B2 (en) | 2001-12-27 | 2008-01-29 | Stmicroelectronics S.R.L. | Method of writing to a phase change memory device |
CN1455412A (en) | 2002-04-30 | 2003-11-12 | 惠普公司 | Resistance crosspoint storage array with charge injection differential read-out amplifier |
JP2006510220A (en) | 2002-12-13 | 2006-03-23 | オヴォニクス,インコーポレイテッド | Memory and access device |
JP2004274055A (en) | 2003-03-04 | 2004-09-30 | Samsung Electronics Co Ltd | Storage cell for memory element, as well as phase change type memory element and its forming method |
US7447092B2 (en) | 2003-08-22 | 2008-11-04 | Samsung Electronics Co., Ltd. | Write driver circuit for controlling a write current applied to a phase change memory based on an ambient temperature |
US20050068804A1 (en) | 2003-09-25 | 2005-03-31 | Samsung Electronics Co., Ltd. | Phase-change memory device and method that maintains the resistance of a phase-change material in a reset state within a constant resistance range |
US7110286B2 (en) | 2004-02-04 | 2006-09-19 | Samsung Electronics Co., Ltd. | Phase-change memory device and method of writing a phase-change memory device |
US7190607B2 (en) | 2004-06-19 | 2007-03-13 | Samsung Electronics Co., Ltd. | Phase-change memory element driver circuits using measurement to control current and methods of controlling drive current of phase-change memory elements using measurement |
US7359231B2 (en) | 2004-06-30 | 2008-04-15 | Intel Corporation | Providing current for phase change memories |
US7423897B2 (en) | 2004-10-01 | 2008-09-09 | Ovonyx, Inc. | Method of operating a programmable resistance memory array |
JP2006108645A (en) | 2004-10-08 | 2006-04-20 | Ind Technol Res Inst | Multilevel phase change memory, method of operating the same, and method of manufacturing the same |
US7609544B2 (en) | 2004-11-26 | 2009-10-27 | Renesas Technology Corp. | Programmable semiconductor memory device |
US7259982B2 (en) | 2005-01-05 | 2007-08-21 | Intel Corporation | Reading phase change memories to reduce read disturbs |
US7515460B2 (en) | 2005-01-25 | 2009-04-07 | Intel Corporation | Multilevel programming of phase change memory cells |
US20060221678A1 (en) | 2005-03-30 | 2006-10-05 | Ferdinando Bedeschi | Circuit for reading memory cells |
US7154774B2 (en) | 2005-03-30 | 2006-12-26 | Ovonyx, Inc. | Detecting switching of access elements of phase change memory cells |
US7388775B2 (en) | 2005-03-30 | 2008-06-17 | Ovonyx, Inc. | Detecting switching of access elements of phase change memory cells |
JP2006295168A (en) | 2005-04-06 | 2006-10-26 | Samsung Electronics Co Ltd | Multivalued resistive memory element, and its manufacture and operating method therefor |
US20070002654A1 (en) | 2005-06-30 | 2007-01-04 | Carlo Borromeo | Method and apparatus for sensing a state of a memory cell |
US7457151B2 (en) | 2005-07-13 | 2008-11-25 | Samsung Electronics Co., Ltd. | Phase change random access memory (PRAM) device having variable drive voltages |
JP2007103945A (en) | 2005-10-06 | 2007-04-19 | Samsung Electronics Co Ltd | Phase change memory devices using magnetic resistance effect, methods of operating and methods of fabricating same |
US7773408B2 (en) | 2005-11-30 | 2010-08-10 | Renesas Technology Corp. | Nonvolatile memory device |
JP2007184591A (en) | 2006-01-02 | 2007-07-19 | Samsung Electronics Co Ltd | Phase change storage element including contact with multi-bit cell and diameter to be adjusted therein, its manufacturing method, and its program method |
US7646627B2 (en) | 2006-05-18 | 2010-01-12 | Renesas Technology Corp. | Magnetic random access memory having improved read disturb suppression and thermal disturbance resistance |
US7745811B2 (en) | 2006-08-16 | 2010-06-29 | Industrial Technology Research Institute | Phase change memory devices and methods for fabricating the same |
TWI305042B (en) | 2006-08-16 | 2009-01-01 | Ind Tech Res Inst | Phase-change memory devices and methods for fabricating the same |
CN101136452A (en) | 2006-08-31 | 2008-03-05 | 财团法人工业技术研究院 | Phase variation storage installation and its making method |
US7535747B2 (en) | 2006-09-04 | 2009-05-19 | Samsung Electronics Co., Ltd. | Phase change random access memory and related methods of operation |
US7542356B2 (en) | 2006-11-01 | 2009-06-02 | Samsung Electronics Co., Ltd. | Semiconductor memory device and method for reducing cell activation during write operations |
US7566895B2 (en) | 2006-11-24 | 2009-07-28 | Industrial Technology Research Institute | Phase change memory device and method for fabricating the same |
TWI318470B (en) | 2006-11-24 | 2009-12-11 | Ind Tech Res Inst | Phase change memory device and method of fabricating the same |
US7639522B2 (en) * | 2006-11-29 | 2009-12-29 | Samsung Electronics Co., Ltd. | Method of driving multi-level variable resistive memory device and multi-level variable resistive memory device |
CN101202326A (en) | 2006-12-14 | 2008-06-18 | 财团法人工业技术研究院 | Phase-change storage apparatus and method of manufacture |
TW200828506A (en) | 2006-12-29 | 2008-07-01 | Ind Tech Res Inst | Phase-change memory element and method for fabricating the same |
CN101211959A (en) | 2006-12-29 | 2008-07-02 | 财团法人工业技术研究院 | Phase-change memory and fabrication method thereof |
US7521372B2 (en) | 2006-12-29 | 2009-04-21 | Industrial Technology Research Institute | Method of fabrication of phase-change memory |
US7643373B2 (en) | 2007-01-12 | 2010-01-05 | Shyh-Shyuan Sheu | Driving method and system for a phase change memory |
JP2008171541A (en) | 2007-01-12 | 2008-07-24 | Ind Technol Res Inst | Method and system for driving phase change memory |
TWI320180B (en) | 2007-01-12 | 2010-02-01 | A driving method and a driving system for writing the phase change memory | |
TWI326917B (en) | 2007-02-01 | 2010-07-01 | Ind Tech Res Inst | Phase-change memory |
JP2008193071A (en) | 2007-02-01 | 2008-08-21 | Ind Technol Res Inst | Phase change memory |
TWI324823B (en) | 2007-02-16 | 2010-05-11 | Ind Tech Res Inst | Memory device and fabrications thereof |
US7670869B2 (en) | 2007-02-16 | 2010-03-02 | Industrial Technology Research Institute | Semiconductor device and fabrications thereof |
TWI330846B (en) | 2007-03-08 | 2010-09-21 | Ind Tech Res Inst | A writing method and system for a phase change memory |
JP2008226427A (en) | 2007-03-08 | 2008-09-25 | Ind Technol Res Inst | Writing method and system for phase change memory |
US7773409B2 (en) | 2007-03-08 | 2010-08-10 | Industrial Technology Research Institute | Writing method and system for a phase change memory |
CN101266834A (en) | 2007-03-15 | 2008-09-17 | 财团法人工业技术研究院 | Writing drive method and system for phase change memory |
CN101271862A (en) | 2007-03-19 | 2008-09-24 | 财团法人工业技术研究院 | Memory element and manufacturing method thereof |
CN101276643A (en) | 2007-03-28 | 2008-10-01 | 财团法人工业技术研究院 | Write-in method and system of phase variation memory |
US7964862B2 (en) | 2007-04-24 | 2011-06-21 | Industrial Technology Research Institute | Phase change memory devices and methods for manufacturing the same |
TWI343642B (en) | 2007-04-24 | 2011-06-11 | Ind Tech Res Inst | Phase-change memory devices and methods for fabricating the same |
US7679163B2 (en) | 2007-05-14 | 2010-03-16 | Industrial Technology Research Institute | Phase-change memory element |
CN101308903A (en) | 2007-05-14 | 2008-11-19 | 财团法人工业技术研究院 | Phase-change memory element |
JP2008283163A (en) | 2007-05-14 | 2008-11-20 | Ind Technol Res Inst | Phase change memory element |
TW200845443A (en) | 2007-05-14 | 2008-11-16 | Ind Tech Res Inst | Phase-change memory element |
CN101312230A (en) | 2007-05-25 | 2008-11-26 | 财团法人工业技术研究院 | Phase change storage apparatus and method of manufacture |
TWI336925B (en) | 2007-05-31 | 2011-02-01 | Ind Tech Res Inst | Phase-change memory cell structures and methods for fabricating the same |
US7923714B2 (en) | 2007-05-31 | 2011-04-12 | Industrial Technology Research Institute | Phase change memory cell structures and methods for manufacturing the same |
TW200849278A (en) | 2007-06-13 | 2008-12-16 | Ind Tech Res Inst | A writing circuit for a phase change memory |
US7672176B2 (en) | 2007-06-13 | 2010-03-02 | Industrial Technology Research Institute | Writing circuit for a phase change memory |
CN101330126A (en) | 2007-06-19 | 2008-12-24 | 财团法人工业技术研究院 | Phase variation storage unit structure and method for manufacturing the same |
US7796454B2 (en) | 2007-06-25 | 2010-09-14 | Industrial Technology Research Institute | Sensing circuit of a phase change memory and sensing method thereof |
TWI334604B (en) | 2007-06-25 | 2010-12-11 | Ind Tech Res Inst | Sensing circuits of phase change memory |
US7933147B2 (en) | 2007-06-25 | 2011-04-26 | Industrial Technology Research Institute | Sensing circuit of a phase change memory and sensing method thereof |
TW200901196A (en) | 2007-06-25 | 2009-01-01 | Ind Tech Res Inst | Sensing circuits and methods of phase change memory |
CN101335045A (en) | 2007-06-27 | 2008-12-31 | 财团法人工业技术研究院 | Write circuit of phase-change memory |
US7787281B2 (en) | 2007-07-05 | 2010-08-31 | Industrial Technology Research Institute | Writing circuit for a phase change memory |
TWI342022B (en) | 2007-07-05 | 2011-05-11 | Ind Tech Res Inst | A writing circuit for a phase change memory |
TW200908294A (en) | 2007-08-14 | 2009-02-16 | Ind Tech Res Inst | Phase-change memory |
CN101369450A (en) | 2007-08-17 | 2009-02-18 | 财团法人工业技术研究院 | Sensing circuit of phase-change memory |
TW200913252A (en) | 2007-09-04 | 2009-03-16 | Ind Tech Res Inst | Phase change memory device and fabrications thereof |
CN101383397A (en) | 2007-09-04 | 2009-03-11 | 财团法人工业技术研究院 | Phase change memory device and fabrication method thereof |
US7678606B2 (en) | 2007-09-04 | 2010-03-16 | Industrial Technology Research Institute | Phase change memory device and fabrication method thereof |
US7796455B2 (en) | 2007-09-21 | 2010-09-14 | Industrial Technology Research Institute | Device controlling phase change storage element and method thereof |
TW200915318A (en) | 2007-09-21 | 2009-04-01 | Ind Tech Res Inst | Device controlling phase change storage element and method of increasing realibility of phase change storage elememt |
CN101414480A (en) | 2007-10-19 | 2009-04-22 | 财团法人工业技术研究院 | Control device for phase-change memory cell and method for adding phase-change memory cell reliability |
US7773410B2 (en) | 2007-11-08 | 2010-08-10 | Industrial Technology Research Institute | Writing system and method for phase change memory |
TW200921682A (en) | 2007-11-08 | 2009-05-16 | Ind Tech Res Inst | Writing system and method for a phase change memory |
US7885109B2 (en) | 2007-12-03 | 2011-02-08 | Industrial Technology Research Institute | Memory and method for dissipation caused by current leakage |
TW200926186A (en) | 2007-12-03 | 2009-06-16 | Ind Tech Res Inst | Memory and method for reducing power dissipation caused by current leakage |
CN101452743A (en) | 2007-12-05 | 2009-06-10 | 财团法人工业技术研究院 | Writing-in system and method for phase change memory |
TWI328816B (en) | 2007-12-06 | 2010-08-11 | Ind Tech Res Inst | Phase change memory and method of controlling phase change memory |
US7773411B2 (en) | 2007-12-06 | 2010-08-10 | Industrial Technology Research Institute | Phase change memory and control method thereof |
CN101471130A (en) | 2007-12-25 | 2009-07-01 | 财团法人工业技术研究院 | Phase-change memory device and its control method |
US20090189142A1 (en) | 2008-01-25 | 2009-07-30 | Industrial Technology Research Institute | Phase-Change Memory |
CN101504968A (en) | 2008-01-25 | 2009-08-12 | 财团法人工业技术研究院 | Phase-change memory and its production method |
TW200937693A (en) | 2008-01-25 | 2009-09-01 | Ind Tech Res Inst | Phase-change memory and method for fabricating the same |
CN101504863A (en) | 2008-02-05 | 2009-08-12 | 财团法人工业技术研究院 | Memory and method for suppressing energy consumption of memory leakage current |
US20090296458A1 (en) | 2008-05-27 | 2009-12-03 | Samsung Electronics Co., Ltd. | Resistance variable memory device and method of writing data |
TW200951981A (en) | 2008-06-02 | 2009-12-16 | Ind Tech Res Inst | Memory and writing method thereof |
US7889547B2 (en) | 2008-06-02 | 2011-02-15 | Industrial Technology Research Institute | Memory and writing method thereof |
US7858961B2 (en) | 2008-06-03 | 2010-12-28 | Industrial Technology Research Institute | Phase change memory devices and methods for fabricating the same |
TW200952169A (en) | 2008-06-03 | 2009-12-16 | Ind Tech Res Inst | Phase-change memory devices and methods for fabricating the same |
CN101599301A (en) | 2008-06-06 | 2009-12-09 | 财团法人工业技术研究院 | Storer and memory-writing method |
US7919768B2 (en) | 2008-07-11 | 2011-04-05 | Industrial Technology Research Institute | Phase-change memory element |
TW201003851A (en) | 2008-07-11 | 2010-01-16 | Ind Tech Res Inst | Phase change memory and method for fabricating the same |
CN101626060A (en) | 2008-07-11 | 2010-01-13 | 财团法人工业技术研究院 | Phase-change memory element |
CN101740716A (en) | 2008-11-12 | 2010-06-16 | 财团法人工业技术研究院 | Phase-change memory element and its forming method |
US20100117050A1 (en) | 2008-11-12 | 2010-05-13 | Industrial Technology Research Institute | Phase-change memory element |
TW201019467A (en) | 2008-11-12 | 2010-05-16 | Ind Tech Res Inst | Phase-change memory element and method for fabricating the same |
TW201025326A (en) | 2008-12-30 | 2010-07-01 | Ind Tech Res Inst | Verification circuits and methods for phase change memory |
US7974122B2 (en) | 2008-12-30 | 2011-07-05 | Industrial Technology Research Institute | Verification circuits and methods for phase change memory array |
US20100165723A1 (en) | 2008-12-31 | 2010-07-01 | Industrial Technology Research Institute | Phase change memory |
TW201025573A (en) | 2008-12-31 | 2010-07-01 | Ind Tech Res Inst | Phase change memory |
US8199561B2 (en) | 2008-12-31 | 2012-06-12 | Higgs Opl. Capital Llc | Phase change memory |
US20120230099A1 (en) | 2008-12-31 | 2012-09-13 | Higgs Opl. Capitol LLC | Phase change memory |
CN101814323A (en) | 2009-02-23 | 2010-08-25 | 财团法人工业技术研究院 | Verification circuit and method of phase change memory array |
CN101819816A (en) | 2009-02-27 | 2010-09-01 | 财团法人工业技术研究院 | Phase change memory |
Non-Patent Citations (2)
Title |
---|
J.H. Yi et al., "Novel Cell Structure of PRAM With Thin Metal Layer Inserted GeSbTe", IEEE, IEDM '03 Technical Digest; 2003; pp. 901-904. |
Stolowitz Ford Cowger LLP, "Listing of Related Cases", Oct. 1, 2013, 1 page. |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8982634B2 (en) * | 2012-07-11 | 2015-03-17 | Ememory Technology Inc. | Flash memory |
Also Published As
Publication number | Publication date |
---|---|
TWI402845B (en) | 2013-07-21 |
TW201025326A (en) | 2010-07-01 |
US7974122B2 (en) | 2011-07-05 |
US20100165720A1 (en) | 2010-07-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
USRE45035E1 (en) | Verification circuits and methods for phase change memory array | |
US10530347B2 (en) | Receiver-side setup and hold time calibration for source synchronous systems | |
CN107093459B (en) | Nonvolatile memory device, reading method thereof, and memory system | |
KR101310991B1 (en) | Read distribution management for phase change memory | |
JP4129170B2 (en) | Semiconductor memory device and memory data correction method for memory cell | |
TWI431632B (en) | Digitally-controllable delay for sense amplifier | |
US6813208B2 (en) | System and method for sensing data stored in a resistive memory element using one bit of a digital count | |
US9070438B2 (en) | Programming of phase-change memory cells | |
TW201118876A (en) | Voltage compensation circuit, multi-level memory device with the same, and voltage compensation method for reading the multi-level memory device | |
US20080144363A1 (en) | Method of testing pram device | |
KR102508925B1 (en) | A memory device | |
EP3680905B1 (en) | Random code generator | |
US7450446B2 (en) | Semiconductor memory device having delay circuit | |
KR100656432B1 (en) | Apparatus and method for controlling column selecting signal of semiconductor memory | |
US10490240B2 (en) | Semiconductor memory device capable of correctly reading data | |
CN111627477A (en) | Nonvolatile memory device for performing read operation and method of operating the same | |
KR101933645B1 (en) | Phase change memory device, method of generating operation voltage of the same and memory system having the same | |
US10908636B2 (en) | Skew correction for source synchronous systems | |
US7936629B2 (en) | Table-based reference voltage characterization scheme | |
US8184469B2 (en) | Stored multi-bit data characterized by multiple-dimensional memory states | |
JP2734017B2 (en) | Non-volatile memory | |
JP2004362756A5 (en) | ||
KR100333711B1 (en) | An apparatus and method for generating a reference voltage in ferroelectric RAM | |
US7463524B2 (en) | Reading and writing method for non-volatile memory with multiple data states | |
JP2014203469A (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: HIGGS OPL. CAPITAL LLC, DELAWARE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE;REEL/FRAME:032544/0907 Effective date: 20111122 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: GULA CONSULTING LIMITED LIABILITY COMPANY, DELAWAR Free format text: MERGER;ASSIGNOR:HIGGS OPL. CAPITAL LLC;REEL/FRAME:037360/0803 Effective date: 20150826 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |