CN101814323A - Verification circuit and method of phase change memory array - Google Patents
Verification circuit and method of phase change memory array Download PDFInfo
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- CN101814323A CN101814323A CN200910007575A CN200910007575A CN101814323A CN 101814323 A CN101814323 A CN 101814323A CN 200910007575 A CN200910007575 A CN 200910007575A CN 200910007575 A CN200910007575 A CN 200910007575A CN 101814323 A CN101814323 A CN 101814323A
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- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
- G11C2013/0066—Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0076—Write operation performed depending on read result
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Abstract
The invention relates to a verification circuit, which is application to a phase change memory array. The verification circuit comprises a sensing unit, a comparator, a control unit, an arithmetic unit and an adjusting unit. The sensing unit senses a sensing voltage from one memory cell of the phase change memory array according to an enable signal. The comparator generates a comparison signal according to the sensing voltage and a reference voltage in order to indicate if the memory cell is in a resetting state. The control unit generates a control signal according to the enable signal. The arithmetic unit generates a first signal according to the control signal in order to indicate if the comparator runs. The adjusting unit provides write current for the memory cell and adjusts the write current according to the control signal until the comparison signal indicates that the memory cell is in the resetting state.
Description
Technical field
The present invention is relevant for a kind of proof scheme, particularly relevant for a kind of proof scheme of phase change memory array.
Background technology
Phase change memorizer (Phase Change Memory, PCM) be a kind of nonvolatile memory with high speed, high capacity density and low power consuming, wherein the phase-change memory cells in phase change memorizer system is formed by phase change material, for example sulphur based material (Chalcogenide) etc.Under the operation that heat is used, phase change material can be switched between crystallization (crystalline) state and noncrystalline (amorphous) state, wherein phase change material has different resistance values under crystalline state and non-crystalline state, and it can represent different storage datas respectively.
Generally speaking, can phase-change memory cells be heated to change its resistance value, make data to be stored in the phase change memorizer by the write current with different current values is provided.In addition, for phase-change memory cells, also needing to provide write current is Reset Status (reset state) with the phase-change memory cells transition.Therefore, needing a kind of proof scheme to verify phase change memory array, is Reset Status with phase-change memory cells by non-Reset Status transition.
Summary of the invention
The invention provides a kind of proof scheme, be applicable to a phase change memory array.Above-mentioned proof scheme comprises: a sensing cell, in order to sense one first sensing voltage from one first storage unit of above-mentioned phase change memory array according to an enable signal; One comparer is in order to produce a comparison signal according to above-mentioned first sensing voltage and a reference voltage, so that indicate whether above-mentioned first storage unit is Reset Status; One control module is in order to produce a control signal according to above-mentioned enable signal; Whether one arithmetic element is in order to produce one first signal, so that indicate above-mentioned comparer to operate according to above-mentioned control signal; And, an adjustment unit, in order to providing a write current to above-mentioned first storage unit, and the size of adjusting above-mentioned write current according to above-mentioned control signal to indicate above-mentioned first storage unit up to above-mentioned comparison signal be Reset Status.
Moreover, the invention provides a kind of verification method, be applicable to a phase change memory array.Storage unit to above-mentioned phase change memory array reads, to obtain a sensing voltage.Then, a more above-mentioned sensing voltage and a reference voltage.When above-mentioned sensing voltage during less than above-mentioned reference voltage, provide a write current to above-mentioned storage unit, and the magnitude of current that increases above-mentioned write current gradually up to corresponding to the above-mentioned sensing voltage of the magnitude of current of above-mentioned write current more than or equal to above-mentioned reference voltage.
Moreover, the invention provides another kind of verification method, be applicable to a phase change memory array.Provide a write current to one first storage unit of above-mentioned phase change memory array, and the magnitude of current that increases above-mentioned write current gradually up to one first sensing voltage that is sensed from above-mentioned first storage unit more than or equal to a reference voltage.When above-mentioned first sensing voltage during more than or equal to above-mentioned reference voltage, the magnitude of current of noting down above-mentioned write current is with as a reference current amount.One second storage unit to above-mentioned phase change memory array reads, to obtain one second sensing voltage.Whether more above-mentioned second sensing voltage and above-mentioned reference voltage are Reset Status to judge above-mentioned second storage unit.When above-mentioned second storage unit is non-Reset Status, provide above-mentioned write current to above-mentioned second storage unit with above-mentioned reference current amount, be Reset Status to change above-mentioned second storage unit.
Description of drawings
The 1st figure is that demonstration is according to the described proof scheme of one embodiment of the invention;
The 2nd figure is the signal waveforms that shows proof scheme among the 1st figure;
3A figure system shows the circuit diagram according to the described control module of one embodiment of the invention;
3B figure system shows the circuit diagram according to the described detecting unit of one embodiment of the invention;
3C figure system shows the circuit diagram according to the described computing unit of one embodiment of the invention;
The 4th figure is that demonstration is according to the described proof scheme of another embodiment of the present invention;
5A and 5B figure system show that proof scheme is to the internal signal waveforms figure of different storage unit execution proving programs among the 4th figure;
The 6th figure is the verification method of demonstration according to the described checking phase change of one embodiment of the invention storage array; And
The 7th figure is the verification method of demonstration according to the described checking phase change of another embodiment of the present invention storage array.
[primary clustering symbol description]
110～proof scheme;
112～sensing cell;
114～comparer;
118～arithmetic element;
116～control module;
330,380～phase inverter;
120,122～switch;
124,340,350～delay cell;
126,390～trigger;
128～judging unit;
130～adjustment unit;
132～write current maker;
134～computing unit;
150～phase change memory array;
310～detecting unit;
320～rejection gate;
360,370～mutual exclusion or door;
436～buffer;
D～adjustment signal;
Signal is adjusted in Dref～reference;
Iwrite～write current;
Rcell～resistance value;
S1, S2, Sclk～signal;
S602-S608, S702-S710～step;
Sc～comparison signal;
Sctr1～control signal;
Sver～validation signal;
SEN～enable signal;
TR～read cycle;
TW～write cycle;
Vcell～sensing voltage;
VDD～voltage; And
Vref～reference voltage.
Embodiment
For above-mentioned and further feature of the present invention and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphicly, be described in detail below:
Embodiment:
The 1st figure is that demonstration is according to the described proof scheme 110 of one embodiment of the invention, in order to verify whether each storage unit in the phase change memory array 150 is (reset) state of resetting.Proof scheme 110 comprises sensing cell 112, comparer 114, control module 116, arithmetic element 118, delay cell 124, trigger 126, judging unit 128, adjustment unit 130 and two switches 120 and 122.Arithmetic element 118 is coupled between control module 116 and the delay cell 124, in order to receive control signal Sctrl to produce signal S1, so that whether indication comparer 114 operates.Delay cell 124 receive delay signal S1 to be producing signal S2, and signal S2 is provided the clock pulse input end to trigger 126.In addition, trigger 126 has the data input pin that is coupled to switch 120, and the data output end that is coupled to judging unit 128.
When receiving the enable signal SEN that judging unit 128 provided, storage unit in 112 pairs of phase change memory arrays of sensing cell 150 reads, with the resistance value Rcell of this storage unit of sensing, so that obtain sensing voltage Vcell corresponding to resistance value Rcell.114 couples of sensing voltage Vcell of comparer and reference voltage Vref compare, and indicate the state of the storage unit that is read in order to comparison signal Sc to be provided.For example, as sensing voltage Vcell during less than reference voltage Vref, the storage unit that comparison signal Sc indication is read as yet not transition become Reset Status.And as sensing voltage Vcell during more than or equal to reference voltage Vref, the storage unit that comparison signal Sc indication is read has been a Reset Status by transition.
In addition, judging unit 128 also can provide enable signal SEN to control module 116 to produce control signal Sctrl.Whether control signal Sctrl can produce signal S1 through arithmetic element 118 and control comparer 114 and act on.Then, comparison signal Sc can gauge tap 120 and whether conducting of switch 122.Switch 120 is coupled between control module 116 and the adjustment unit 130, and switch 122 is coupled between voltage VDD and the switch 120, and wherein switch 120 and switch 122 are controlled by comparison signal Sc.Therefore, when the storage unit that is read was non-Reset Status, comparison signal Sc meeting gauge tap 120 and switch 122 were adjusted to control signal Sctrl signal Sclk and are sent to adjustment unit 130 and trigger 126.With reference to the 1st figure and the 2nd figure, the 2nd figure is the signal waveforms that shows proof scheme 110 among the 1st figure simultaneously.Control signal Sctrl and signal Sclk can be considered have the different operating cycle pulse signal of (duty cycle).In addition, adjustment unit 130 comprises write current maker 132 and computing unit 134.But the number of pulses of computing unit 134 signal calculated Sclk is adjusted signal D to produce, and wherein adjusts signal D system and is made up of plural byte.In this embodiment, adjust signal D and comprise a D0, D1, D2 and D3.Then, write current maker 132 can produce write current Iwrite this storage unit to phase change memory array according to adjusting signal D, so that this storage unit is carried out transition.Moreover write current maker 132 also can be according to adjusting the magnitude of current that signal D adjusts write current Iwrite, and promptly write current Iwrite has corresponding to the magnitude of current of adjusting signal D.In the present invention, the figure place of adjustment signal D can determine the resolution of the magnitude of current of write current Iwrite.
With reference to the 2nd figure, in read cycle TR, control signal Sctrl is a high-voltage level.Simultaneously, sensing circuit 112 can sense sensing voltage Vcell from this storage unit, and promptly 110 pairs of these storage unit of proof scheme read.In period T W, adjusting circuit 130 can provide the write current Iwrite that has corresponding to the magnitude of current of adjusting signal D to this storage unit, so that change the resistance value of this storage unit.For example, the data value of adjusting signal D be " 0010 " during, proof scheme 110 is understood the write current Iwrite that provide corresponding to the magnitude of current of " 0010 " to this storage unit during period T W.Then, proof scheme 110 can be during period T R sensing and judge whether this storage unit is Reset Status.If not, then proof scheme 110 can provide write current Iwrite corresponding to the magnitude of current of " 0011 " to this storage unit during next cycle TW.Therefore, if when this storage unit is non-Reset Status, the magnitude of current that proof scheme 110 can increase write current Iwrite gradually is Reset Status up to this storage unit by transition.For example, the data value of adjusting signal D be " 1000 " during, proof scheme 110 is understood the write current Iwrite that provide corresponding to the magnitude of current of " 1000 " to this storage unit during period T W.Then, proof scheme 110 can read this storage unit to obtain the sensing voltage Vcell corresponding to the magnitude of current of " 1000 " during period T R.Because present resulting sensing voltage Vcell is more than or equal to reference voltage Vref, thus comparison signal Sc can to indicate this storage unit be Reset Status by transition.Then, trigger 126 can produce validation signal Sver to judging unit 128, to provide next enable signal SEN to sensing cell 112, so that another storage unit is verified.
3A figure system shows the circuit diagram according to the described control module of one embodiment of the invention.Corresponding to four adjustment signal D, control module is made up of 320 and 4 phase inverters 330 of 310,5 rejection gates of 16 detecting units (NOR).3B figure system shows the circuit diagram according to the described detecting unit of one embodiment of the invention.Detecting unit comprises two delay cells 340 and 350, two mutual exclusions or door (XOR) 360 and 370, phase inverter 380 and trigger 390.In proof scheme, determined by delay cell 340 cycle length of read cycle TR, and write cycle TW and the total cycle time of read cycle TR determined by delay cell 350.3C figure system shows the circuit diagram according to the described computing unit of one embodiment of the invention.In this embodiment, computing unit is a totalizer, and it comprises four triggers.
The 4th figure is that demonstration is according to the described proof scheme 410 of another embodiment of the present invention.Adjustment circuit 130 in the proof scheme 110 of the 1st figure is adjusted circuit 430 and is more comprised buffer 436.As described previously, when comparison signal Sc indication storage unit had been Reset Status by transition, trigger 126 can produce validation signal Sver to judging unit 128, so that another storage unit is verified.Simultaneously, trigger 126 also can provide validation signal Sver to buffer 436, in order to will being stored in the buffer 436 corresponding to the present adjustment signal D of the magnitude of current of write current, with as with reference to adjustment signal Dref.Then, judging unit 128 can provide next enable signal SEN to buffer 436, so that the reference adjustment signal Dref that will be stored in the buffer 436 is sent to computing unit 134.Then, the data value that computing unit 134 will be adjusted signal D is set for reference to the data value of adjusting signal Dref, make the write current generation unit to provide to have corresponding to reference to the write current Iwrite of the magnitude of current of adjusting signal Dref to another storage unit.
5A and 5B figure system show the internal signal waveforms figure of 410 pairs of different storage unit execution proving programs of proof scheme among the 4th figure.With reference to the 4th figure and 5A figure, at first, 410 couples of storage unit Cell 1 of proof scheme verify.As described previously, proof scheme 410 adjust signal D for " 1000 " during in to sense storage unit Cell 1 be Reset Status by transition.Then, buffer 436 can store the data value that " 1000 " are reference adjustment signal Dref according to validation signal Sver.Then, 410 couples of storage unit Cell 2 of proof scheme verify.Buffer 436 can provide according to the enable signal SEN corresponding to storage unit Cell2 with reference to adjusting signal Dref to computing unit 134, with the calculating initial value (initial value) as adjustment signal D.For storage unit Cell 2, at first, 410 couples of storage unit Cell 2 of proof scheme read.Then, when proof scheme 410 senses storage unit Cell 2 for non-Reset Status, proof scheme 410 can provide have corresponding to reference to the write current Iwrite of the magnitude of current of adjusting signal Dref to storage unit Cell 2, promptly computing unit 134 can provide have data value " 1000 " adjustment signal D to write current generation unit 132 so that produce write current Iwrite.Then, proof scheme 410 can be during period T R reading cells Cell 2 to obtain sensing voltage Vcell corresponding to the magnitude of current of " 1000 ".Because the sensing voltage Vcell that obtains at present is more than or equal to reference voltage Vref, then can to indicate storage unit Cell 2 be Reset Status by transition to comparison signal Sc.Then, trigger 126 can produce validation signal Sver to judging unit 128, finish in order to the checking of notice storage unit Cell 2, and the checking of carrying out next storage unit is all finished up to the checking of each storage unit.So, can reduce proving time of phase change storage array.
With reference to the 4th figure and 5B figure, after the checking of finishing storage unit Cell 1, the data value " 1000 " of adjusting signal D is stored in the buffer 436 to adjust the data value of signal Dref as reference.Then, when proof scheme 410 senses storage unit Cell 2 for non-Reset Status, proof scheme 410 can provide have corresponding to reference to the write current Iwrite of the magnitude of current of adjusting signal Dref to storage unit Cell 2.Then, proof scheme 410 meeting reading cells Cell 2 during period T R are to obtain the sensing voltage Vcell corresponding to the magnitude of current of " 1000 ".As sensing voltage Vcell during less than reference voltage Vref (storage unit Cell 2 is non-Reset Status), it is Reset Status up to storage unit Cell 2 by transition that proof scheme 410 can increase the write current Iwrite magnitude of current gradually according to adjustment signal D, as shown in 5B figure.In this embodiment, computing unit 134 can be with reference to the data value " 1000 " of adjusting signal Dref with as calculating initial value and increasing the data value of adjusting signal D according to the number of pulses of signal Sclk.
The 6th figure is the verification method of demonstration according to the described checking phase change of one embodiment of the invention storage array.At first, at step S602, a storage unit of phase change memory array is read, to obtain sensing voltage.Then, sensing voltage and reference voltage are compared, with judge this storage unit whether transition be Reset Status (step S604).Then, at step S606, when sensing voltage during less than reference voltage (this storage unit is non-Reset Status), provide write current to this storage unit, and the magnitude of current that increases write current gradually up to corresponding to the sensing voltage of the magnitude of current of write current more than or equal to reference voltage, promptly this storage unit is a Reset Status, then finishes the checking to this storage unit.
The 7th figure is the verification method of demonstration according to the described checking phase change of another embodiment of the present invention storage array.At first, at step S702, first storage unit of write current to phase change memory array is provided, and the magnitude of current that increases write current gradually up to first sensing voltage that is sensed from first storage unit more than or equal to a reference voltage, promptly first storage unit is converted into Reset Status.Then, when first storage unit is converted into Reset Status, with the electricity flow records of write current and save as reference current amount (step S704).Then, second storage unit of phase change memory array is read, to obtain second sensing voltage (step S706).Whether then, second sensing voltage and reference voltage are compared, be Reset Status (step S708) to judge second storage unit.When second storage unit is non-Reset Status, provide the storage unit of the write current to the second with reference current amount, being Reset Status (step S710) with the second storage unit transition.When corresponding to second sensing voltage of the magnitude of current of write current during less than reference voltage, second storage unit is non-Reset Status.Therefore, the magnitude of current that can increase write current gradually up to corresponding to second sensing voltage of the magnitude of current of write current more than or equal to above-mentioned reference voltage, can be Reset Status then with the second storage unit transition.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit scope of the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (19)
1. a proof scheme is applicable to a phase change memory array, comprising:
One sensing cell is in order to sense one first sensing voltage according to an enable signal from one first storage unit of above-mentioned phase change memory array;
One comparer is in order to produce a comparison signal according to above-mentioned first sensing voltage and a reference voltage, so that indicate whether above-mentioned first storage unit is Reset Status;
One control module is in order to produce a control signal according to above-mentioned enable signal;
One arithmetic element, in order to produce one first signal according to above-mentioned control signal, so that indicate above-mentioned comparer whether to operate, and;
One adjustment unit, in order to providing a write current to above-mentioned first storage unit, and the size of adjusting above-mentioned write current according to above-mentioned control signal to indicate above-mentioned first storage unit up to above-mentioned comparison signal be Reset Status.
2. proof scheme as claimed in claim 1, wherein when above-mentioned first sensing voltage during less than above-mentioned reference voltage, it is non-Reset Status that above-mentioned comparison signal is indicated above-mentioned first storage unit, and when above-mentioned first sensing voltage during more than or equal to above-mentioned reference voltage, it is Reset Status that above-mentioned comparison signal is indicated above-mentioned first storage unit.
3. proof scheme as claimed in claim 2, wherein when above-mentioned comparison signal indicated above-mentioned first storage unit to be non-Reset Status, above-mentioned adjustment unit increased the magnitude of current of above-mentioned write current gradually according to above-mentioned control signal.
4. proof scheme as claimed in claim 1, wherein above-mentioned control signal is a pulse signal, and when above-mentioned control signal is one first voltage level, above-mentioned sensing circuit is from above-mentioned first sensing voltage of the above-mentioned first storage unit sensing, and when above-mentioned control signal was one second voltage level, above-mentioned adjustment circuit provided above-mentioned write current to above-mentioned first storage unit.
5. proof scheme as claimed in claim 4 more comprises:
One first switch, have one first end that is coupled to above-mentioned control circuit and one second end that is coupled to above-mentioned adjustment circuit, whether wherein above-mentioned first switch determines the above-mentioned control signal of above-mentioned control circuit is sent to above-mentioned adjustment circuit according to above-mentioned comparison signal; And
One second switch is coupled between a specific voltage and above-mentioned second end, has a control end in order to receive above-mentioned comparison signal.
6. proof scheme as claimed in claim 5 more comprises:
One delay cell is in order to postpone above-mentioned first signal to produce a secondary signal;
One trigger has a data input pin and is coupled to above-mentioned second end, a clock pulse input end in order to receive an above-mentioned secondary signal and a data output end in order to a validation signal to be provided; And
One judging unit is in order to provide above-mentioned enable signal to above-mentioned control module.
7. proof scheme as claimed in claim 6, wherein above-mentioned adjustment unit more comprises:
One computing unit has one of plural byte in order to the number of pulses of calculating above-mentioned control signal with generation and adjusts signal; And
One write current maker, in order to produce above-mentioned write current, wherein above-mentioned write current has the magnitude of current corresponding to above-mentioned adjustment signal, and when above-mentioned comparison signal indicated above-mentioned first storage unit to be Reset Status, above-mentioned write current had a reference current amount.
8. proof scheme as claimed in claim 7, wherein above-mentioned adjustment unit more comprises:
One buffer is in order to store above-mentioned reference current amount.
9. proof scheme as claimed in claim 6, wherein when above-mentioned comparison signal indicates above-mentioned first storage unit to be Reset Status, above-mentioned judging unit provides above-mentioned enable signal to above-mentioned sensing cell according to above-mentioned validation signal, makes above-mentioned sensing cell sense one second sensing voltage according to above-mentioned enable signal from one second storage unit of above-mentioned phase change memory array.
10. proof scheme as claimed in claim 9, wherein when above-mentioned comparison signal indicates above-mentioned first storage unit to be Reset Status, above-mentioned judging unit provides above-mentioned enable signal to above-mentioned control module according to above-mentioned validation signal, makes above-mentioned control module produce above-mentioned control signal according to above-mentioned enable signal.
11. proof scheme as claimed in claim 10, above-mentioned adjustment unit provide the above-mentioned write current with above-mentioned reference current amount to above-mentioned second storage unit according to above-mentioned control signal.
12. proof scheme as claimed in claim 11, wherein above-mentioned comparer produces above-mentioned comparison signal according to above-mentioned second sensing voltage and the above-mentioned reference voltage corresponding to above-mentioned reference current amount, so that indicate whether above-mentioned second storage unit is Reset Status.
13. proof scheme as claimed in claim 12, wherein when corresponding to above-mentioned second sensing voltage of above-mentioned reference current amount during more than or equal to above-mentioned reference voltage, it is Reset Status that above-mentioned comparison signal is indicated above-mentioned second storage unit, and when corresponding to above-mentioned second sensing voltage of above-mentioned reference current amount during less than above-mentioned reference voltage, it is non-Reset Status that above-mentioned comparison signal is indicated above-mentioned second storage unit.
14. proof scheme as claimed in claim 13, wherein when above-mentioned comparison signal indicates above-mentioned second storage unit to be non-Reset Status, above-mentioned adjustment unit increases the magnitude of current of the above-mentioned write current that is provided to above-mentioned second storage unit gradually according to above-mentioned control signal, makes the magnitude of current of above-mentioned write current greater than above-mentioned reference current amount.
15. a verification method is applicable to a phase change memory array, comprising:
Read a storage unit of above-mentioned phase change memory array, to obtain a sensing voltage;
A more above-mentioned sensing voltage and a reference voltage;
When above-mentioned sensing voltage during less than above-mentioned reference voltage, provide a write current to above-mentioned storage unit, and the magnitude of current that increases above-mentioned write current gradually up to corresponding to the above-mentioned sensing voltage of the magnitude of current of above-mentioned write current more than or equal to above-mentioned reference voltage.
16. verification method as claimed in claim 15, wherein when corresponding to the above-mentioned sensing voltage of the magnitude of current of above-mentioned write current during more than or equal to above-mentioned reference voltage, said memory cells is a Reset Status, and when corresponding to the above-mentioned sensing voltage of the magnitude of current of above-mentioned write current during less than above-mentioned reference voltage, said memory cells is non-Reset Status.
17. a verification method is applicable to a phase change memory array, comprising:
Provide a write current to one first storage unit of above-mentioned phase change memory array, and the magnitude of current that increases above-mentioned write current gradually up to one first sensing voltage that is sensed from above-mentioned first storage unit more than or equal to a reference voltage;
When above-mentioned first sensing voltage during more than or equal to above-mentioned reference voltage, the magnitude of current of noting down above-mentioned write current is with as a reference current amount;
One second storage unit to above-mentioned phase change memory array reads, to obtain one second sensing voltage;
Whether more above-mentioned second sensing voltage and above-mentioned reference voltage are Reset Status to judge above-mentioned second storage unit;
When above-mentioned second storage unit is non-Reset Status, provide above-mentioned write current to above-mentioned second storage unit with above-mentioned reference current amount, be Reset Status to change above-mentioned second storage unit.
18. verification method as claimed in claim 17 more comprises:
When corresponding to above-mentioned second sensing voltage of above-mentioned reference current amount during less than above-mentioned reference voltage, the magnitude of current that increases above-mentioned write current gradually up to corresponding to above-mentioned second sensing voltage of the magnitude of current of above-mentioned write current more than or equal to above-mentioned reference voltage.
19. verification method as claimed in claim 18, wherein when corresponding to above-mentioned second sensing voltage of the magnitude of current of above-mentioned write current during more than or equal to above-mentioned reference voltage, above-mentioned second storage unit is a Reset Status, and when corresponding to above-mentioned second sensing voltage of the magnitude of current of above-mentioned write current during less than above-mentioned reference voltage, above-mentioned second storage unit is non-Reset Status.
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| US8605493B2 (en) | 2008-12-31 | 2013-12-10 | Higgs Opl. Capital Llc | Phase change memory |
| USRE45035E1 (en) | 2008-12-30 | 2014-07-22 | Higgs Opl. Capital Llc | Verification circuits and methods for phase change memory array |
| USRE45189E1 (en) | 2007-11-08 | 2014-10-14 | Higgs Opl. Capital Llc | Writing system and method for phase change memory |
| CN108597558A (en) * | 2018-04-23 | 2018-09-28 | 中国科学院上海微系统与信息技术研究所 | It is preferred that the system and method for phase transition storage write-operation current |
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| CN101369450B (en) * | 2007-08-17 | 2011-03-16 | 财团法人工业技术研究院 | Sensing circuit of phase-change memory and sensing method |
| CN101236780B (en) * | 2008-02-26 | 2012-07-04 | 中国科学院上海微系统与信息技术研究所 | Circuit design standard and implementation method for 3-D solid structure phase change memory chip |
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2009
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE45189E1 (en) | 2007-11-08 | 2014-10-14 | Higgs Opl. Capital Llc | Writing system and method for phase change memory |
| USRE45035E1 (en) | 2008-12-30 | 2014-07-22 | Higgs Opl. Capital Llc | Verification circuits and methods for phase change memory array |
| US8605493B2 (en) | 2008-12-31 | 2013-12-10 | Higgs Opl. Capital Llc | Phase change memory |
| CN108597558A (en) * | 2018-04-23 | 2018-09-28 | 中国科学院上海微系统与信息技术研究所 | It is preferred that the system and method for phase transition storage write-operation current |
| CN108597558B (en) * | 2018-04-23 | 2020-10-20 | 中国科学院上海微系统与信息技术研究所 | System and method for optimizing write operation current of phase change memory |
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| CN101814323B (en) | 2013-06-12 |
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