USRE45189E1 - Writing system and method for phase change memory - Google Patents
Writing system and method for phase change memory Download PDFInfo
- Publication number
- USRE45189E1 USRE45189E1 US13/571,798 US201213571798A USRE45189E US RE45189 E1 USRE45189 E1 US RE45189E1 US 201213571798 A US201213571798 A US 201213571798A US RE45189 E USRE45189 E US RE45189E
- Authority
- US
- United States
- Prior art keywords
- writing
- data
- circuit
- current
- pcm cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
- 238000000034 method Methods 0.000 title claims abstract description 89
- 238000001514 detection method Methods 0.000 claims description 4
- 230000004044 response Effects 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 18
- 239000011159 matrix material Substances 0.000 description 5
- 230000007423 decrease Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000012782 phase change material Substances 0.000 description 2
- 230000002860 competitive effect Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
Definitions
- the invention relates to a writing system and method for a phase change memory.
- phase change memory is the most competitive next generation non-volatile memory due to its higher speed, lower power consumption, higher capacity, reliability, easier process integration and lower cost.
- phase change memory The operation of a phase change memory is mainly achieved by inputting two current pulses with different current magnitudes to the phase change memory to switch the phase change memory between an amorphous state and crystalline state.
- the phase change memory According to Ohm-Joule's Law, when the current is input to the phase change memory, the phase change memory is heated.
- the phase change memory may thus be crystallized or melted based on different currents.
- the logic state of the phase change memory can be switched by inputting different currents, enabling data storage.
- FIG. 1 is a schematic diagram showing the writing current pulse and the reading current pulse of the phase change memory.
- phase change memory When a RESET operation is applied to the phase change memory, a reset current I RESET with high amplitude and short pulse width is applied, the phase change memory is thus melted because the temperature of the phase change memory exceeds the melting temperature of the phase change material of the phase change memory, T m . When the temperature of the phase change memory decreases, the state of the phase change memory is transformed to the amorphous state due to the insufficient cool down period. Thus, the phase change memory has high resistance. When a SET operation is applied to the phase change memory, a set current I SET with lower amplitude and longer pulse width is applied.
- the phase change memory is heated by the set current I SET , and the temperature of the phase change memory is held substantially between the melting temperature T m and a crystallizing temperature T c of the phase change material used by the phase change memory.
- T m melting temperature
- T c crystallizing temperature
- the phase change memory respectively stores data with logic state 1 and 0 by the RESET operation and the SET operation.
- a read current I READ the amplitude of which is less than the set current I SET , is applied to the phase change memory to determine the logic state of the data stored in the phase change memory based on the sensed resistance.
- the writing system comprises a first phase change memory (PCM) cell, a second PCM cell, a first writing circuit and a verifying circuit.
- the first writing circuit executes a writing procedure, receives and writes a first data to the first PCM cell.
- the verifying circuit executes a verifying procedure and the circuit further comprises a processing unit and a second writing circuit.
- the processing unit reads and compares the data stored in the second PCM cell with a second data.
- the second writing circuit writes the second data to the second PCM cell when the data stored in the second PCM cell and the second data are not matched.
- An embodiment of the invention provides a writing method for a phase change memory and the method is implemented by a first writing circuit and a verifying circuit.
- the method comprises performing a writing procedure to a first phase change memory (PCM) cell in a first cycle; performing a verifying procedure to a second PCM cell in the first cycle; and if the verifying result of the second PCM cell is matched, the verifying circuit outputs a current adjustment signal to the first writing circuit to adjust a first writing current output by the first writing circuit.
- PCM phase change memory
- FIG. 1 is a schematic diagram showing the writing current pulse and the reading current pulse of the phase change memory.
- FIG. 2 is a current-resistance characteristic curve diagram of a phase change memory.
- FIG. 3 is a schematic diagram of the control circuit for the phase change memory according to an embodiment of the invention.
- FIG. 4 is a flowchart of the writing procedure and the verifying procedure according to an embodiment of the invention.
- FIG. 5 is a timing diagram of a conventional writing procedure and verifying procedure for the phase change memory and the present innovative writing procedure and verifying procedure for the phase change memory.
- FIG. 6 is a schematic diagram of an embodiment of the writing system for the phase change memory according to the invention.
- FIG. 7 is a circuit diagram of a writing circuit and the auxiliary writing circuit according to an embodiment of the invention.
- FIG. 8 is a schematic diagram of a writing system for the phase change memory according to another embodiment of the invention.
- FIG. 2 is a current-resistance characteristic curve diagram of a phase change memory.
- Curve 21 is a current-resistance characteristic curve of a normal phase change memory.
- the resistance of the phase change memory is substantially R SET
- the resistance of the phase change memory is substantially R RESET . If the access number of the phase change memory increases, the current-resistance characteristic curve may drift, such as the curve 22 .
- the set current I SET cannot maintain the resistance of the phase change memory R SET due to the process of the phase change memory. In this situation, a smaller set current I SET and reset current I RESET are required to keep the phase change memory operating normally.
- FIG. 3 is a schematic diagram of the control circuit for the phase change memory according to an embodiment of the invention.
- a read/write splitting structure is applied to increase the performance of the phase change memory.
- the reading and verifying circuit 31 comprises a reading circuit 34 and a verifying circuit 35 to verify the phase change memory cell matrix 33 .
- the writing circuit 32 writes to the bit line 37 of the phase change memory cell matrix 33
- the reading and verifying circuit 31 verifies the PCM cell coupled to the bit line 36 .
- the reading circuit 34 reads and transmits the data stored in the PCM cell coupled to the bit line 36 to the verifying circuit 35 .
- the verifying circuit 35 compares the data from the reading circuit 34 with a reference data.
- the PCM cell matrix 33 can be normally accessed. If the data read by the reading circuit 34 is not the same as the reference data, a control signal is output to the writing circuit 32 to adjust the magnitude of the output current thereof.
- the writing current is more than usual; thus, the W/L ratio of the transistor is also larger than usual to carry the larger writing current.
- the control signal S 1 turns the transistor T 1 on and the writing current can be transmitted to the PCM cell matrix 33 via the transistor T 1 .
- the operation of the transistors T 2 and Tn is the same as the operation of the transistor T 1 .
- the control signal X 1 turns the transistor Y 1 on and the reading current can be transmitted to the PCM cell matrix 33 via the transistor Y 1 .
- the operation of the transistors Y 2 and Yn is the same as the operation of the transistor Y 1 .
- the switches coupled to the writing circuit 32 and the reading circuit 34 are implemented by different transistors with different W/L ratios.
- the switch coupled to the writing circuit 32 is implemented by a transistor with larger W/L ratio, such as the transistor T 1 , to carry a larger current.
- the switch coupled to the reading circuit 34 is implemented by a transistor with smaller W/L ratio, such as the transistor X 1 , to carry a smaller current.
- FIG. 4 is a flowchart of the writing procedure and the verifying procedure according to an embodiment of the invention.
- a writing procedure is first applied to the (N ⁇ 1)th PCM cell, and the procedure jumps to both the step S 42 and step S 43 .
- step S 42 another writing procedure is applied to the Nth PCM cell.
- step S 43 a verifying procedure is applied to the (N ⁇ 1)th PCM cell.
- step S 44 a read current is applied to read the data stored in the (N ⁇ 1)th PCM cell, and a reference data is then compared with the data stored in the (N ⁇ 1)th PCM cell.
- the reference data is the data which was originally written to the (N ⁇ 1)th PCM cell.
- step S 45 a comparison circuit compares the data stored in the (N ⁇ 1)th PCM cell with the reference data. If the data stored in the (N ⁇ 1)th PCM cell is the same as the reference data, the procedure jumps to step S 47 S49. If the data stored in the (N ⁇ 1)th PCM cell is not the same as the reference data, the procedure jumps to step S 46 .
- step S 46 the writing current is adjusted based on the comparison result generated in step S 45 and when the comparison result in the step S 45 is yes, the adjusted writing current is applied to write the (N+1)th PCM cell in step S 49 for executing a writing procedure to the (N+1)th PCM cell in step S 48 .
- the steps S 42 to S 46 are implemented during the same cycle.
- a verifying procedure is also applied to the Nth PCM cell.
- step S 46 after the writing current is adjusted in step S 46 , the procedure jumps to step S 47 to apply a writing procedure to the (N ⁇ 1)th PCM cell.
- the writing current is adjusted based on the comparison result generated in step S 45 .
- the writing procedure in the step S 47 and step S 48 are implemented by different writing circuit.
- FIG. 5 is a timing diagram of a conventional writing procedure and verifying procedure for the phase change memory and the present innovative writing procedure and verifying procedure for the phase change memory.
- Timing diagram 51 shows the timing diagram of a conventional writing procedure and verifying procedure for the phase change memory. The conventional verifying procedure is executed after the writing procedure. If the verifying procedure passes, another writing procedure for the next PCM cell is executed. If the verifying procedure fails, the writing procedure is re-executed for the PCM cell.
- Timing diagram is timing diagram of the present innovative writing procedure and verifying procedure for the phase change memory.
- the writing procedure and the verifying procedure can be implemented by different processing unit. Therefore, the processing time can be significantly reduced.
- the processing unit can be implemented by software or hardware.
- FIG. 6 is a schematic diagram of an embodiment of the writing system for the phase change memory according to the invention.
- the first writing circuit 62 receives and writes a reference data to the phase change memory 63 .
- the verifying unit 61 comprises a processing unit 64 and a second writing circuit 66 .
- the reading circuit 65 outputs a read current to the phase change memory 63 to read the data stored in the phase change memory 63 .
- the processing unit 64 compares the reference data and the data read from the phase change memory 63 read by the reading circuit 65 . If the reference data is the same as the data read from the phase change memory 63 , a verify signal is transmitted to the first writing circuit 62 to maintain the magnitude of the writing current of the first writing circuit 62 . If the reference data is not the same as the data read from the phase change memory 63 , a control signal is transmitted to the first writing circuit 62 and the second writing circuit 66 to adjust the magnitude of the writing current.
- the second writing circuit 66 receives the control signal and re-writes the reference data to the phase change memory 63 by the adjusted current.
- the first writing circuit 62 writes to the Nth PCM cell.
- the first writing circuit 62 interrupts the writing procedure and re-writes the reference data to the PCM cell by the adjusted writing current.
- the first writing circuit 62 adjusts the magnitude of the writing current and executes a writing procedure to the (N+1)th PCM cell by the adjusted writing current.
- the first writing circuit 62 and the second writing circuit 64 further respectively comprise an auxiliary writing circuit to adjust the magnitude of the writing current from the first writing circuit 62 and the second writing circuit 64 based on the control signal.
- FIG. 7 is a circuit diagram of a writing circuit and the auxiliary writing circuit according to an embodiment of the invention.
- the writing circuit 72 outputs the writing current I based on the reference current I res output by a reference current source 71 .
- the auxiliary driving 73 utilizes the current mirror and the different W/L ratios of transistors T 1 , T 2 , T 3 , T 4 , T 5 and T 6 to output different auxiliary currents with different magnitudes.
- the auxiliary driving circuit 73 outputs the auxiliary current based on the control signal S 1 , S 2 and S 3 .
- the auxiliary currents output by the auxiliary driving circuit 73 can be output after addition.
- Those skilled in the art can modify the auxiliary driving circuit 73 to let the auxiliary currents output by the auxiliary driving circuit 73 to be output after subtraction.
- FIG. 8 is a schematic diagram of a writing system for the phase change memory according to another embodiment of the invention.
- the first writing circuit 82 receives and writes the data to the phase change memory 83 .
- the verifying unit 81 verifies whether the data stored in the phase change memory 83 is correct based on a reference data. In this embodiment, when the verifying unit 81 verifies the (N ⁇ 1)th PCM cell, the first writing circuit 82 writes the Nth PCM cell.
- the verifying unit 81 comprises a detection and comparison circuit 84 , a current adjustment circuit 85 and a second writing circuit 87 .
- the reading circuit 86 reads the phase change memory 83 by a reading current and transmits the read data to the detection and comparison circuit 84 .
- the detection and comparison circuit 84 compares the data from the reading 86 and a reference data. If the two data are matched, a verify signal is transmitted to the first writing 82 to maintain the magnitude of the writing current of the first writing circuit 82 . If the reference data is not the same as the data read from the phase change memory 83 , a control signal is transmitted to the first writing circuit 82 and the second writing circuit 87 to adjust the magnitude of the writing current.
- the Nth PCM cell still can be verified.
- the second writing circuit 87 receives the control signal and re-writes the reference data to the phase change memory 83 by the adjusted current.
- the first writing circuit 82 writes to the Nth PCM cell.
- the first writing circuit 82 interrupts the writing procedure and re-writes the reference data to the PCM cell by the adjusted writing current.
- the first writing circuit 82 adjusts the magnitude of the writing current and executes a writing procedure to the (N+1)th PCM cell by the adjusted writing current.
- the first writing circuit 82 and the second writing circuit 87 further respectively comprise an auxiliary writing circuit to adjust the magnitude of the writing current from the first writing circuit 82 and the second writing circuit 87 based on the control signal.
Landscapes
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (34)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/571,798 USRE45189E1 (en) | 2007-11-08 | 2012-08-10 | Writing system and method for phase change memory |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW096142224A TWI347607B (en) | 2007-11-08 | 2007-11-08 | Writing system and method for a phase change memory |
TW96142224A | 2007-11-08 | ||
US12/165,761 US7773410B2 (en) | 2007-11-08 | 2008-07-01 | Writing system and method for phase change memory |
US13/571,798 USRE45189E1 (en) | 2007-11-08 | 2012-08-10 | Writing system and method for phase change memory |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/165,761 Reissue US7773410B2 (en) | 2007-11-08 | 2008-07-01 | Writing system and method for phase change memory |
Publications (1)
Publication Number | Publication Date |
---|---|
USRE45189E1 true USRE45189E1 (en) | 2014-10-14 |
Family
ID=40623563
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/165,761 Ceased US7773410B2 (en) | 2007-11-08 | 2008-07-01 | Writing system and method for phase change memory |
US13/571,798 Active 2029-01-08 USRE45189E1 (en) | 2007-11-08 | 2012-08-10 | Writing system and method for phase change memory |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/165,761 Ceased US7773410B2 (en) | 2007-11-08 | 2008-07-01 | Writing system and method for phase change memory |
Country Status (2)
Country | Link |
---|---|
US (2) | US7773410B2 (en) |
TW (1) | TWI347607B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI615854B (en) * | 2016-12-09 | 2018-02-21 | Powerchip Technology Corporation | Memory apparatus |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007034542A1 (en) | 2005-09-21 | 2007-03-29 | Renesas Technology Corp. | Semiconductor device |
TWI347607B (en) | 2007-11-08 | 2011-08-21 | Ind Tech Res Inst | Writing system and method for a phase change memory |
US20090304775A1 (en) * | 2008-06-04 | 2009-12-10 | Joshi Ashok V | Drug-Exuding Orthopedic Implant |
TWI402845B (en) | 2008-12-30 | 2013-07-21 | Higgs Opl Capital Llc | Verification circuits and methods for phase change memory |
TWI412124B (en) | 2008-12-31 | 2013-10-11 | Higgs Opl Capital Llc | Phase change memory |
US8605531B2 (en) * | 2011-06-20 | 2013-12-10 | Intel Corporation | Fast verify for phase change memory with switch |
KR102079370B1 (en) | 2013-02-05 | 2020-02-20 | 삼성전자주식회사 | Nonvolatile memory device and writing method thereof |
US9471227B2 (en) | 2014-07-15 | 2016-10-18 | Western Digital Technologies, Inc. | Implementing enhanced performance with read before write to phase change memory to avoid write cancellations |
CN105023606B (en) * | 2015-08-14 | 2018-06-26 | 中国科学院上海微系统与信息技术研究所 | A kind of phase transition storage and its method for restoring data |
Citations (79)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4974205A (en) * | 1988-10-24 | 1990-11-27 | Fujitsu Limited | Josephson memory and read/write circuit |
US5694363A (en) | 1995-04-28 | 1997-12-02 | Sgs-Thomson Microelectronics S.R.L. | Reading circuit for memory cell devices having a low supply voltage |
US5787042A (en) | 1997-03-18 | 1998-07-28 | Micron Technology, Inc. | Method and apparatus for reading out a programmable resistor memory |
US5883837A (en) | 1996-09-30 | 1999-03-16 | Sgs-Thomson Microelectronics, S.R.L. | Reading circuit for semiconductor memory cells |
JP2002246561A (en) | 2001-02-19 | 2002-08-30 | Dainippon Printing Co Ltd | Storage cell, memory matrix using the same, and their manufacturing methods |
US6487113B1 (en) | 2001-06-29 | 2002-11-26 | Ovonyx, Inc. | Programming a phase-change memory with slow quench time |
CN1455412A (en) | 2002-04-30 | 2003-11-12 | 惠普公司 | Resistance crosspoint storage array with charge injection differential read-out amplifier |
JP2004274055A (en) | 2003-03-04 | 2004-09-30 | Samsung Electronics Co Ltd | Storage cell for memory element, as well as phase change type memory element and its forming method |
US20050068804A1 (en) | 2003-09-25 | 2005-03-31 | Samsung Electronics Co., Ltd. | Phase-change memory device and method that maintains the resistance of a phase-change material in a reset state within a constant resistance range |
JP2005525690A (en) | 2001-08-31 | 2005-08-25 | オヴォニクス インコーポレイテッド | Phase change memory with higher pore position |
JP2006510220A (en) | 2002-12-13 | 2006-03-23 | オヴォニクス,インコーポレイテッド | Memory and access device |
JP2006108645A (en) | 2004-10-08 | 2006-04-20 | Ind Technol Res Inst | Multilevel phase change memory, method of operating the same, and method of manufacturing the same |
US7054213B2 (en) | 2000-12-28 | 2006-05-30 | Stmicroelectronics, Inc. | Method and circuit for determining sense amplifier sensitivity |
US7110286B2 (en) * | 2004-02-04 | 2006-09-19 | Samsung Electronics Co., Ltd. | Phase-change memory device and method of writing a phase-change memory device |
US20060221678A1 (en) | 2005-03-30 | 2006-10-05 | Ferdinando Bedeschi | Circuit for reading memory cells |
JP2006295168A (en) | 2005-04-06 | 2006-10-26 | Samsung Electronics Co Ltd | Multivalued resistive memory element, and its manufacture and operating method therefor |
US7154774B2 (en) | 2005-03-30 | 2006-12-26 | Ovonyx, Inc. | Detecting switching of access elements of phase change memory cells |
US20070002654A1 (en) | 2005-06-30 | 2007-01-04 | Carlo Borromeo | Method and apparatus for sensing a state of a memory cell |
US7190607B2 (en) | 2004-06-19 | 2007-03-13 | Samsung Electronics Co., Ltd. | Phase-change memory element driver circuits using measurement to control current and methods of controlling drive current of phase-change memory elements using measurement |
JP2007103945A (en) | 2005-10-06 | 2007-04-19 | Samsung Electronics Co Ltd | Phase change memory devices using magnetic resistance effect, methods of operating and methods of fabricating same |
JP2007184591A (en) | 2006-01-02 | 2007-07-19 | Samsung Electronics Co Ltd | Phase change storage element including contact with multi-bit cell and diameter to be adjusted therein, its manufacturing method, and its program method |
US7259982B2 (en) | 2005-01-05 | 2007-08-21 | Intel Corporation | Reading phase change memories to reduce read disturbs |
US7324371B2 (en) | 2001-12-27 | 2008-01-29 | Stmicroelectronics S.R.L. | Method of writing to a phase change memory device |
CN101136452A (en) | 2006-08-31 | 2008-03-05 | 财团法人工业技术研究院 | Phase variation storage installation and its making method |
US7359231B2 (en) | 2004-06-30 | 2008-04-15 | Intel Corporation | Providing current for phase change memories |
CN101202326A (en) | 2006-12-14 | 2008-06-18 | 财团法人工业技术研究院 | Phase-change storage apparatus and method of manufacture |
TW200828506A (en) | 2006-12-29 | 2008-07-01 | Ind Tech Res Inst | Phase-change memory element and method for fabricating the same |
JP2008171541A (en) | 2007-01-12 | 2008-07-24 | Ind Technol Res Inst | Method and system for driving phase change memory |
JP2008193071A (en) | 2007-02-01 | 2008-08-21 | Ind Technol Res Inst | Phase change memory |
US7423897B2 (en) | 2004-10-01 | 2008-09-09 | Ovonyx, Inc. | Method of operating a programmable resistance memory array |
CN101266834A (en) | 2007-03-15 | 2008-09-17 | 财团法人工业技术研究院 | Writing drive method and system for phase change memory |
CN101271862A (en) | 2007-03-19 | 2008-09-24 | 财团法人工业技术研究院 | Memory element and manufacturing method thereof |
JP2008226427A (en) | 2007-03-08 | 2008-09-25 | Ind Technol Res Inst | Writing method and system for phase change memory |
CN101276643A (en) | 2007-03-28 | 2008-10-01 | 财团法人工业技术研究院 | Write-in method and system of phase variation memory |
US7447092B2 (en) | 2003-08-22 | 2008-11-04 | Samsung Electronics Co., Ltd. | Write driver circuit for controlling a write current applied to a phase change memory based on an ambient temperature |
TW200845443A (en) | 2007-05-14 | 2008-11-16 | Ind Tech Res Inst | Phase-change memory element |
US7457151B2 (en) * | 2005-07-13 | 2008-11-25 | Samsung Electronics Co., Ltd. | Phase change random access memory (PRAM) device having variable drive voltages |
CN101312230A (en) | 2007-05-25 | 2008-11-26 | 财团法人工业技术研究院 | Phase change storage apparatus and method of manufacture |
TW200849278A (en) | 2007-06-13 | 2008-12-16 | Ind Tech Res Inst | A writing circuit for a phase change memory |
CN101330126A (en) | 2007-06-19 | 2008-12-24 | 财团法人工业技术研究院 | Phase variation storage unit structure and method for manufacturing the same |
US20080316847A1 (en) | 2007-06-25 | 2008-12-25 | Industrial Technology Research Institute | Sensing circuit of a phase change memory and sensing method thereof |
CN101335045A (en) | 2007-06-27 | 2008-12-31 | 财团法人工业技术研究院 | Write circuit of phase-change memory |
TWI305042B (en) | 2006-08-16 | 2009-01-01 | Ind Tech Res Inst | Phase-change memory devices and methods for fabricating the same |
TW200908294A (en) | 2007-08-14 | 2009-02-16 | Ind Tech Res Inst | Phase-change memory |
CN101369450A (en) | 2007-08-17 | 2009-02-18 | 财团法人工业技术研究院 | Sensing circuit of phase-change memory |
CN101383397A (en) | 2007-09-04 | 2009-03-11 | 财团法人工业技术研究院 | Phase change memory device and fabrication method thereof |
TW200915318A (en) | 2007-09-21 | 2009-04-01 | Ind Tech Res Inst | Device controlling phase change storage element and method of increasing realibility of phase change storage elememt |
US7515460B2 (en) | 2005-01-25 | 2009-04-07 | Intel Corporation | Multilevel programming of phase change memory cells |
CN101414480A (en) | 2007-10-19 | 2009-04-22 | 财团法人工业技术研究院 | Control device for phase-change memory cell and method for adding phase-change memory cell reliability |
US20090122599A1 (en) | 2007-11-08 | 2009-05-14 | Industrial Technology Research Institute | Writing system and method for phase change momory |
US7535747B2 (en) | 2006-09-04 | 2009-05-19 | Samsung Electronics Co., Ltd. | Phase change random access memory and related methods of operation |
US7542356B2 (en) * | 2006-11-01 | 2009-06-02 | Samsung Electronics Co., Ltd. | Semiconductor memory device and method for reducing cell activation during write operations |
CN101452743A (en) | 2007-12-05 | 2009-06-10 | 财团法人工业技术研究院 | Writing-in system and method for phase change memory |
TW200926186A (en) | 2007-12-03 | 2009-06-16 | Ind Tech Res Inst | Memory and method for reducing power dissipation caused by current leakage |
CN101471130A (en) | 2007-12-25 | 2009-07-01 | 财团法人工业技术研究院 | Phase-change memory device and its control method |
US7566895B2 (en) | 2006-11-24 | 2009-07-28 | Industrial Technology Research Institute | Phase change memory device and method for fabricating the same |
US20090189142A1 (en) | 2008-01-25 | 2009-07-30 | Industrial Technology Research Institute | Phase-Change Memory |
CN101504863A (en) | 2008-02-05 | 2009-08-12 | 财团法人工业技术研究院 | Memory and method for suppressing energy consumption of memory leakage current |
CN101504968A (en) | 2008-01-25 | 2009-08-12 | 财团法人工业技术研究院 | Phase-change memory and its production method |
US7609544B2 (en) * | 2004-11-26 | 2009-10-27 | Renesas Technology Corp. | Programmable semiconductor memory device |
US20090296458A1 (en) | 2008-05-27 | 2009-12-03 | Samsung Electronics Co., Ltd. | Resistance variable memory device and method of writing data |
CN101599301A (en) | 2008-06-06 | 2009-12-09 | 财团法人工业技术研究院 | Storer and memory-writing method |
TW200951981A (en) | 2008-06-02 | 2009-12-16 | Ind Tech Res Inst | Memory and writing method thereof |
TW200952169A (en) | 2008-06-03 | 2009-12-16 | Ind Tech Res Inst | Phase-change memory devices and methods for fabricating the same |
US7639522B2 (en) | 2006-11-29 | 2009-12-29 | Samsung Electronics Co., Ltd. | Method of driving multi-level variable resistive memory device and multi-level variable resistive memory device |
US7646627B2 (en) * | 2006-05-18 | 2010-01-12 | Renesas Technology Corp. | Magnetic random access memory having improved read disturb suppression and thermal disturbance resistance |
CN101626060A (en) | 2008-07-11 | 2010-01-13 | 财团法人工业技术研究院 | Phase-change memory element |
US7670869B2 (en) | 2007-02-16 | 2010-03-02 | Industrial Technology Research Institute | Semiconductor device and fabrications thereof |
US20100117050A1 (en) | 2008-11-12 | 2010-05-13 | Industrial Technology Research Institute | Phase-change memory element |
US20100165723A1 (en) | 2008-12-31 | 2010-07-01 | Industrial Technology Research Institute | Phase change memory |
US20100165720A1 (en) | 2008-12-30 | 2010-07-01 | Industrial Technology Research Institute | Verification circuits and methods for phase change memory array |
US7773408B2 (en) * | 2005-11-30 | 2010-08-10 | Renesas Technology Corp. | Nonvolatile memory device |
US7773411B2 (en) | 2007-12-06 | 2010-08-10 | Industrial Technology Research Institute | Phase change memory and control method thereof |
CN101814323A (en) | 2009-02-23 | 2010-08-25 | 财团法人工业技术研究院 | Verification circuit and method of phase change memory array |
US7787281B2 (en) | 2007-07-05 | 2010-08-31 | Industrial Technology Research Institute | Writing circuit for a phase change memory |
CN101819816A (en) | 2009-02-27 | 2010-09-01 | 财团法人工业技术研究院 | Phase change memory |
TWI334604B (en) | 2007-06-25 | 2010-12-11 | Ind Tech Res Inst | Sensing circuits of phase change memory |
TWI336925B (en) | 2007-05-31 | 2011-02-01 | Ind Tech Res Inst | Phase-change memory cell structures and methods for fabricating the same |
TWI343642B (en) | 2007-04-24 | 2011-06-11 | Ind Tech Res Inst | Phase-change memory devices and methods for fabricating the same |
-
2007
- 2007-11-08 TW TW096142224A patent/TWI347607B/en not_active IP Right Cessation
-
2008
- 2008-07-01 US US12/165,761 patent/US7773410B2/en not_active Ceased
-
2012
- 2012-08-10 US US13/571,798 patent/USRE45189E1/en active Active
Patent Citations (119)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4974205A (en) * | 1988-10-24 | 1990-11-27 | Fujitsu Limited | Josephson memory and read/write circuit |
US5694363A (en) | 1995-04-28 | 1997-12-02 | Sgs-Thomson Microelectronics S.R.L. | Reading circuit for memory cell devices having a low supply voltage |
US5883837A (en) | 1996-09-30 | 1999-03-16 | Sgs-Thomson Microelectronics, S.R.L. | Reading circuit for semiconductor memory cells |
US5787042A (en) | 1997-03-18 | 1998-07-28 | Micron Technology, Inc. | Method and apparatus for reading out a programmable resistor memory |
US7054213B2 (en) | 2000-12-28 | 2006-05-30 | Stmicroelectronics, Inc. | Method and circuit for determining sense amplifier sensitivity |
JP2002246561A (en) | 2001-02-19 | 2002-08-30 | Dainippon Printing Co Ltd | Storage cell, memory matrix using the same, and their manufacturing methods |
US6487113B1 (en) | 2001-06-29 | 2002-11-26 | Ovonyx, Inc. | Programming a phase-change memory with slow quench time |
JP2005525690A (en) | 2001-08-31 | 2005-08-25 | オヴォニクス インコーポレイテッド | Phase change memory with higher pore position |
US7324371B2 (en) | 2001-12-27 | 2008-01-29 | Stmicroelectronics S.R.L. | Method of writing to a phase change memory device |
CN1455412A (en) | 2002-04-30 | 2003-11-12 | 惠普公司 | Resistance crosspoint storage array with charge injection differential read-out amplifier |
JP2006510220A (en) | 2002-12-13 | 2006-03-23 | オヴォニクス,インコーポレイテッド | Memory and access device |
JP2004274055A (en) | 2003-03-04 | 2004-09-30 | Samsung Electronics Co Ltd | Storage cell for memory element, as well as phase change type memory element and its forming method |
US7447092B2 (en) | 2003-08-22 | 2008-11-04 | Samsung Electronics Co., Ltd. | Write driver circuit for controlling a write current applied to a phase change memory based on an ambient temperature |
US20050068804A1 (en) | 2003-09-25 | 2005-03-31 | Samsung Electronics Co., Ltd. | Phase-change memory device and method that maintains the resistance of a phase-change material in a reset state within a constant resistance range |
US7110286B2 (en) * | 2004-02-04 | 2006-09-19 | Samsung Electronics Co., Ltd. | Phase-change memory device and method of writing a phase-change memory device |
US7190607B2 (en) | 2004-06-19 | 2007-03-13 | Samsung Electronics Co., Ltd. | Phase-change memory element driver circuits using measurement to control current and methods of controlling drive current of phase-change memory elements using measurement |
US7359231B2 (en) | 2004-06-30 | 2008-04-15 | Intel Corporation | Providing current for phase change memories |
US7423897B2 (en) | 2004-10-01 | 2008-09-09 | Ovonyx, Inc. | Method of operating a programmable resistance memory array |
JP2006108645A (en) | 2004-10-08 | 2006-04-20 | Ind Technol Res Inst | Multilevel phase change memory, method of operating the same, and method of manufacturing the same |
US7609544B2 (en) * | 2004-11-26 | 2009-10-27 | Renesas Technology Corp. | Programmable semiconductor memory device |
US7259982B2 (en) | 2005-01-05 | 2007-08-21 | Intel Corporation | Reading phase change memories to reduce read disturbs |
US7515460B2 (en) | 2005-01-25 | 2009-04-07 | Intel Corporation | Multilevel programming of phase change memory cells |
US7388775B2 (en) | 2005-03-30 | 2008-06-17 | Ovonyx, Inc. | Detecting switching of access elements of phase change memory cells |
US7154774B2 (en) | 2005-03-30 | 2006-12-26 | Ovonyx, Inc. | Detecting switching of access elements of phase change memory cells |
US20060221678A1 (en) | 2005-03-30 | 2006-10-05 | Ferdinando Bedeschi | Circuit for reading memory cells |
JP2006295168A (en) | 2005-04-06 | 2006-10-26 | Samsung Electronics Co Ltd | Multivalued resistive memory element, and its manufacture and operating method therefor |
US20070002654A1 (en) | 2005-06-30 | 2007-01-04 | Carlo Borromeo | Method and apparatus for sensing a state of a memory cell |
US7457151B2 (en) * | 2005-07-13 | 2008-11-25 | Samsung Electronics Co., Ltd. | Phase change random access memory (PRAM) device having variable drive voltages |
JP2007103945A (en) | 2005-10-06 | 2007-04-19 | Samsung Electronics Co Ltd | Phase change memory devices using magnetic resistance effect, methods of operating and methods of fabricating same |
US7773408B2 (en) * | 2005-11-30 | 2010-08-10 | Renesas Technology Corp. | Nonvolatile memory device |
JP2007184591A (en) | 2006-01-02 | 2007-07-19 | Samsung Electronics Co Ltd | Phase change storage element including contact with multi-bit cell and diameter to be adjusted therein, its manufacturing method, and its program method |
US7646627B2 (en) * | 2006-05-18 | 2010-01-12 | Renesas Technology Corp. | Magnetic random access memory having improved read disturb suppression and thermal disturbance resistance |
US7745811B2 (en) | 2006-08-16 | 2010-06-29 | Industrial Technology Research Institute | Phase change memory devices and methods for fabricating the same |
TWI305042B (en) | 2006-08-16 | 2009-01-01 | Ind Tech Res Inst | Phase-change memory devices and methods for fabricating the same |
CN101136452A (en) | 2006-08-31 | 2008-03-05 | 财团法人工业技术研究院 | Phase variation storage installation and its making method |
US7535747B2 (en) | 2006-09-04 | 2009-05-19 | Samsung Electronics Co., Ltd. | Phase change random access memory and related methods of operation |
US7542356B2 (en) * | 2006-11-01 | 2009-06-02 | Samsung Electronics Co., Ltd. | Semiconductor memory device and method for reducing cell activation during write operations |
US7566895B2 (en) | 2006-11-24 | 2009-07-28 | Industrial Technology Research Institute | Phase change memory device and method for fabricating the same |
TWI318470B (en) | 2006-11-24 | 2009-12-11 | Ind Tech Res Inst | Phase change memory device and method of fabricating the same |
US7639522B2 (en) | 2006-11-29 | 2009-12-29 | Samsung Electronics Co., Ltd. | Method of driving multi-level variable resistive memory device and multi-level variable resistive memory device |
CN101202326A (en) | 2006-12-14 | 2008-06-18 | 财团法人工业技术研究院 | Phase-change storage apparatus and method of manufacture |
CN101211959A (en) | 2006-12-29 | 2008-07-02 | 财团法人工业技术研究院 | Phase-change memory and fabrication method thereof |
TW200828506A (en) | 2006-12-29 | 2008-07-01 | Ind Tech Res Inst | Phase-change memory element and method for fabricating the same |
US7521372B2 (en) | 2006-12-29 | 2009-04-21 | Industrial Technology Research Institute | Method of fabrication of phase-change memory |
JP2008171541A (en) | 2007-01-12 | 2008-07-24 | Ind Technol Res Inst | Method and system for driving phase change memory |
TWI320180B (en) | 2007-01-12 | 2010-02-01 | A driving method and a driving system for writing the phase change memory | |
US7643373B2 (en) | 2007-01-12 | 2010-01-05 | Shyh-Shyuan Sheu | Driving method and system for a phase change memory |
TWI326917B (en) | 2007-02-01 | 2010-07-01 | Ind Tech Res Inst | Phase-change memory |
JP2008193071A (en) | 2007-02-01 | 2008-08-21 | Ind Technol Res Inst | Phase change memory |
US7670869B2 (en) | 2007-02-16 | 2010-03-02 | Industrial Technology Research Institute | Semiconductor device and fabrications thereof |
TWI324823B (en) | 2007-02-16 | 2010-05-11 | Ind Tech Res Inst | Memory device and fabrications thereof |
US7773409B2 (en) | 2007-03-08 | 2010-08-10 | Industrial Technology Research Institute | Writing method and system for a phase change memory |
JP2008226427A (en) | 2007-03-08 | 2008-09-25 | Ind Technol Res Inst | Writing method and system for phase change memory |
TWI330846B (en) | 2007-03-08 | 2010-09-21 | Ind Tech Res Inst | A writing method and system for a phase change memory |
CN101266834A (en) | 2007-03-15 | 2008-09-17 | 财团法人工业技术研究院 | Writing drive method and system for phase change memory |
CN101271862A (en) | 2007-03-19 | 2008-09-24 | 财团法人工业技术研究院 | Memory element and manufacturing method thereof |
CN101276643A (en) | 2007-03-28 | 2008-10-01 | 财团法人工业技术研究院 | Write-in method and system of phase variation memory |
US7964862B2 (en) | 2007-04-24 | 2011-06-21 | Industrial Technology Research Institute | Phase change memory devices and methods for manufacturing the same |
TWI343642B (en) | 2007-04-24 | 2011-06-11 | Ind Tech Res Inst | Phase-change memory devices and methods for fabricating the same |
US7679163B2 (en) | 2007-05-14 | 2010-03-16 | Industrial Technology Research Institute | Phase-change memory element |
JP2008283163A (en) | 2007-05-14 | 2008-11-20 | Ind Technol Res Inst | Phase change memory element |
CN101308903A (en) | 2007-05-14 | 2008-11-19 | 财团法人工业技术研究院 | Phase-change memory element |
TW200845443A (en) | 2007-05-14 | 2008-11-16 | Ind Tech Res Inst | Phase-change memory element |
CN101312230A (en) | 2007-05-25 | 2008-11-26 | 财团法人工业技术研究院 | Phase change storage apparatus and method of manufacture |
US7923714B2 (en) | 2007-05-31 | 2011-04-12 | Industrial Technology Research Institute | Phase change memory cell structures and methods for manufacturing the same |
TWI336925B (en) | 2007-05-31 | 2011-02-01 | Ind Tech Res Inst | Phase-change memory cell structures and methods for fabricating the same |
TW200849278A (en) | 2007-06-13 | 2008-12-16 | Ind Tech Res Inst | A writing circuit for a phase change memory |
US7672176B2 (en) | 2007-06-13 | 2010-03-02 | Industrial Technology Research Institute | Writing circuit for a phase change memory |
CN101330126A (en) | 2007-06-19 | 2008-12-24 | 财团法人工业技术研究院 | Phase variation storage unit structure and method for manufacturing the same |
US7796454B2 (en) | 2007-06-25 | 2010-09-14 | Industrial Technology Research Institute | Sensing circuit of a phase change memory and sensing method thereof |
TW200901196A (en) | 2007-06-25 | 2009-01-01 | Ind Tech Res Inst | Sensing circuits and methods of phase change memory |
US7933147B2 (en) | 2007-06-25 | 2011-04-26 | Industrial Technology Research Institute | Sensing circuit of a phase change memory and sensing method thereof |
TWI334604B (en) | 2007-06-25 | 2010-12-11 | Ind Tech Res Inst | Sensing circuits of phase change memory |
US20080316847A1 (en) | 2007-06-25 | 2008-12-25 | Industrial Technology Research Institute | Sensing circuit of a phase change memory and sensing method thereof |
CN101335045A (en) | 2007-06-27 | 2008-12-31 | 财团法人工业技术研究院 | Write circuit of phase-change memory |
US7787281B2 (en) | 2007-07-05 | 2010-08-31 | Industrial Technology Research Institute | Writing circuit for a phase change memory |
TWI342022B (en) | 2007-07-05 | 2011-05-11 | Ind Tech Res Inst | A writing circuit for a phase change memory |
TW200908294A (en) | 2007-08-14 | 2009-02-16 | Ind Tech Res Inst | Phase-change memory |
CN101369450A (en) | 2007-08-17 | 2009-02-18 | 财团法人工业技术研究院 | Sensing circuit of phase-change memory |
CN101383397A (en) | 2007-09-04 | 2009-03-11 | 财团法人工业技术研究院 | Phase change memory device and fabrication method thereof |
TW200913252A (en) | 2007-09-04 | 2009-03-16 | Ind Tech Res Inst | Phase change memory device and fabrications thereof |
US7678606B2 (en) | 2007-09-04 | 2010-03-16 | Industrial Technology Research Institute | Phase change memory device and fabrication method thereof |
US7796455B2 (en) | 2007-09-21 | 2010-09-14 | Industrial Technology Research Institute | Device controlling phase change storage element and method thereof |
TW200915318A (en) | 2007-09-21 | 2009-04-01 | Ind Tech Res Inst | Device controlling phase change storage element and method of increasing realibility of phase change storage elememt |
CN101414480A (en) | 2007-10-19 | 2009-04-22 | 财团法人工业技术研究院 | Control device for phase-change memory cell and method for adding phase-change memory cell reliability |
TW200921682A (en) | 2007-11-08 | 2009-05-16 | Ind Tech Res Inst | Writing system and method for a phase change memory |
US20090122599A1 (en) | 2007-11-08 | 2009-05-14 | Industrial Technology Research Institute | Writing system and method for phase change momory |
US7773410B2 (en) | 2007-11-08 | 2010-08-10 | Industrial Technology Research Institute | Writing system and method for phase change memory |
US7885109B2 (en) | 2007-12-03 | 2011-02-08 | Industrial Technology Research Institute | Memory and method for dissipation caused by current leakage |
TW200926186A (en) | 2007-12-03 | 2009-06-16 | Ind Tech Res Inst | Memory and method for reducing power dissipation caused by current leakage |
CN101452743A (en) | 2007-12-05 | 2009-06-10 | 财团法人工业技术研究院 | Writing-in system and method for phase change memory |
TWI328816B (en) | 2007-12-06 | 2010-08-11 | Ind Tech Res Inst | Phase change memory and method of controlling phase change memory |
US7773411B2 (en) | 2007-12-06 | 2010-08-10 | Industrial Technology Research Institute | Phase change memory and control method thereof |
CN101471130A (en) | 2007-12-25 | 2009-07-01 | 财团法人工业技术研究院 | Phase-change memory device and its control method |
US20090189142A1 (en) | 2008-01-25 | 2009-07-30 | Industrial Technology Research Institute | Phase-Change Memory |
CN101504968A (en) | 2008-01-25 | 2009-08-12 | 财团法人工业技术研究院 | Phase-change memory and its production method |
TW200937693A (en) | 2008-01-25 | 2009-09-01 | Ind Tech Res Inst | Phase-change memory and method for fabricating the same |
CN101504863A (en) | 2008-02-05 | 2009-08-12 | 财团法人工业技术研究院 | Memory and method for suppressing energy consumption of memory leakage current |
US20090296458A1 (en) | 2008-05-27 | 2009-12-03 | Samsung Electronics Co., Ltd. | Resistance variable memory device and method of writing data |
US7889547B2 (en) | 2008-06-02 | 2011-02-15 | Industrial Technology Research Institute | Memory and writing method thereof |
TW200951981A (en) | 2008-06-02 | 2009-12-16 | Ind Tech Res Inst | Memory and writing method thereof |
TW200952169A (en) | 2008-06-03 | 2009-12-16 | Ind Tech Res Inst | Phase-change memory devices and methods for fabricating the same |
US7858961B2 (en) | 2008-06-03 | 2010-12-28 | Industrial Technology Research Institute | Phase change memory devices and methods for fabricating the same |
CN101599301A (en) | 2008-06-06 | 2009-12-09 | 财团法人工业技术研究院 | Storer and memory-writing method |
US7919768B2 (en) | 2008-07-11 | 2011-04-05 | Industrial Technology Research Institute | Phase-change memory element |
CN101626060A (en) | 2008-07-11 | 2010-01-13 | 财团法人工业技术研究院 | Phase-change memory element |
TW201003851A (en) | 2008-07-11 | 2010-01-16 | Ind Tech Res Inst | Phase change memory and method for fabricating the same |
TW201019467A (en) | 2008-11-12 | 2010-05-16 | Ind Tech Res Inst | Phase-change memory element and method for fabricating the same |
US20100117050A1 (en) | 2008-11-12 | 2010-05-13 | Industrial Technology Research Institute | Phase-change memory element |
CN101740716A (en) | 2008-11-12 | 2010-06-16 | 财团法人工业技术研究院 | Phase-change memory element and its forming method |
US20100165720A1 (en) | 2008-12-30 | 2010-07-01 | Industrial Technology Research Institute | Verification circuits and methods for phase change memory array |
TW201025326A (en) | 2008-12-30 | 2010-07-01 | Ind Tech Res Inst | Verification circuits and methods for phase change memory |
US7974122B2 (en) | 2008-12-30 | 2011-07-05 | Industrial Technology Research Institute | Verification circuits and methods for phase change memory array |
US20100165723A1 (en) | 2008-12-31 | 2010-07-01 | Industrial Technology Research Institute | Phase change memory |
TW201025573A (en) | 2008-12-31 | 2010-07-01 | Ind Tech Res Inst | Phase change memory |
US8199561B2 (en) | 2008-12-31 | 2012-06-12 | Higgs Opl. Capital Llc | Phase change memory |
US20120230099A1 (en) | 2008-12-31 | 2012-09-13 | Higgs Opl. Capitol LLC | Phase change memory |
CN101814323A (en) | 2009-02-23 | 2010-08-25 | 财团法人工业技术研究院 | Verification circuit and method of phase change memory array |
CN101819816A (en) | 2009-02-27 | 2010-09-01 | 财团法人工业技术研究院 | Phase change memory |
Non-Patent Citations (2)
Title |
---|
J.H. Yi et al., "Novel Cell Structure of PRAM With Thin Metal Layer Inserted GeSbTe", IEEE, IEDM '03 Technical Digest, 2003, p. 901-904. |
Stolowitz Ford Cowger LLP, "Listing of Related Cases", Apr. 24, 2013, 1 page. |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI615854B (en) * | 2016-12-09 | 2018-02-21 | Powerchip Technology Corporation | Memory apparatus |
Also Published As
Publication number | Publication date |
---|---|
US20090122599A1 (en) | 2009-05-14 |
TWI347607B (en) | 2011-08-21 |
US7773410B2 (en) | 2010-08-10 |
TW200921682A (en) | 2009-05-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
USRE45189E1 (en) | Writing system and method for phase change memory | |
CN109671464B (en) | Memory module, method of operating the same, and test system for memory module | |
JP4718134B2 (en) | Write driver circuit and write current application method in phase change memory device | |
US8040723B2 (en) | Voltage compensation circuit, multi-level memory device with the same, and voltage compensation method for reading the multi-level memory device | |
US7643373B2 (en) | Driving method and system for a phase change memory | |
US8644061B2 (en) | Variable resistance memory device performing program and verification operation | |
US10297295B2 (en) | Semiconductor memory device | |
US7428170B2 (en) | Voltage generation circuit, flash memory device including the same and method for programming the flash memory device | |
US20120155194A1 (en) | Wordline voltage control within a memory | |
US7760583B2 (en) | Apparatus for controlling column selecting signal for semiconductor memory apparatus and method of controlling the same | |
KR20120012709A (en) | Memory device, precharge controlling method thereof, and devices having the same | |
US20110199851A1 (en) | Memory controller, semiconductor storage device, and memory system including the memory controller and the semiconductor storage device | |
TW200839782A (en) | A compensation circuit and a memory with the compensation circuit | |
US20030112664A1 (en) | Semiconductor storage device and information apparatus | |
CN101452743B (en) | Writing-in system and method for phase change memory | |
US7764548B2 (en) | Semiconductor memory device which delays refreshment signal for performing self-refreshment | |
US8599593B2 (en) | Memory system and method of operating the same | |
US20180150248A1 (en) | Memory device, semiconductor system including the same, and method for driving the semiconductor system | |
US9619319B2 (en) | Semiconductor device and error correction information writing method | |
US7978547B2 (en) | Data I/O control signal generating circuit in a semiconductor memory apparatus | |
JP2000195285A (en) | Semiconductor memory, control method for output signal in semiconductor device, and output signal control circuit | |
US20220336014A1 (en) | Phase-change memory device for improving resistance drift and dynamic resistance drift compensation method of the same | |
US8248842B2 (en) | Memory cell array biasing method and a semiconductor memory device | |
KR20040023187A (en) | Circuit for generating signal of pulsed sense enable | |
JPH1153899A (en) | Flash memory and method for deciding its operation |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: HIGGS OPL. CAPITAL LLC, DELAWARE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE;REEL/FRAME:029425/0209 Effective date: 20111122 |
|
AS | Assignment |
Owner name: GULA CONSULTING LIMITED LIABILITY COMPANY, DELAWAR Free format text: MERGER;ASSIGNOR:HIGGS OPL. CAPITAL LLC;REEL/FRAME:037360/0803 Effective date: 20150826 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552) Year of fee payment: 8 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |