CN108597558B - System and method for optimizing write operation current of phase change memory - Google Patents
System and method for optimizing write operation current of phase change memory Download PDFInfo
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- CN108597558B CN108597558B CN201810368154.4A CN201810368154A CN108597558B CN 108597558 B CN108597558 B CN 108597558B CN 201810368154 A CN201810368154 A CN 201810368154A CN 108597558 B CN108597558 B CN 108597558B
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Abstract
The invention provides a system and a method for optimizing write operation current of a phase change memory, wherein the method comprises the following steps: adjusting the write operation current based on the write operation current change step length to enable the write operation current to be sequentially increased from the minimum write operation current to the maximum write operation current; after the write operation current is obtained each time, performing write operation on the unit to be operated and performing electrical test on the unit to be operated to obtain resistance data and a V-I characteristic curve corresponding to the write operation current; before each write operation, erasing operation is carried out on the unit to be operated based on the same preset erasing parameters; carrying out statistical analysis on resistance data corresponding to different write operation currents, and screening true write operation currents which enable the unit to be operated to successfully carry out write operation; fitting a V-I characteristic curve corresponding to the true write operation current to obtain a plurality of sub-threshold slopes; and carrying out statistical analysis on the obtained sub-threshold slopes to obtain the optimal write operation current. The invention solves the problem that the optimal write operation current cannot be screened out by the existing method.
Description
Technical Field
The present invention relates to the field of integrated circuit testing, and more particularly, to a system and method for optimizing write operation current of a phase change memory.
Background
The phase change memory is a novel nonvolatile memory and has the characteristics of high read-write speed, compatibility with a CMOS (complementary metal oxide semiconductor) process, high density and the like. The core of the phase change memory is a chalcogenide-based phase change material, which presents different resistance values in an amorphous state and a crystalline state and has larger resistance difference, wherein the resistance value difference of a unit device can reach 2-3 orders of magnitude. The basic working principle of the phase change memory is that different pulses are applied to two ends of a phase change device unit, so that the phase change material is converted between an amorphous state and a crystalline state to realize writing and erasing operations, and meanwhile, the resistance value of the phase change material is measured through the ohm law principle to realize reading operation.
The phase change memory belongs to a current operation type device, and for the phase change memory: the switching of the cell data '0' and '1' and the sensing of the cell data are achieved by the corresponding operating currents. The write operation (RESET) of the phase change memory, i.e., the write '0' operation, is to operate the phase change cell to a high resistance state (RESET state). The writing operation is to apply writing current to the phase-change material, convert electric energy into heat energy through a heating electrode, raise the temperature of the phase-change material above the melting temperature, and finally cause the long-range order of the crystalline state of the phase-change material to be damaged through the rapid quenching process, so that the phase-change material is converted from the crystalline state to the amorphous state. The write operation causes the phase change cell to be finally in the high resistance region, and the storage of '0' is realized. An erase operation (SET), i.e., a write '1' operation, is to operate the phase change cell to a low resistance state (SET state). The erasing operation is to apply an electric pulse with proper amplitude and long time to the phase-change material, so that the temperature of the phase-change material is raised to be between the crystallization temperature and the melting temperature, and the width of the electric pulse is maintained to be larger than the crystallization induction time, thereby ensuring that the phase-change material is fully crystallized in enough time. It can be seen that the operating current is an important parameter of the phase change memory, and has a significant influence on the overall performance of the chip. The write operation current is relatively large, and the proper value of the write operation current is selected, so that the write operation of the chip can be realized, the yield of the chip is ensured, redundant current consumption is avoided, and the power consumption of the chip is reduced.
The conventional method for determining the write operation current is determined according to the resistance value of a cell after the write operation from a macroscopic view. The specific method comprises the following steps: selecting a RESET current, testing the resistance distribution of a chip after write operation is carried out, and finally determining the value of the write operation current; when the resistance distribution is consistent, the phase change resistor is in a high-resistance area, and the tail area does not appear in the resistance distribution, so that the current can be considered to be capable of performing writing operation. Therefore, the traditional method can only distinguish from resistance distribution, but the precision of the resistance distribution is low; and for the conditions that the resistance distribution is the same and the RESET current is different, the traditional method is difficult to apply and cannot obtain the optimal write operation current, so that the write operation current screened by the traditional method has the over-operation condition on the phase change unit, the fatigue reliability and the data retention of the phase change memory are reduced, and the traditional method cannot meet the requirements under the environment that the power consumption and the chip working parameters need to be accurately controlled.
Therefore, it is desirable to provide a new system and method for optimizing the write operation current of a phase change memory to solve the above-mentioned problems.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a system and a method for optimizing a write operation current of a phase change memory, which are used to solve the problems of the prior art, such as excessive operation, high power consumption, etc. due to the fact that the accuracy is not enough and the optimal write operation current cannot be screened out.
To achieve the above and other related objects, the present invention provides a method of optimizing a write operation current of a phase change memory, the method comprising:
setting the minimum write operation current, the maximum write operation current and the write operation current change step length of the phase change memory, and selecting a plurality of units to be operated from the phase change memory;
adjusting the write operation current based on the write operation current change step length to enable the write operation current to be sequentially increased from the minimum write operation current to the maximum write operation current; after the write operation current is obtained each time, performing write operation on the unit to be operated based on the write operation current, and after the write operation is finished, performing electrical test on the unit to be operated to obtain resistance data and a V-I characteristic curve corresponding to the write operation current; before writing operation is carried out on the unit to be operated each time, erasing operation is carried out on the unit to be operated based on the same preset erasing parameters;
carrying out statistical analysis on resistance data corresponding to different write operation currents, and screening true write operation currents which enable the unit to be operated to successfully carry out write operation; fitting a V-I characteristic curve corresponding to the true write operation current to obtain a sub-threshold slope corresponding to the true write operation current; and
and carrying out statistical analysis on the obtained subthreshold slope to obtain the optimal write operation current of the phase change memory.
Optionally, the minimum write operation current and the maximum write operation current are set according to the minimum initial write operation current and the maximum initial write operation current of the phase change memory, where the minimum write operation current is smaller than the minimum initial write operation current, and the maximum write operation current is larger than the maximum initial write operation current.
Optionally, the method for acquiring the V-I characteristic curve includes: setting a scanning voltage, and carrying out V-I scanning test on the unit to be operated based on the scanning voltage to obtain a V-I characteristic curve; wherein the scan voltage is less than a threshold voltage of the phase change memory for phase change.
Optionally, the method for screening the true write operation current includes: and counting resistance data corresponding to different write operation currents, and screening each resistance data based on a reference resistance to take the write operation current corresponding to the resistance data larger than the reference resistance as the true write operation current.
Optionally, the method for obtaining the sub-threshold slope includes: and carrying out log taking on the current value in the V-I characteristic curve so as to obtain a subthreshold slope corresponding to the true write operation current.
Optionally, the method for obtaining the optimal write operation current of the phase change memory comprises: and carrying out statistical analysis on the sub-threshold slope, and screening out the true write operation current corresponding to the sub-threshold slope when the change of the sub-threshold slope is close to saturation so as to be used as the optimal write operation current of the phase change memory.
The present invention also provides a system for optimizing a write operation current of a phase change memory, the system comprising: the device comprises a main control module, a parameter setting module, a switching module, a signal acquisition module, a parameter measurement module and a data processing module, wherein the main control module is connected with the parameter setting module, the switching module and the data processing module; wherein the content of the first and second substances,
the main control module is used for controlling the switching module so as to realize that the signal acquisition module is connected with the parameter setting module or the signal acquisition module is connected with the parameter measurement module; when the signal acquisition module is connected with the parameter setting module, the signal acquisition module is used for controlling the parameter setting module to sequentially generate an address signal, an erasing operation current and a writing operation current, wherein the writing operation current generated each time is sequentially increased from the minimum writing operation current to the maximum writing operation current by taking the writing operation current change step as a variable quantity; when the signal acquisition module is connected with the parameter measurement module, the signal acquisition module is used for transmitting the resistance data and the V-I characteristic curve acquired by the parameter measurement module to the data processing module;
the parameter setting module is used for sequentially generating an address signal, an erasing operation current and a writing operation current under the control of the main control module and transmitting the address signal, the erasing operation current and the writing operation current to the signal acquisition module, wherein the writing operation current output each time is sequentially increased from the minimum writing operation current to the maximum writing operation current by taking the writing operation current change step as a variable quantity;
the switching module is used for realizing the connection between the signal acquisition module and the parameter setting module or between the signal acquisition module and the parameter measurement module under the control of the main control module;
the signal acquisition module is used for selecting a plurality of units to be operated from the phase change memory according to the address signal, the erasing operation current and the writing operation current which are sequentially output by the parameter setting module, and sequentially performing erasing operation and writing operation on the units to be operated;
the parameter measuring module performs electrical test on the phase change memory through the signal acquisition module, acquires resistance data and a V-I characteristic curve corresponding to each write operation current, and transmits the resistance data and the V-I characteristic curve to the data processing module through the main control module; and
the data processing module is used for carrying out statistical analysis on resistance data corresponding to each write operation current and screening true write operation currents which enable the unit to be operated to successfully carry out write operation; fitting a V-I characteristic curve corresponding to each true write operation current to obtain a sub-threshold slope corresponding to each true write operation current; and carrying out statistical analysis on the obtained subthreshold slope to obtain the optimal write operation current of the phase change memory.
Optionally, the parameter setting module includes an address selection unit and a pulse signal generation unit respectively connected between the main control module and the switching module; wherein the content of the first and second substances,
the address selection unit is used for outputting an address signal to the signal acquisition module under the control of the main control module; and
the pulse signal generating unit is used for sequentially outputting erasing operation current and writing operation current to the signal acquisition module under the control of the main control module, wherein the writing operation current output each time is sequentially increased from the minimum writing operation current to the maximum writing operation current by taking the writing operation current change step as a variable quantity.
As described above, the system and method for writing operation current of the phase change memory according to the present invention have the following advantages:
by the system and the method, the write operation current of the phase change memory can be optimized, and the precision of write operation current screening is greatly improved; the effect of write operation is ensured while unnecessary power consumption of the RESET operation is reduced; the influence of over-operation on the fatigue reliability of the phase change memory can be avoided, the high-temperature durability and the reading durability of the phase change memory are ensured, and the service life of the phase change memory is prolonged.
The method provided by the invention starts from a microscopic angle, has the advantages of simplicity and convenience in operation, high screening precision, low testing cost, no damage to the chip and the like, and can be used for accurately determining the most suitable write operation current parameter of mass production chips and improving the performance of the chips.
Drawings
FIG. 1 shows a schematic flow diagram of the process of the present invention.
Fig. 2 shows a block diagram of the system according to the invention.
FIG. 3 is a graph showing sub-threshold slope distributions for different true write currents when the phase change memory is optimized for write currents by the method of the present invention.
FIG. 4 is a diagram illustrating resistance data distributions corresponding to different true write currents when write current optimization is performed on a phase change memory by the method of the present invention.
Description of the element reference numerals
100 main control module
200 parameter setting module
201 address selection unit
202 pulse signal generating unit
300 switching module
400 signal acquisition module
500 parameter measuring module
600 data processing module
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 4. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, the present embodiment provides a method for optimizing a write operation current of a phase change memory, the method comprising:
the method comprises the following steps: setting the minimum write operation current, the maximum write operation current and the write operation current change step length of the phase change memory, and selecting a plurality of units to be operated from the phase change memory;
step two: adjusting the write operation current based on the write operation current change step length to enable the write operation current to be sequentially increased from the minimum write operation current to the maximum write operation current; after the write operation current is obtained each time, performing write operation on the unit to be operated based on the write operation current, and after the write operation is finished, performing electrical test on the unit to be operated to obtain resistance data and a V-I characteristic curve corresponding to the write operation current; before writing operation is carried out on the unit to be operated each time, erasing operation is carried out on the unit to be operated based on the same preset erasing parameters;
step three: carrying out statistical analysis on resistance data corresponding to different write operation currents, and screening true write operation currents which enable the unit to be operated to successfully carry out write operation; fitting a V-I characteristic curve corresponding to the true write operation current to obtain a sub-threshold slope corresponding to the true write operation current; and
step four: and carrying out statistical analysis on the obtained subthreshold slope to obtain the optimal write operation current of the phase change memory.
As an example, in step one, according to the minimum initial write operation current I of the phase change memoryiniminAnd maximum initial write operation current IinimaxSetting the minimum write operation current IminAnd a maximum write operation current ImaxWherein the minimum write operation current IminLess than the minimum initial write operation current IiniminThe maximum write operation current ImaxGreater than the maximum initial write operation current Iinimax. It is noted that the minimum initial write current I is described hereininiminAnd maximum initial write operation current IinimaxThe minimum factory write operation current and the maximum factory write operation current are specified when the phase change memory is factory; the minimum write operation current IminAnd the maximum write operation current ImaxMust be set to ensure that the phase change memory can function properly within a given current range.
As an example, in step one, the write operation current varies by a step size IsetpRelated to the optimized precision of the write operation current, wherein the write operation current changes by step size IsetpThe smaller the write operation current is, the higher the optimization precision of the write operation current is, and the write operation current changes by a step length IsetpThe larger the write operation current, the lower the optimization accuracy of the write operation current; therefore, in the present embodiment, in order to ensure the optimum accuracy of the write operation current, the write operation current varies by a step size IsetpShould be set as small as possible.
As an example, in step two, the method for acquiring the V-I characteristic curve includes: setting a scanning voltage, and carrying out V-I scanning test on the unit to be operated based on the scanning voltage to obtain a V-I characteristic curve; wherein the scan voltage is less than a threshold voltage of the phase change memory for phase change.
As an example, in the second step, before performing the write operation on the unit to be operated each time, the erasing operation on the unit to be operated based on the same preset erasing parameter is further included, so that before performing the write operation on the unit to be operated each time, the states of the phase change materials of the unit to be operated are the same, so as to ensure the accuracy of the subsequent measurement. It should be noted that the preset erasing parameters include the width of the erasing operation current pulse and the height of the erasing operation current pulse, that is, the erasing operation current can be determined by determining the preset erasing parameters.
As an example, in step three, the method of screening the true write operation current includes: to pairAnd counting resistance data corresponding to different write operation currents, and screening each resistance data based on a reference resistance to take the write operation current corresponding to the resistance data larger than the reference resistance as the true write operation current. It is noted that the reference resistance is the resistance of the phase change memory in the high resistance state, and is typically 106The above.
As an example, in step three, the method for obtaining the sub-threshold slope includes: and carrying out log operation on the current value in the V-I characteristic curve, and taking the obtained V-log (I) characteristic curve as a subthreshold slope corresponding to the true write operation current.
As an example, in step four, the method for obtaining the optimal write operation current of the phase change memory comprises: and carrying out statistical analysis on the sub-threshold slope, and screening out the true write operation current corresponding to the sub-threshold slope when the change of the sub-threshold slope is close to saturation so as to be used as the optimal write operation current of the phase change memory.
It should be noted that, in the method of this embodiment, from the perspective of the microstructure of the phase change memory unit, the microscopic phenomenon of the phase change material under the write operation is characterized by using the relationship between the carrier transport mechanism and the macroscopic electrical property, so as to screen out the optimal write operation current of the phase change memory. The specific principle is as follows: under the action of write operation currents with different amplitudes, the internal defect densities of amorphous materials of the phase change memory cells are different, so that currents generated by electronic transition under the action of a certain electric field are different, and macroscopic voltage and current (V-I) characteristics are different; and measuring the amorphous V-I characteristic curve of the phase change memory unit after the write operation, fitting the V-I characteristic curve, and performing statistical analysis on the obtained sub-threshold slope STS to obtain the optimal write operation current of the phase change memory.
As shown in fig. 2, the present embodiment further provides a system for optimizing a write operation current of a phase change memory, the system comprising: the system comprises a main control module 100, a parameter setting module 200, a switching module 300, a signal acquisition module 400, a parameter measurement module 500 and a data processing module 600, wherein the main control module 100 is connected with the parameter setting module 200, the switching module 300 and the data processing module 600, the parameter setting module 200 is connected with the switching module 300, the switching module 300 is connected with the signal acquisition module 400 and the parameter measurement module 500, and the parameter measurement module 500 is connected with the main control module 100; wherein the content of the first and second substances,
the main control module 100 is configured to control the switching module 300, so as to enable the signal acquisition module 400 to be connected with the parameter setting module 200 or the signal acquisition module 400 to be connected with the parameter measurement module 500; when the signal acquisition module 400 is connected to the parameter setting module 200, the signal acquisition module is configured to control the parameter setting module 200 to sequentially generate an address signal, an erase operation current, and a write operation current, where the write operation current generated each time is sequentially increased from the minimum write operation current to the maximum write operation current by using the write operation current change step as a variation; when the signal acquisition module 400 is connected to the parameter measurement module 500, the signal acquisition module is configured to transmit the resistance data and the V-I characteristic curve acquired by the parameter measurement module 500 to the data processing module 600;
the parameter setting module 200 is configured to sequentially generate an address signal, an erase operation current, and a write operation current under the control of the main control module 100, and transmit the address signal, the erase operation current, and the write operation current to the signal acquisition module 400, where the write operation current output each time is sequentially increased from the minimum write operation current to the maximum write operation current by using the write operation current change step as a variation;
the switching module 300 is configured to, under the control of the main control module 100, enable the signal acquisition module 400 to be connected to the parameter setting module 200 or the signal acquisition module 400 to be connected to the parameter measurement module 500;
the signal acquisition module 400 is configured to select a plurality of units to be operated from the phase change memory according to the address signal, the erase operation current, and the write operation current sequentially output by the parameter setting module 200, and sequentially perform erase operation and write operation on the units to be operated;
the parameter measuring module 500 performs an electrical test on the phase change memory through the signal collecting module 400, obtains resistance data and a V-I characteristic curve corresponding to each write operation current, and transmits the resistance data and the V-I characteristic curve to the data processing module 600 through the main control module 100; and
the data processing module 600 is configured to perform statistical analysis on resistance data corresponding to each write operation current, and screen a true write operation current for enabling the unit to be operated to successfully perform write operation; fitting a V-I characteristic curve corresponding to each true write operation current to obtain a sub-threshold slope corresponding to each true write operation current; and carrying out statistical analysis on the obtained subthreshold slope to obtain the optimal write operation current of the phase change memory.
As an example, the master control module 100 includes a computer; the signal acquisition module 400 includes a high-precision micro-control probe station, and the phase change memory placed on the probe station communicates with the entire test system through a probe.
As an example, as shown in fig. 2, the parameter setting module 200 includes an address selecting unit 201 and a pulse signal generating unit 202 respectively connected between the main control module 100 and the switching module 300; wherein the content of the first and second substances,
the address selection unit 201 is configured to output an address signal to the signal acquisition module 400 under the control of the main control module 100; and
the pulse signal generating unit 202 is configured to sequentially output an erase operation current and a write operation current to the signal collecting module 400 under the control of the main control module 100, where the write operation current output each time is sequentially increased from the minimum write operation current to the maximum write operation current by using the write operation current change step as a variation.
Referring to fig. 1 to 4, a method for optimizing a write operation current of a phase change memory according to the present embodiment is described in detail with reference to the system for optimizing a write operation current of a phase change memory according to the present embodiment.
Before testing, a phase change memory (4M phase change memory) to be tested needs to be placed on the probe table, the probe is electrically connected with a corresponding PAD of the phase change memory to be tested, communication between the phase change memory to be tested and the whole testing system is realized, and corresponding testing is performed after hardware connection is completed, wherein the method specifically comprises the following steps:
1) setting the minimum write operation current I of the phase change memory to be tested according to the factory parameters of the phase change memory to be testedminMaximum write operation current ImaxAnd write operation current change step Istep。
2) The switching module 300 is controlled by the main control module 100, so that the signal acquisition module 400 is connected to the parameter setting module 200, and the main control module 100 controls the address selection unit 201 to generate an address signal and output the address signal to the signal acquisition module 400, so as to select a plurality of units to be operated from the phase change memory to be tested.
3) The main control module 100 controls the pulse signal generating unit 202 to generate an erasing operation current to erase the unit to be operated, so that the unit to be operated becomes a crystalline state (low resistance state).
4) Controlling the pulse signal generating unit 202 to generate a write operation current through the main control module 100 so as to perform write operation on the unit to be operated; at this time, the write operation current is the minimum write operation current Imin。
5) The switching module 300 is controlled by the main control module 100, so that the signal acquisition module 400 is connected with the parameter measurement module 500, and the unit to be operated is electrically tested by the parameter measurement module 500 to successively obtain the minimum write operation current IminCorresponding resistance data and V-I characteristic curve; and the minimum write operation current I is transmitted through the main control module 100minThe corresponding resistance data and the V-I characteristic curve are transmitted to the data processing module 600.
6) The switching module 300 is controlled by the main control module 100, so that the signal acquisition module 400 is connected to the parameter setting module 200, and the pulse signal generation unit 202 is controlled by the main control module 100 to generate an erasing operation current, so as to erase the unit to be operated, so that the unit to be operated becomes a crystalline state (low resistance state).
7) Controlling the pulse signal generating unit 202 to generate a write operation current by the main control module 100 to perform a write operation on the unit to be operated, wherein the write operation current is obtained by adding a write operation current change step length I on the original basisstep；
8) The switching module 300 is controlled by the main control module 100, so that the signal acquisition module 400 is connected with the parameter measurement module 500, and the unit to be operated is electrically tested by the parameter measurement module 500, so as to successively acquire resistance data and a V-I characteristic curve corresponding to write operation current; the resistance data and the V-I characteristic curve corresponding to the write operation current are transmitted to the data processing module 600 through the main control module 100;
9) repeating 6) to 8) until the maximum write operation current ImaxThe corresponding resistance data and the V-I characteristic curve are transmitted to the data processing module 600;
10) the data processing module 600 performs statistical analysis on the resistance data corresponding to each write operation current, and selects a true write operation current for enabling the unit to be operated to successfully perform write operation from each write operation current; fitting a V-I characteristic curve corresponding to each true write operation current to obtain a sub-threshold slope corresponding to each true write operation current; and then carrying out statistical analysis on the obtained subthreshold slope so as to obtain the optimal write operation current of the phase change memory.
It can be seen that the sub-threshold slope obtained by the above method is shown in fig. 3, and it can be seen from fig. 3 that as the true write operation current becomes larger, the sub-threshold slope STS becomes larger and the distribution becomes more saturated; when the sub-threshold slope STS is saturated, the corresponding true write operation current is about 0.81mA, so that the 0.81mA true write operation current is used as the optimal write operation current of the phase change memory to be tested, the write operation effect of the phase change memory to be tested is ensured, and unnecessary power consumption is reduced. While fig. 4 shows the resistance data distribution corresponding to the true write operation current, it can be seen from fig. 4 that the resistance distributions of the cells to be operated are completely indistinguishable in the process of the true write operation current changing from 0.58mA to 0.77mA, while the subthreshold slope STS shown in fig. 3 can be completely distinguished and has a rule increasing with the increase of the true write operation current. Therefore, as can be seen from fig. 3 and 4, the method described in this embodiment can still realize the screening of the write operation current in the case that the conventional method cannot be applied.
In summary, the system and method for optimizing the write operation current of the phase change memory according to the present invention have the following advantages:
by the system and the method, the write operation current of the phase change memory can be optimized, and the precision of write operation current screening is greatly improved; the effect of write operation is ensured while unnecessary power consumption of the RESET operation is reduced; the influence of over-operation on the fatigue reliability of the phase change memory can be avoided, the high-temperature durability and the reading durability of the phase change memory are ensured, and the service life of the phase change memory is prolonged.
The method provided by the invention starts from a microscopic angle, has the advantages of simplicity and convenience in operation, high screening precision, low testing cost, no damage to the chip and the like, and can be used for accurately determining the most suitable write operation current parameter of mass production chips and improving the performance of the chips.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A method for obtaining an optimal write operation current of a phase change memory, the method comprising:
setting the minimum write operation current, the maximum write operation current and the write operation current change step length of the phase change memory, and selecting a plurality of units to be operated from the phase change memory;
adjusting the write operation current based on the write operation current change step length to enable the write operation current to be sequentially increased from the minimum write operation current to the maximum write operation current; after the write operation current is obtained each time, performing write operation on the unit to be operated based on the write operation current, and after the write operation is finished, performing electrical test on the unit to be operated to obtain resistance data and a V-I characteristic curve corresponding to the write operation current; before writing operation is carried out on the unit to be operated each time, erasing operation is carried out on the unit to be operated based on the same preset erasing parameters;
carrying out statistical analysis on resistance data corresponding to different write operation currents, and screening true write operation currents which enable the unit to be operated to successfully carry out write operation; fitting a V-I characteristic curve corresponding to the true write operation current to obtain a sub-threshold slope corresponding to the true write operation current; and
and carrying out statistical analysis on the obtained subthreshold slope to obtain the optimal write operation current of the phase change memory.
2. The method of claim 1, wherein the minimum write current and the maximum write current are set according to a minimum initial write current and a maximum initial write current of the phase change memory, wherein the minimum write current is smaller than the minimum initial write current, and the maximum write current is larger than the maximum initial write current.
3. The method for obtaining the optimal write operation current of the phase change memory as claimed in claim 1, wherein the method for obtaining the V-I characteristic curve comprises: setting a scanning voltage, and carrying out V-I scanning test on the unit to be operated based on the scanning voltage to obtain a V-I characteristic curve; wherein the scan voltage is less than a threshold voltage of the phase change memory for phase change.
4. The method for obtaining the optimal write operation current of the phase change memory according to claim 1, wherein the method for screening the true write operation current comprises: and counting resistance data corresponding to different write operation currents, and screening each resistance data based on a reference resistance to take the write operation current corresponding to the resistance data larger than the reference resistance as the true write operation current.
5. The method for obtaining the optimal write operation current of the phase change memory according to claim 1, wherein the method for obtaining the subthreshold slope comprises: and carrying out log taking on the current value in the V-I characteristic curve so as to obtain a subthreshold slope corresponding to the true write operation current.
6. The method for obtaining the optimal write operation current of the phase change memory according to claim 1, wherein the method for obtaining the optimal write operation current of the phase change memory comprises: and carrying out statistical analysis on the sub-threshold slope, and screening out the true write operation current corresponding to the sub-threshold slope when the change of the sub-threshold slope is close to saturation so as to be used as the optimal write operation current of the phase change memory.
7. A system for obtaining an optimal write operation current for a phase change memory, the system comprising: the device comprises a main control module, a parameter setting module, a switching module, a signal acquisition module, a parameter measurement module and a data processing module, wherein the main control module is connected with the parameter setting module, the switching module and the data processing module; wherein the content of the first and second substances,
the main control module is used for controlling the switching module so as to realize that the signal acquisition module is connected with the parameter setting module or the signal acquisition module is connected with the parameter measurement module; when the signal acquisition module is connected with the parameter setting module, the signal acquisition module is used for controlling the parameter setting module to sequentially generate an address signal, an erasing operation current and a writing operation current, wherein the writing operation current generated each time is sequentially increased from a minimum writing operation current to a maximum writing operation current by taking a writing operation current change step as a variable quantity; when the signal acquisition module is connected with the parameter measurement module, the signal acquisition module is used for transmitting the resistance data and the V-I characteristic curve acquired by the parameter measurement module to the data processing module;
the parameter setting module is used for sequentially generating an address signal, an erasing operation current and a writing operation current under the control of the main control module and transmitting the address signal, the erasing operation current and the writing operation current to the signal acquisition module, wherein the writing operation current output each time is sequentially increased from the minimum writing operation current to the maximum writing operation current by taking the writing operation current change step as a variable quantity;
the switching module is used for realizing the connection between the signal acquisition module and the parameter setting module or between the signal acquisition module and the parameter measurement module under the control of the main control module;
the signal acquisition module is used for selecting a plurality of units to be operated from the phase change memory according to the address signal, the erasing operation current and the writing operation current which are sequentially output by the parameter setting module, and sequentially performing erasing operation and writing operation on the units to be operated;
the parameter measuring module performs electrical test on the phase change memory through the signal acquisition module, acquires resistance data and a V-I characteristic curve corresponding to each write operation current, and transmits the resistance data and the V-I characteristic curve to the data processing module through the main control module; and
the data processing module is used for carrying out statistical analysis on resistance data corresponding to each write operation current and screening true write operation currents which enable the unit to be operated to successfully carry out write operation; fitting a V-I characteristic curve corresponding to each true write operation current to obtain a sub-threshold slope corresponding to each true write operation current; and carrying out statistical analysis on the obtained subthreshold slope to obtain the optimal write operation current of the phase change memory.
8. The system for obtaining the optimal write operation current of the phase change memory according to claim 7, wherein the parameter setting module comprises an address selection unit and a pulse signal generation unit respectively connected between the main control module and the switching module; wherein the content of the first and second substances,
the address selection unit is used for outputting an address signal to the signal acquisition module under the control of the main control module; and
the pulse signal generating unit is used for sequentially outputting erasing operation current and writing operation current to the signal acquisition module under the control of the main control module, wherein the writing operation current output each time is sequentially increased from the minimum writing operation current to the maximum writing operation current by taking the writing operation current change step as a variable quantity.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1588664A (en) * | 2004-08-06 | 2005-03-02 | 中国科学院上海微系统与信息技术研究所 | Characterization emthod for convertable phase change material electric property |
| US6928022B2 (en) * | 2003-11-27 | 2005-08-09 | Samsung Electronics Co., Ltd. | Write driver circuit in phase change memory device and method for applying write current |
| CN101101965A (en) * | 2005-08-11 | 2008-01-09 | 上海交通大学 | Phase change film material of silicon-adulterated sulfur series for phase change memory |
| TW201025327A (en) * | 2008-12-26 | 2010-07-01 | Hynix Semiconductor Inc | Write driver circuit of PRAM |
| CN101814323A (en) * | 2009-02-23 | 2010-08-25 | 财团法人工业技术研究院 | Verification circuit and method of phase change memory array |
| CN102290106A (en) * | 2011-07-06 | 2011-12-21 | 华中科技大学 | Device for testing phase change memory unit array |
| CN102543170A (en) * | 2012-02-17 | 2012-07-04 | 北京时代全芯科技有限公司 | Method for realizing low power consumption of phase change memory |
| CN102831935A (en) * | 2012-05-18 | 2012-12-19 | 华中科技大学 | Pulse I-V (intravenous) characteristic testing method and device of phase change memory unit |
| CN102915765A (en) * | 2011-08-05 | 2013-02-06 | 海力士半导体有限公司 | Nonvolatile memory system and program method thereof |
-
2018
- 2018-04-23 CN CN201810368154.4A patent/CN108597558B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6928022B2 (en) * | 2003-11-27 | 2005-08-09 | Samsung Electronics Co., Ltd. | Write driver circuit in phase change memory device and method for applying write current |
| CN1588664A (en) * | 2004-08-06 | 2005-03-02 | 中国科学院上海微系统与信息技术研究所 | Characterization emthod for convertable phase change material electric property |
| CN101101965A (en) * | 2005-08-11 | 2008-01-09 | 上海交通大学 | Phase change film material of silicon-adulterated sulfur series for phase change memory |
| TW201025327A (en) * | 2008-12-26 | 2010-07-01 | Hynix Semiconductor Inc | Write driver circuit of PRAM |
| CN101814323A (en) * | 2009-02-23 | 2010-08-25 | 财团法人工业技术研究院 | Verification circuit and method of phase change memory array |
| CN102290106A (en) * | 2011-07-06 | 2011-12-21 | 华中科技大学 | Device for testing phase change memory unit array |
| CN102915765A (en) * | 2011-08-05 | 2013-02-06 | 海力士半导体有限公司 | Nonvolatile memory system and program method thereof |
| CN102543170A (en) * | 2012-02-17 | 2012-07-04 | 北京时代全芯科技有限公司 | Method for realizing low power consumption of phase change memory |
| CN102831935A (en) * | 2012-05-18 | 2012-12-19 | 华中科技大学 | Pulse I-V (intravenous) characteristic testing method and device of phase change memory unit |
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