JP2006108645A - Multilevel phase change memory, method of operating the same, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilevel phase change memory having a single memory cell, a method of manufacturing the same, and a method of operating the same. <P>SOLUTION: The multilevel phase change memory, the method of operating the same, and the method of manufacturing the same are provided. The phase change memory includes two phase change layers and electrodes which are arranged in a parallel structure to form a memory cell. A voltage driving mode is used for controlling and driving the memory such that a multilevel memory state can be obtained by applications at different voltage levels. Another embodiment includes two phase change layers and electrodes which are arranged in a series structure to form a memory cell. A current driving mode is used for controlling and driving the memory such that a multilevel memory state can be obtained by applications at different current levels. The provided multilevel phase change memory has a larger number of bits and a larger capacity than a memory having a single phase change layer. Further, the series structure makes it possible to reduce a cell area and a device size. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to semiconductor memory devices, and more particularly to semiconductor memory devices having multi-level memory states.

  Memory is widely used in common electrical devices. Many are DRAM, SRAM, or flash memory. The application and architecture of the electrical device determines its memory usage and required capacity. Development of memory technologies such as FeRAM, MRAM, and phase change memory is ongoing.

  Phase change semiconductor memory stores data via resistance changes caused by material phase changes. Regarding the phase change material, in the 1960s, S. R. Ovshinsky discovered that chalcogenide has distinctly different optical properties and electrical conductivity in its crystallization (state) and amorphization (state). Chalcogenides are capable of high-speed reversible conversion and have switching / memory applications.

  Phase change memory is called semiconductor memory because chalcogenide belongs to group VIA of the periodic table of elements and is a semiconductor material between metal and nonmetal. For example, it is necessary to add some elements for specific purposes in practice, such as for increasing the amorphization / crystallization rate or improving the crystal properties.

  Phase change memory meets the requirements of large and fast storage operation and long storage time. These memories have the advantages of small size, more storage data, and fast operating speed, and can store data for more than 10 years at 130 ° C. Thus, phase change memory is a non-volatile memory that has great potential and has high write / read speed, high integrity, long-term durability, low power consumption, and radiation resistance. The main technological trends focus on lower power consumption through higher recording density and memory cell miniaturization.

  However, in addition to increasing memory density by reducing area, multi-level / multi-state memories are being considered. Thus, a single memory cell has two or more memory states without changing the component size.

  In the related art, Tyler Lowrey (Ovonyx) provides a multi-state structure in published in-house technical papers. Memory cells with a single phase change layer are used to obtain multi-levels with different resistance values by controlling the reset current. However, the small current isolation problem of writing errors due to current offset must be solved. Furthermore, it is difficult to control the multi-state after continuous operation due to the influence of heating.

  US Pat. No. 5,534,711 discloses a multilevel storage device for improving the stability of multilevel operation.

  U.S. Pat. No. 6,507,061 discloses a phase change memory having two phase change layers separated by a barrier layer, which can be programmed to reduce size and provide a suitable heat sink. One of these phase change layers is not used to store data, but is used to maintain temperature.

  U.S. Pat. No. 6,635,91 discloses a four-level memory cell that belongs to the category of Programmable Metallization Cell Memory (PMCm). This cell is composed of a solid electrolyte layer and two electrodes. The conductivity of the solid electrolyte layer is changed by supplying an electric field through the electrodes.

  Phase change memory, MRAM, and FRAM are main memory technology trends, such as non-volatile, high speed (close to the operating speed of DRAM and SRAM), large capacity, high integrity, high environmental resistance, long storage time, etc. Have advantages. Furthermore, the operating voltage is gradually decreasing. These memories may be replaced with flash memory in the near future. Accordingly, there is an urgent need for a new phase change memory structure.

  Accordingly, the present invention relates to a multi-level phase change memory, a method for manufacturing the same, and a method for operating the same that substantially solve the problems of the related art.

  It is an object of the present invention to provide a multi-level phase change memory through a single memory cell, a method for manufacturing the same, and a method for operating the same.

  Another object of the present invention is to provide a multi-level phase change memory, a method for manufacturing the same, and a method for operating the same. The memory cell includes two memory cells formed in series to obtain a memory cell having a high density. Consists of independent phase change units. The materials of these phase change units may be the same or different.

  Another object of the present invention is to provide a multi-level phase change memory, a method for manufacturing the same, and a method for operating the same. The memory cell includes two memory cells formed in parallel to obtain a memory cell having a high density. Consists of independent phase change units. The materials of these phase change units may be the same or different.

  Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure described in the written description, the claims thereof and the appended drawings.

  In accordance with the objectives of the present invention to achieve these and other advantages, a phase change memory includes a first phase change layer and a second phase change layer. The first phase change layer has a first characteristic curve with a current-time relationship and includes a crystalline state and an amorphous state, and the second phase change layer has a second characteristic curve with a current-time relationship. And includes a crystalline state and an amorphous state. The first and second characteristic curves intersect with each other to form a first state, a second state, a third state, and a fourth state. In the first state, the first phase change layer and the second phase change layer are in a crystalline state, while in the second state, the first phase change layer is in an amorphous state and the second phase change layer The layer is in the crystalline state. In the third state, the first phase change layer is in a crystalline state and the second phase change layer is in an amorphous state, while in the fourth state, the first phase change layer and the second phase change layer Is in an amorphous state.

  In accordance with the purpose of the present invention to achieve these and other advantages, as embodied and broadly described herein, a phase change memory includes a first phase change layer having a crystalline state and an amorphous state, and a crystalline state. A second phase change layer having an amorphous state and a first phase change layer and a second phase for supplying an electrical signal to change states of the first phase change layer and the second phase change layer A first top electrode and a second top electrode respectively formed on one surface of the change layer, and at least one bottom electrode formed on the other surface of the first phase change layer and the second phase change layer Including.

  In accordance with the objectives of the present invention to achieve these and other advantages, the phase change memory includes a first phase change layer, a second phase change layer, and between the first phase change layer and the second phase change layer. The intermediate layer formed on the first phase change layer, the first electrode formed on the other side of the first phase change layer, and the second electrode formed on the other side of the second phase change layer.

  In accordance with the objectives of the present invention to achieve these and other advantages, a phase change memory state conversion method includes applying a first pulse to crystallize a first phase change layer and a second phase change layer. And applying a second pulse to change the crystalline states of the first phase change layer and the second phase change layer. The first pulse and the second pulse are voltage signals. The third pulse and the fourth pulse are voltage signals.

  In order to achieve these and other advantages, in accordance with the objectives of the present invention, a method for phase change of a phase change memory includes applying a pulse to change the crystalline state of the first phase change layer and the second phase change layer. Prepare. This pulse is a voltage signal.

  In accordance with the purpose of the present invention, phase change memory has the advantage of a multi-level memory state in only one cell.

  In accordance with the purpose of the present invention, phase change memory has the advantage of defining read isolation for multilevel memory states.

  In accordance with the purpose of the present invention, phase change memory has the advantage of transferring the memory state through one or two operational steps.

  In accordance with the purpose of the present invention, phase change memory has the advantage of reducing the area of one bit. In this way, the memory density is increased.

  In accordance with the purpose of the present invention, phase change memory has the advantages of direct write and erase operations.

  In accordance with the purpose of the present invention, phase change memory has the advantage of reducing the time of write and erase operations.

  In accordance with the objectives of the present invention, phase change memory has the advantage of reducing the complexity for manufacturing the device. No additional mask is required for memory processing.

  In accordance with the objectives of the present invention, the phase change memory uses a series configuration and can employ the same processing for a single phase change layer.

  In accordance with the purpose of the present invention, the phase change memory has 2 bits in a single cell under the same region. Memory has the advantage of increasing device density.

That is, the first invention of the present application is a phase change memory, which includes a first phase change layer having a first characteristic curve of current-time relationship including at least a crystalline state and an amorphous state, and at least a crystalline state and an amorphous state. A second phase change layer having a second characteristic curve having a current-time relationship, including a state, and the first and second characteristic curves intersecting each other to form a first state, a second state, a third state And the fourth state. In the first state, the first phase change layer and the second phase change layer are in a crystalline state, and in the second state, the first phase change layer Is in an amorphous state, the second phase change layer is in a crystalline state, and in the third state, the first phase change layer is in a crystalline state, the second phase change layer is in an amorphous state, and the fourth state , The first phase change layer and the second phase change layer are in an amorphous state There is a phase change memory.
A second invention of the present application is the memory according to the first invention, wherein the materials of the first phase change layer and the second phase change layer are the same.
A third invention of the present application is the memory according to the first invention, wherein materials of the first phase change layer and the second phase change layer are different.
According to a fourth aspect of the present invention, there is provided a phase change memory, wherein a first phase change layer having a crystalline state and an amorphous state, a second phase change layer having a crystalline state and an amorphous state, and an electric signal are supplied. In order to change the states of the first phase change layer and the second phase change layer, the first top formed on one surface of the first phase change layer and the second phase change layer A phase change memory comprising an electrode, a second top electrode, and at least one bottom electrode formed on another surface of the first phase change layer and the second phase change layer.
A fifth invention of the present application is the memory according to the fourth invention, wherein the materials of the first phase change layer and the second phase change layer are the same.
The sixth invention of the present application is the memory according to the fourth invention, wherein the materials of the first phase change layer and the second phase change layer are different.
A seventh invention of the present application is the memory according to the fourth invention, wherein the materials of the first top electrode and the second top electrode are the same.
An eighth invention of the present application is the memory according to the fourth invention, wherein the materials of the first top electrode and the second top electrode are different.
The ninth aspect of the present invention is the same as the fourth aspect, wherein the contact area between the first top electrode and the first phase change layer is the same as the contact area between the second top electrode and the second phase change layer. It is a memory of description.
The tenth invention of the present application is the fourth invention, wherein a contact area between the first top electrode and the first phase change layer is different from a contact area between the second top electrode and the second phase change layer. Memory.
An eleventh invention of the present application is the memory according to the fourth invention, wherein the bottom electrode is composed of one electrode connected to the first phase change layer and the second phase change layer.
A twelfth aspect of the present invention is the memory according to the fourth aspect, comprising two electrodes connected to the first phase change layer and the second phase change layer, respectively.
A thirteenth aspect of the present invention is the memory according to the twelfth aspect, wherein the materials of the two bottom electrodes are the same.
A fourteenth aspect of the present invention is the memory according to the twelfth aspect, wherein the materials of the two bottom electrodes are different.
A fifteenth aspect of the present invention is the memory according to the fourth aspect, further comprising a functional layer formed between the first top electrode and the first phase change layer.
According to a sixteenth aspect of the present invention, the functional layer includes a heating layer for improving heating efficiency, a nucleation acceleration layer for accelerating the crystallization speed of the first phase change layer, and the first phase change layer. The memory according to the fifteenth aspect of the present invention, which is one of the diffusion stop layers for preventing diffusion between the first top electrode and the first top electrode, or any combination thereof.
The seventeenth invention of the present application is the memory according to the fourth invention, further comprising a functional layer formed between the second top electrode and the first phase change layer.
According to an eighteenth aspect of the present invention, the functional layer includes a heating layer for improving heating efficiency, a nucleation acceleration layer for accelerating the crystallization speed of the second phase change layer, and the first phase change layer. The memory according to the seventeenth aspect of the present invention, which is one or any combination of diffusion stop layers for preventing diffusion between the first top electrode and the second top electrode.
According to a nineteenth aspect of the present invention, there is provided a manufacturing method for manufacturing a phase change memory, the step of providing a substrate having a metal contact formed therein, the step of forming a bottom electrode on the substrate, Forming a phase change layer on the electrode; implanting ions in a portion of the phase change layer to form a first phase change layer and a second phase change layer; and a corresponding first phase Forming a first top electrode and a second top electrode on the change layer and the second phase change layer.
The twentieth invention of the present application is the manufacturing method according to the nineteenth invention, further comprising a step of etching the bottom electrode and the phase change layer.
Further, the twenty-first invention of the present application is the element according to the nineteenth invention, wherein the element for ion implantation is one selected from the group consisting of Group IIIA, Group IVA, Group VA, Group VIA, and rare earth transition metal. It is a manufacturing method.
The twenty-second invention of the present application is based on the nineteenth invention, further comprising a step of etching the first phase change layer and the second phase change layer to separate the first phase change layer and the second phase change layer. It is a manufacturing method of description.
According to a twenty-third aspect of the present invention, the functional layer is formed before the first top electrode is formed, and the functional layer is a crystallization of the heating layer for improving the heating efficiency and the first phase change layer. A nucleation acceleration layer for accelerating the velocity, and one or any combination thereof of a diffusion stop layer for preventing diffusion between the first phase change layer and the first top electrode A manufacturing method according to the nineteenth invention.
In the twenty-fourth invention of the present application, the functional layer is formed before the second top electrode is formed, and the functional layer is a crystallization of a heating layer for improving heating efficiency and a second phase change layer. A nucleation acceleration layer for accelerating the velocity, and one or any combination thereof of a diffusion stop layer for preventing diffusion between the second phase change layer and the second top electrode A manufacturing method according to the nineteenth invention.
According to a twenty-fifth aspect of the present invention, there is provided a manufacturing method for manufacturing a phase change memory, comprising: providing a substrate having a metal contact formed therein; forming a bottom electrode on the substrate; Forming a first phase change layer and a second phase change layer on the electrode, and forming the first top electrode and the second top electrode into the corresponding first phase change layer and second phase change layer; And a forming step.
According to a twenty-sixth aspect of the present invention, the functional layer is formed before the first top electrode is formed, and the functional layer is a crystallization of the heating layer for improving the heating efficiency and the first phase change layer. A nucleation acceleration layer for accelerating the velocity, and one or any combination thereof of a diffusion stop layer for preventing diffusion between the first phase change layer and the first top electrode A manufacturing method according to a twenty-fifth aspect of the present invention.
According to a twenty-seventh aspect of the present invention, the functional layer is formed before the second top electrode is formed, and the functional layer is a crystallization of a heating layer for improving heating efficiency and a second phase change layer. A nucleation acceleration layer for accelerating the velocity, and one or any combination thereof of a diffusion stop layer for preventing diffusion between the second phase change layer and the second top electrode A manufacturing method according to a twenty-fifth aspect of the present invention.
According to a twenty-eighth aspect of the present invention, there is provided the phase change method for a phase change memory according to the fourth aspect, wherein the first phase change layer and the second phase change layer are crystallized by applying the first pulse. And a step of changing a crystal state of the first phase change layer and the second phase change layer by applying a second pulse.
The 29th invention of the present application is the phase change method of the phase change memory according to the 4th invention, wherein a pulse is applied to change the crystal states of the first phase change layer and the second phase change layer. A state conversion method including steps.
The 30th invention of the present application is a phase change memory, which is formed between a first phase change layer, a second phase change layer, and a first phase change layer and a second phase change layer. A phase change comprising: an intermediate layer formed; a first electrode formed on the other side of the first phase change layer; and a second electrode formed on the other side of the second phase change layer It is memory.
A thirty-first aspect of the present invention is the memory according to the thirtieth aspect, wherein the first phase change layer and the second phase change layer are made of the same material.
A thirty-second invention of the present application is the memory according to the thirtieth invention, wherein the materials of the first phase change layer and the second phase change layer are different.
The 33rd invention of the present application is the memory according to the 30th invention, wherein the materials of the first electrode and the second electrode are the same.
A thirty-fourth aspect of the present invention is the memory according to the thirtieth aspect, wherein the materials of the first electrode and the second electrode are different.
The 35th invention of the present application is the invention as described in the 30th invention, wherein the contact area between the first electrode and the first phase change layer is the same as the contact area between the second electrode and the second phase change layer. It is memory.
The thirty-sixth aspect of the present invention is according to the thirty-third aspect, wherein a contact area between the first electrode and the first phase change layer is different from a contact area between the second electrode and the second phase change layer. It is memory.
A thirty-seventh aspect of the present invention is the memory according to the thirtieth aspect, further comprising a first functional layer formed between the first electrode and the first phase change layer.
According to a thirty-eighth aspect of the present invention, the first functional layer includes a heating layer for improving heating efficiency, a nucleation promoting layer for accelerating the crystallization speed of the first phase change layer, and the first functional layer. The memory according to the thirty-seventh aspect, which is one or any combination of diffusion stop layers for preventing diffusion between the phase change layer and the first electrode.
The thirty-ninth aspect of the present invention is the memory according to the thirtieth aspect, further comprising a second functional layer formed between the second electrode and the second phase change layer.
In the 40th invention of the present application, the second functional layer includes a heating layer for improving heating efficiency, a nucleation acceleration layer for accelerating the crystallization speed of the second phase change layer, and a second layer. The memory according to the thirty-ninth aspect, wherein the memory is one or any combination of diffusion stop layers for preventing diffusion between the phase change layer and the second electrode.
According to a forty-first aspect of the present invention, there is provided a manufacturing method for manufacturing a phase change memory, the step of providing a substrate having a metal contact formed therein, and the step of forming a first electrode on the substrate. Forming a first phase change layer, sequentially forming an intermediate layer and a second phase change layer on the first electrode, and forming a second electrode on the second phase change layer; It is a manufacturing method provided with.
The forty-second invention of the present application is the manufacturing method according to the forty-first invention, further comprising the step of forming a first functional layer on the first electrode.
The 43rd invention of the present application is the manufacturing method according to the 41st invention, further comprising a step of forming a second functional layer on the second phase change layer.
In the 44th invention of the present application, the first functional layer is formed before the first electrode is formed, and the first functional layer is a heating layer for improving heating efficiency, a first phase. One or more of a nucleation acceleration layer for accelerating the crystallization rate of the change layer and a diffusion stop layer for preventing diffusion between the first phase change layer and the first electrode It is a manufacturing method as described in the 41st invention which is arbitrary combinations.
According to a 45th aspect of the present invention, the second functional layer is formed before the second electrode is formed, and the second functional layer is a heating layer for improving heating efficiency, a second phase. One or more of a nucleation acceleration layer for accelerating the crystallization rate of the change layer and a diffusion stop layer for preventing diffusion between the second phase change layer and the second electrode It is a manufacturing method as described in the 41st invention which is arbitrary combinations.
The 46th invention of the present application is the manufacturing method according to the 41st invention, further comprising a step of forming an oxide layer before forming the first electrode.
The 47th invention of the present application is the manufacturing method according to the 41st invention, further comprising a step of forming an oxide layer before forming the second electrode.
The 48th invention of the present application is a phase change memory state conversion method including at least a first phase change layer and a second phase change layer, and each of these layers has four memory states formed therein. At least having a crystalline state and an amorphous state, wherein the method crystallizes the first phase change layer and the second phase change layer by applying a first pulse which is a voltage signal; Applying a second pulse as a signal to change the crystal states of the first phase change layer and the second phase change layer.
The 49th invention of the present application is a phase change memory state conversion method including at least a first phase change layer and a second phase change layer, and each of these layers has four memory states formed therein. State conversion comprising at least a crystalline state and an amorphous state, the method comprising applying a pulse as a voltage signal to change the crystalline state of the first phase change layer and the second phase change layer Is the method.

Further scope of application of the present invention will become apparent from the detailed description given below. However, since various changes and modifications within the spirit and scope of the present invention will be apparent to those skilled in the art from this detailed description, the detailed description and specific examples illustrating the embodiments of the present invention are provided as examples. It is given solely and is intended to provide a further description of the claimed invention.
The accompanying drawings, which provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, explain the principles of the invention.

[Description of related technology]
This application enjoys the benefit of Taiwan Patent Applications 93130600 and 93130598, both filed on October 8, 2004, and is incorporated herein for all purposes fully described below.

  Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. References herein to "one embodiment" and "an embodiment" are used to refer to a particular feature, structure, or characteristic described in connection with that embodiment. Is included in at least one embodiment of the present invention. The appearance of the phrase “in one emblem” (in one embodiment) in various places in this specification is not necessarily all referring to the same embodiment.

  Reference is made to FIG. 1 showing the structure of the phase change memory of the present invention. In this embodiment, the phase change memory includes a first phase change layer 10, a second phase change layer 20, a bottom electrode 30, a first top electrode 41, and a second top electrode 42. The first phase change layer 10 and the second phase change layer 20 are formed on the bottom electrode 30 by a semiconductor process. The first top electrode 41 is formed on the first phase change layer 10 by a semiconductor process. The second top electrode 42 is formed on the second phase change layer 20 by a semiconductor process.

  In another embodiment, the protective layer 50 covers and protects the first phase change layer 10, the second phase change layer 20, the bottom electrode 30, the first top electrode 41, and the second top electrode 42. In order to do so, it is formed of a dielectric material by a semiconductor process. In another embodiment, the bottom electrode 30 is formed on a substrate 60, which is formed for connection to a transistor (not shown) necessary for operation. This substrate 60 is formed by the previous process for a COMS or bipolar transistor. In another embodiment, the metal line 70 is formed on the protective layer 50 so that the first phase change layer 10 and the second phase change layer 20 are heated to change state via an electrical signal. The first top electrode 41 and the second top electrode 42 are contacted to provide a voltage or current signal, thereby controlling the operation of the phase change memory according to the present invention.

  In accordance with the principles of the present invention, two phase change layers are used and connected in parallel to form a single memory cell. Each phase change layer has a crystalline state and an amorphous state, and these states change by heating. First phase change layer 10 has a crystalline state and an amorphous state, while second phase change layer 20 has a crystalline state and an amorphous state. Thus, when two phase change layers are connected in parallel, four states are formed. These four states are hereinafter referred to as a first state, a second state, a third state, and a fourth state. The conditions for the four states are described below.

  It is preferable that the first phase change layer 10 and the second phase change layer 20 are different materials for phase change, have different characteristics, and have a resistance difference. The crystallization and amorphization rates of first phase change layer 10 and second phase change layer 20 are preferably different. For example, one of these layers can use a material with characteristics of low resistance, high crystallization temperature, and fast crystallization rate, while the other layer has high resistance, low crystallization temperature, and slower crystallization. A material having the characteristics of the conversion rate can be used. In one embodiment, the materials of first phase change layer 10 and second phase change layer 20 are different. In other embodiments, the two layers can use the same phase change material. The technical effect of the four memory states can be achieved by forming two single phase change cells in parallel via an optimized structure design.

For example, the first phase change layer 10 can use doped eutectic SbTe, AgInSbTe, or GeInSbTe. The second phase change layer 20 can use a GeSbTe compound such as Ge ₂ Sb ₂ Te ₅ . The foregoing materials are for illustration only and are not intended to limit the composition of the invention. Two phase change layers with different resistance change and crystallization / amorphization rate, change phase change layer composition, adjust phase change layer thickness, change top electrode type and contact area, or phase change It is obtained by forming a functional layer between the layer and the top electrode.

  The bottom electrode 30 not only connects the first phase change layer 10 and the second phase change layer 20 to energize, but also assists the heat sink. A material having stable chemical properties (does not react with the phase change layer) and high thermal conductivity, such as TiN, can be used.

  The material of the first top electrode 41 and the second top electrode 42 may be the same as the material of the bottom electrode 30. In one embodiment, the material of the first top electrode 41 and the second top electrode 42 may be the same as the material of the bottom electrode 30 to simplify the manufacturing process. In other embodiments, the sizes of the first top electrode 41 and the second top electrode 42 may be the same. In still other embodiments, the sizes of the first top electrode 41 and the second top electrode 42 may be different. The size of the electrode is adjusted to control the heating efficiency.

  In accordance with the principles of the present invention, in one embodiment, the functional layer 80 is optionally between the first top electrode 41 and the first phase change layer 10 or between the second top electrode 42 and the second phase electrode. It is formed between the phase change layer 20. As shown in FIG. 2, the functional layer 80 may be arranged as one layer or both layers. In one embodiment, the functional layer 80 may be a heating layer for improving the heating efficiency. In another embodiment, the functional layer 80 may be a nucleation acceleration layer for accelerating the crystallization speed of the first phase change layer. In still another embodiment, the functional layer 80 may be a diffusion stop layer for preventing diffusion between the first phase change layer and the first top electrode. As the material of the functional layer 80, refractory metal, conductive metal carbide, alloy carbide, metal nitride, alloy nitride, metal carbonitride, or alloy carbonitride can be used. The functional layer 80 may have one, two, or all of the above functions according to the material properties.

  In one embodiment, the provided phase change memory selects a cell to be written or read through a transistor such as a MOSFET or BJT. The transistor is connected to the bottom electrode 30 through a metal contact 61. Sufficient heat for the phase change of the first phase change layer 10 and the second phase change layer 20 is applied to the heater or by applying a voltage to the first top electrode 61 and the second top electrode 62. Generated. Next, a signal is sent to the receiving end and the sense amplifier via the top electrode and the bottom electrode. In accordance with the principles of the present invention, the operation of the multi-level phase change memory is controlled by the applied voltage and the applied time.

  Reference is made to FIGS. 3A to 3I which illustrate the fabrication process of a phase change memory according to the present invention. In this embodiment, the phase change layer uses the same material. One composition of the phase change layer is transformed by the ion implant.

  The substrate 100 with the metal contact 101 formed therein is provided for a pre-fabrication process for CMOS or bipolar. A bottom electrode 102 is formed on the substrate 100. Next, as shown in FIGS. 3A to 3B, a phase change layer 103 is deposited and the bottom electrode 102 and the phase change layer 103 are etched. For example, the phase change layer 103 is made of 16 at. % To 37 at. Eutectic SbTe having a% composition can be used.

  Next, a portion of the phase change layer 103 is implanted to change the chemical composition. Implanted elements include Group IIIA, Group IVA, Group VA, Group VIA, and rare earth transition metals. After the implantation, as shown in FIG. 3E, a first phase change layer 103A and a second phase change layer 103B are formed, and both are connected to each other.

  As shown in FIG. 3F, the phase change layer 103 (the first phase change layer 103A and the second phase change layer 103B connected to each other) is composed of the first phase change layer 103A and the second phase change layer 103B. Etch to separate.

  Next, a dielectric layer 104 is deposited for protection. As shown in FIGS. 3G-3H, the first top electrode 105 and the second top electrode 106 are deposited through a masking process and an etching process. The surface of the dielectric layer 104 is polished, and then a metal line 107 is deposited as shown in FIG. 3I. In one embodiment, the sizes of the first top electrode 105 and the second top electrode 106 are the same. In other embodiments, the sizes of the first top electrode 105 and the second top electrode 106 are different.

  In other embodiments, a functional layer (referred to as functional layer 80 in FIG. 2) can be formed between first top electrode 105 and first phase change layer 103A. The functional layer includes a heating layer for improving heating efficiency, a nucleation acceleration layer for accelerating the crystallization speed of the first phase change layer, and diffusion between the first phase change layer and the first top electrode. It may be a diffusion stop layer for preventing or an arbitrary combination of these layers. Optionally, this functional layer is formed between the second top electrode 106 and the second phase change layer 103B. It should be noted that one or two functional layers may be employed.

  Reference is made to FIGS. 4A to 4G illustrating the manufacturing process of a phase change memory according to the present invention. In this embodiment, each phase change layer uses different materials.

  The substrate 200 with the metal contacts 201 formed therein is provided for a pre-fabrication process for CMOS or bipolar. The bottom electrode 202 is formed on the substrate 200. As shown in FIGS. 4A to 4D, a first phase change layer 203 and a second phase change layer 204 are deposited. As the material of these phase change layers, eutectic SbTe or GeSbTe compounds can be used. In one embodiment, the thickness of the first phase change layer 203 and the second phase change layer 204 may be the same. In other embodiments, the thickness of the first phase change layer 203 and the second phase change layer 204 may be different.

  Next, a dielectric layer 205 is deposited for protection. As shown in FIGS. 4E-4F, the first top electrode 206 and the second top electrode 207 are deposited through a masking process and an etching process. The surface of the dielectric layer 205 is polished and then a metal line 208 is deposited as shown in FIG. 4G. In one embodiment, the first top electrode 206 and the second top electrode 207 have the same size. In other embodiments, the sizes of the first top electrode 206 and the second top electrode 207 are different.

  In other embodiments, a functional layer (referred to as functional layer 80 in FIG. 2) can be formed between the first top electrode 206 and the first phase change layer 203. The functional layer includes a heating layer, a nucleation acceleration layer for accelerating the crystallization speed of the first phase change layer, and a diffusion stop for preventing diffusion between the first phase change layer and the first top electrode. It may be a layer or any combination of these layers. Optionally, this functional layer is formed between the second top electrode 207 and the second phase change layer 204. It should be noted that one or two functional layers may be employed.

  The operation of the phase change memory according to the present invention is shown as follows. Please refer to FIG. 5A to FIG. 5D.

  The phase change layer according to the present invention uses a voltage driven mode during operation. The first phase change layer 11 and the second phase change layer 12 are heated by applying different voltages on the first top electrode 41 and the second top electrode 42. Next, due to material properties, the first phase change layer 11 and the second phase change layer 12 generate 0, 1, or 2 amorphous volumes. In the present invention, the 2 amorphous volume is referred to as the fourth state, the 1 amorphous volume is referred to as the 2nd and 3rd states, and the 0 amorphous volume is referred to as the 1st state. Schematic diagrams of all states are shown in FIGS. 5A-5D. A phase change layer having an amorphous volume has the highest resistance. Therefore, the parallel resistance in the fourth state is the highest, the resistance in the third state is the second, the resistance in the second state is the third highest, and the resistance in the first state is the lowest. The four resistance levels correspond to four memory states and achieve four memory states.

  In accordance with the principles of the present invention, the physical parameters of the materials of the first phase change layer 11 and the second phase change layer 12 are shown in Table I. In this table, the first material is used for the first phase change layer 11 and the second material is used for the second phase change layer 12 or vice versa.

  The materials listed below are exemplary and illustrative and are not intended to limit the materials of the phase change memory of the present invention. Thus, those skilled in the art can obtain a phase change memory having four memory states through appropriate material selection.

It is assumed that the amorphous volume of the first material and the second material are the same. The ratio of thickness to crystallization area is 1: 9. The size of the heating electrode is the same. The total resistance for each state is estimated as follows.
<First state>
The first phase change layer and the second phase change layer are crystallized.
1 / R1 = 1 / [(5 × 10 ⁻³ ) × 10] +1 / [(1 × 10 ⁻² ) × 10] to 30, R1 = 0.03
<Second state>
The first phase change layer crystallizes and the second phase change layer becomes amorphous.
1 / R2 = 1 / [(5 × 10 ⁻³ ) × 10] + 1 / [100 × 1 + (1 × 10 ⁻² ) × 9] to 20, R2 = 0.05
<Third state>
The first phase change layer becomes amorphous and the second phase change layer crystallizes.
1 / R3 = 1 / [50 × 1 + (5 × 10 ⁻³ ) × 9] +1 / [(1 × 10 ⁻² ) × 10] -10, R3 = 0.1
<Fourth state>
The first phase change layer and the second phase change layer become amorphous.
1 / R4 = 1 / [50 × 1 + (5 × 10 ⁻³ ) × 9] + 1 / [100 × 1 + (1 × 10 ⁻² ) × 9] to 0.03, R4 = 33.3

  From the above estimation, the total resistance is determined by the resistance of the amorphized region. The total current when voltage V is applied is I4 = 0.03V, I3 = 10V, I2 = 20V, and I1 = 30V, respectively. Thus, the memory state is determined by reading the memory current.

  Reference is made to FIGS. 6A-6D of the assumed characteristic curves listed above. Regions I, II, III and IV in the drawing can be obtained by selecting an appropriate material or adjusting the size of the structure.

  A voltage pulse test of a single phase change cell is performed on the first material and the second material. Amorphization and crystallization conditions are obtained by modulating (changing) voltage (V) and time (t). The crystallized cell is used for the amorphization test, while the written cell is used for the crystallization test. These test results are shown in a Vt diagram having an amorphized region, a crystallized region, and an ablation region. The amorphized region and the crystallized region of each phase change material are adjusted so as not to overlap entirely by adjusting the structural parameters of the memory cell. Thus, there are a plurality of corresponding relationships according to different phase change materials. For example, the higher the crystallization temperature, the higher the bottom edge of the crystallization region, and the higher the melting point, the higher the bottom edge of the amorphization region. Edge becomes faster.

  When the two memories are connected in parallel and the voltage pulse (V, t) enters the overlapping amorphized region (area IV), each phase change layer has an amorphous volume. When the voltage pulse (V, t) enters the amorphized region of the first material and does not overlap with the amorphized region of the second material (area III), the first phase change layer has an amorphous volume. However, the second phase change layer does not work. When the voltage pulse (V, t) enters the amorphized region of the second material and does not overlap with the amorphized region of the first material (area II), only the second phase change layer generates an amorphous volume. However, the first phase change layer melts and cools down smoothly, and then crystallizes. When the voltage pulse (V, t) enters the overlapping crystallization region (area I), the two phase change layers crystallize, regardless of their state.

  Different first and second materials are selected for testing by appropriately adjusting the structural parameters, and the results obtained are shown in FIGS. 6A-6D. From the results shown in these figures, four memory states formed by two phase change layers are obtained.

  In accordance with the principles of the present invention, two methods can be employed for operation of the phase change memory when transitioning to different memory states.

  These two methods are hereinafter referred to as zero mode and direct overwrite mode. The memory state (second, third, and fourth states) is zero for zero mode operation, ie, the first state (the first phase change layer and the second phase change layer are crystallized). Is converted to another memory state. This operation is performed as follows.

  Two stage operation is used in zero mode operation. For the state conversion, the first pulse is generated by the first phase change layer and the second phase change layer such that the first phase change layer and the second phase change layer are crystallized to return to the first state. To be applied. A second pulse is then applied to change the crystals of the first phase change layer and the second phase change layer according to the memory state.

  Detailed operation will be described below with reference to FIG.

  The Y axis in FIG. 7 indicates the read current, and represents the first state, the second state, the third state, and the fourth state in order from the highest. The direction of the arrow represents a control signal for different memory states. In accordance with the principles of the present invention, the energy for each memory state is different. Therefore, four control signals are required according to the resistance of each state. These signals correspond to the first state, the second state, the third state, and the fourth state, respectively, a first control signal, a second control signal, a third control signal, And the fourth control signal.

  Control signals corresponding to phase change layer state conversions are listed in Table II.

  When the first control signal is applied, the first phase change layer and the second phase change layer are in a crystalline state (first state). When the second control signal is applied, these layers are in the second state. When the third control signal is applied, these layers are in the third state. When the fourth control signal is applied, these layers are in the fourth state.

  As shown in FIG. 7, when converted from the third state to the second state, the first control signal is first applied so that the cell is in the first state, and then the second The control signal is applied so that the cell is in the second state. In other embodiments, when converting from the fourth state to the second state, the first control signal is first applied such that the cell is in the first state, and then the fourth control. The signal is applied so that the cell is in the fourth state. Thus, in zero mode operation, two signals are required to change the memory state. The first pulse is applied to return the state to zero and the second pulse is applied so that the cell is in the desired state.

  In accordance with the principles of the present invention, there are few control signals for zero mode. It is easier to operate and there are no problems with incomplete crystallization of the amorphized volume.

  In other embodiments, the method is a direct overwrite mode. The aforementioned zero operation is not necessary for the direct override mode during state conversion. Similarly, four control signals listed in Table III are required.

  When the first control signal is applied, the first phase change layer and the second phase change layer are in a crystalline state (first state). When the second control signal is applied, these layers are in the second state. When the third control signal is applied, these layers are in the third state. When the fourth control signal is applied, these layers are in the fourth state.

  As shown in FIG. 8, when converting from the third state to the second state, only the second control signal is applied. In other embodiments, only the fourth control signal is applied when converting from the second state to the fourth state. Therefore, in the direct overwrite mode, only one pulse is necessary for state conversion. This direct overwrite mode has the advantage of shortening the conversion time, and the original memory state need not be detected first before conversion.

  In accordance with aspects of the present invention and the cd principle, a multi-level memory cell is composed of two independent single layer change cells connected in parallel and uses the same drive voltage for different resistance levels for writing and reading.

  These two independent phase change cells are configured to obtain a two voltage-pulse (Vt) diagram for state conversion operation in zero mode or direct overwrite mode.

  In one embodiment, two independent phase change cells employ one or two different phase change materials. In other embodiments, the material of the heating electrode and the contact area of the electrode is varied to adjust the current density to control the heating efficiency. In one embodiment, the heating layer is formed between the electrode and each phase change layer to improve heating efficiency. In other embodiments, the thickness of the phase change layer and the bottom electrode (metal thermal conduction layer) is adjusted to control the thermal radiation efficiency. For example, when a material having a low resistance in the crystalline state is used, a heating layer is formed or the contact area of the electrode is reduced to improve the heating efficiency. In one embodiment, if the material requires a faster critical cooling rate, this is accomplished by reducing the thickness of the phase change layer or increasing the thickness of the bottom electrode.

  Reference is made to FIG. 9 showing the serial structure of the phase change layer of the present invention. In this embodiment, the phase change layer includes a first phase change layer 110, a second phase change layer 120, an intermediate layer 130, a first electrode 141, and a second electrode 142. The first phase change layer 110 and the second phase change layer 120 are formed on the two surfaces of the intermediate layer 130 by a semiconductor process. The first electrode 141 is formed on the other side of the first phase change layer 110 by a semiconductor process. The second electrode 142 is formed on the other side of the second phase change layer 120 by a semiconductor process.

  In another embodiment, the protective layer 150 covers and protects the first phase change layer 110, the second phase change layer 120, the intermediate layer 130, the first electrode 141, and the second electrode 142. In addition, it is formed of a dielectric material by a semiconductor process. The first electrode 141 and the second electrode 142 supply a voltage or current signal so that the first phase change layer 110 and the second phase change layer 120 are heated and change state via an electrical signal. Thereby controlling the operation of the phase change memory in accordance with the present invention.

  Reference is made to FIG. 10 where the main structure of the phase change memory is the same as that of the embodiment of FIG. Optionally, the first functional layer 161 and the second functional layer 162 are between the first electrode 141 and the first phase change layer 110 and between the second electrode 142 and the second phase change layer 120. It is formed. The material of the first functional layer 161 and the second functional layer 162 is poly-Si or SiC. In one embodiment, the first functional layer 161 and the second functional layer 162 may be heating layers for improving heating efficiency. In one embodiment, the first functional layer 161 and the second functional layer 162 may be a nucleation acceleration layer for accelerating the crystallization speed of the first phase change layer. In other embodiments, the first functional layer 161 and the second functional layer 162 may be diffusion stop layers for preventing diffusion between the first phase change layer and the first electrode. The first functional layer 161 and the second functional layer 162 may have one, two, or all of the listed functions according to material properties.

  The area of the first functional layer 161 may be the same as or different from the area of the electrode, and may be the same as or different from the area of the phase change layer. Similarly, the area of the second functional layer 162 may be the same as or different from the area of the electrode, and may be the same as or different from the area of the phase change layer. The first functional layer 161 and the second functional layer 162 may be the same or different. The illustrated embodiment is merely exemplary and explanatory, and is not intended to limit the area and thickness of the first functional layer 161 and the second functional layer 162. In one embodiment, optionally, a first functional layer 161 or a second functional layer 162 is disposed.

  In accordance with the principles of the present invention, two phase change layers are used and connected in series to form a single memory cell. Each phase change layer has a crystalline state and an amorphous state and can be changed by heating.

  First phase change layer 110 has a crystalline state and an amorphous state, and second phase change layer 120 also has a crystalline state and an amorphous state. Thus, when two phase change layers are connected in series, four states are formed. These four states are hereinafter referred to as a first state, a second state, a third state, and a fourth state. The conditions for these four states are described as follows.

  The first phase change layer 110 has a first characteristic curve having a current-time relationship including a crystalline state and an amorphous state, and the second phase change layer 120 includes a current- It has a second characteristic curve related to time. First phase change layer 110 and second phase change layer 120 are configured in series. The first and second characteristic curves intersect each other to form a first state, a second state, a third state, and a fourth state. In the first state, the first phase change layer 110 and the second phase change layer are in a crystalline state, while in the second state, the first phase change layer 110 is in an amorphous state, The phase change layer 120 is in a crystalline state. In the third state, the first phase change layer 110 is in a crystalline state and the second phase change layer 120 is in an amorphous state, while in the fourth state, the first phase change layer 110 and the first phase change layer 110 are in the amorphous state. The two phase change layers 120 are in an amorphous state.

  The first phase change layer 110 and the second phase change layer 120 are different materials for phase change, preferably have different characteristics, and have a resistance difference. The properties of these two materials are opposite. In addition, the crystallization and amorphization rates of first phase change layer 110 and second phase change layer 120 are preferably different. For example, one of these layers can use a material with characteristics of low resistance, high crystallization temperature, and fast crystallization rate, while the other layer has high resistance, low crystallization temperature, and slower crystallization. A material having the characteristics of the conversion rate can be used. In one embodiment, the materials of first phase change layer 110 and second phase change layer 120 are different. In other embodiments, the two layers can use the same phase change material. The technical effect of the four memory states can be achieved by forming two single phase change cells in series via an optimized structure design.

  For example, the first phase change layer 110 may use doped eutectic SbTe, AgInSbTe, or GeInSbTe. The second phase change layer 120 may use a GeSbTe compound such as Ge2Sb2Te5. The foregoing materials are merely illustrative and are not intended to limit the composition of the present invention. Two phase change layers with different resistance change and crystallization / amorphization rate, change the composition of the phase change layer, adjust the thickness of the phase change layer, distinguish the top electrode type and contact area, or phase change It is obtained by forming a functional layer between the layer and the top electrode.

  The intermediate layer 130 can employ a material having a stable structure having good electrical and thermal conductivity. For example, the material is a metal nitride, metal carbide, or metal silicide.

  The materials of the first electrode 141 and the second electrode 142 may be the same or different. In one embodiment, the material of the first electrode 141 and the second electrode 142 may be the same to simplify the manufacturing process. The heating efficiency is controlled by adjusting the size of the electrode. In one embodiment, the size of the first electrode 141 and the second electrode 142 may be the same. In other embodiments, the sizes of the first electrode 141 and the second electrode 142 may be different. The size of the electrode is adjusted to control the heating efficiency.

  In one embodiment, the provided phase change memory selects a cell to be written or read via a transistor such as a MOSFET or BJT. Sufficient heat for the phase change of the first phase change layer 110 and the second phase change layer 120 is generated by applying a voltage to the heater or to the first electrode 141 and the second electrode 142. Is done. Next, the signal is sent to the receiving end and the sense amplifier through the electrodes. In accordance with the principles of the present invention, the operation of the multi-level phase change memory is controlled by the applied voltage and the applied time.

  Reference is made to FIGS. 12A to 12I which illustrate the fabrication process of a phase change memory according to the present invention.

  The substrate 1100 on which the metal contact 1101 is formed is provided by the previous CMOS or bipolar manufacturing process. Next, as shown in FIG. 12A, an oxide layer 1102 is deposited on the substrate 1100.

  Through holes are formed by masking and etching processes. The first electrode 1110 is formed in the through hole as shown in FIG. 12B. Next, as shown in FIG. 12C, the first phase change layer 1120, the intermediate layer 1130, and the second phase change layer 1140 are sequentially formed.

  Next, as shown in FIG. 12D, an oxide layer 1150 is formed. Other through holes are formed by a masking process and an etching process. As shown in FIG. 12E, a second electrode 1160 is formed in the through hole.

  As described in the above embodiment, the first functional layer is further formed between the first electrode 1110 and the first phase change layer 1120, and the second functional layer is Further formed between the second electrode 1150 and the second phase change layer 1140.

  The operation of the phase change memory according to the present invention is shown as follows. Please refer to FIG. 13A and FIG. 13D.

  The phase change memory according to the present invention uses a current drive mode during operation. The first phase change layer 111 and the second phase change layer 112 are heated by applying different currents on the first electrode 141 and the second electrode 142. Next, the first phase change layer 111 and the second phase change layer 112 generate 0, 1, or 2 amorphous volumes depending on their material properties. In the present invention, the 2 amorphous volume is called the second state, the 1 amorphous volume is called the 3rd state and the 4th state, and the 0 amorphous volume is called the 1st state. Schematic views of all states are shown in FIGS. 13A to 13D. A phase change layer having an amorphous volume has the highest resistance. Therefore, the series resistance in the second state is the highest, the third state is the second, the fourth state is the third highest, and the resistance in the first state is the lowest. The four resistance levels correspond to four memory states, thereby achieving four memory states.

  In accordance with the principles of the present invention, the physical parameters of the materials of the first phase change layer 111 and the second phase change layer 112 are estimated as shown in Table IV, where the first material is the first phase change layer. While applied to the change layer 111, a second material is applied to the second phase change layer 112 or vice versa.

  The materials listed below are exemplary and illustrative and are not intended to limit the materials of the phase change memory of the present invention. Thus, those skilled in the art can obtain a phase change memory having four memory states through the selection of appropriate materials.

It is assumed that the amorphous volume of the first material and the second material are the same. The ratio of thickness to crystallization area is 1: 9. The size of the heating electrode is the same. The total resistance for each state is estimated as follows.
<First state>
The first phase change layer and the second phase change layer are crystallized.
R1 = (5 × 10 ⁻³ ) × 10 + [(1 × 10 ⁻² ) × 10] to 0.15
<Second state>
The first phase change layer crystallizes and the second phase change layer becomes amorphous.
R2 = [50 × 1 + (5 × 10 ⁻³ ) × 9] + [(1 × 10 ⁻² ) × 10] to 50
<Third state>
The first phase change layer becomes amorphous and the second phase change layer crystallizes.
R3 = [(5 × 10 ⁻³ ) × 10] + [100 × 1 + (1 × 10 ⁻² ) × 9] -100
<Fourth state>
The first phase change layer and the second phase change layer become amorphous.
R4 = [50 × 1 + (5 × 10 ⁻³ ) × 9] + [100 × 1 + (1 × 10 ⁻² ) × 9] to 150

  From the above estimation, the total resistance is determined by the resistance of the amorphized region. Thus, the memory state is determined by reading the memory voltage.

  Reference is made to FIGS. 13A-13D of the characteristic curves for the conditions listed above. Regions I, II, III and IV in the drawing can be obtained by selecting an appropriate material or adjusting the size of the structure.

A current pulse test of a single phase change cell is performed on the first material and the second material. Amorphization and crystallization conditions can be obtained by modulating (changing) the current (I) and time (t). The crystallized cell is used for the amorphization test, while the written cell is used for the crystallization test. These test results are shown in an It diagram having an amorphized region, a crystallized region, and an ablation region. The amorphous region and the crystallized region are adjusted so as not to overlap entirely by adjusting the structural parameters of the memory cell. Thus, there are a plurality of corresponding relationships according to different phase change materials. For example, a higher crystallization temperature corresponds to a higher bottom edge of the crystallization region, a higher melting point corresponds to a higher bottom edge of the amorphous region, and a faster crystallization rate corresponds to the crystallization region and the amorphous region. Corresponds to the front edge of the conversion area.
When the two memories are connected in series and the current pulse (I, t) enters the overlapping amorphized region (area IV), each phase change layer has an amorphous volume. If the current pulse (I, t) enters the amorphized region of the first material and does not overlap with the amorphized region of the second material (area III), the first phase change layer has an amorphous volume. However, the second phase change layer does not work. If the current pulse (I, t) enters the amorphized region of the second material and does not overlap with the amorphized region of the first material (area II), only the second phase change layer generates an amorphous volume. However, the first phase change layer melts and cools down smoothly, and then crystallizes. When the current pulse (I, t) enters the overlapping crystallization region (area I), the two phase change layers crystallize, regardless of their state.

  Different first and second materials are selected for testing by appropriately adjusting the structural parameters. The obtained results are shown in FIGS. 13A to 13D. From the results shown in these figures, four memory states formed by two phase change layers are obtained.

  In accordance with the principles of the present invention, two methods can be employed for operation of the phase change memory when transitioning to different memory states.

  These two methods are hereinafter referred to as zero mode and direct overwrite mode. The memory state (second, third, and fourth states) is zero for zero mode operation, ie, the first state (the first phase change layer and the second phase change layer are crystallized). Is converted to another memory state. This operation is performed as follows.

  Two stage operation is used in zero mode operation. For the state conversion, the first pulse is generated by the first phase change layer and the second phase change layer such that the first phase change layer and the second phase change layer are crystallized to return to the first state. To be applied. A second pulse is then applied to change the crystals of the first phase change layer and the second phase change layer according to the memory state.

  The detailed operation will be described below with reference to FIG.

  The Y axis in FIG. 14 indicates the read voltage, and represents the first state, the second state, the third state, and the fourth state in order from the highest. The direction of the arrow represents a control signal for different memory states. In accordance with the principles of the present invention, the energy for each memory state is different. Therefore, four control signals are required according to the resistance of each state. These signals correspond to the first state, the second state, the third state, and the fourth state, respectively, a first control signal, a second control signal, a third control signal, And the fourth control signal.

  When the first control signal is applied, the first phase change layer and the second phase change layer are in a crystalline state (first state). When the second control signal is applied, these layers are in the second state. When the third control signal is applied, these layers are in the third state. When the fourth control signal is applied, these layers are in the fourth state.

  As shown in FIG. 14, when converted from the third state to the second state, the first control signal is first applied so that the cell is in the first state, and then the second The control signal is applied so that the cell is in the second state. In other embodiments, when converting from the fourth state to the second state, the first control signal is first applied such that the cell is in the first state, and then the fourth control. The signal is applied so that the cell is in the fourth state. Thus, in zero mode operation, two signals are required to change the memory state. The first pulse is applied to bring the state back to zero, and the second pulse is applied to bring the cell to the desired state. Thereafter, the pulse and the control signal are preferably voltage signals.

  In accordance with the principles of the present invention, there are few control signals for zero mode. It is easier to operate and there is no problem of incomplete crystallization of the amorphous volume.

  In other embodiments, the method is a direct overwrite mode. The aforementioned zero operation is not necessary for the direct override mode during state conversion. Similarly, four control signals listed in Table VI are required.

  When the first control signal is applied, the first phase change layer and the second phase change layer are in a crystalline state (first state). When the second control signal is applied, these layers are in the second state. When the third control signal is applied, these layers are in the third state. When the fourth control signal is applied, these layers are in the fourth state.

  As shown in FIG. 15, when converting from the third state to the second state, only the second control signal is applied. In another embodiment, when converting from the second state to the fourth state, only the fourth control signal is applied. Therefore, in the direct overwrite mode, only one pulse is necessary for state conversion. Thereafter, the pulse and the control signal are preferably voltage signals.

  This direct overwrite mode has the advantage of shortening the conversion time, and the original memory state need not be detected first before conversion.

  In accordance with aspects and principles of the present invention, a multi-level memory cell is comprised of two independent single phase change cells connected in series, with the same drive current (read voltage) for different write and read resistance levels. Is used.

  Two independent phase change cells are configured to obtain two current-pulse (It) diagrams for state conversion operations in zero mode or direct overwrite mode.

  Thus, while the invention has been described, it is clear that the invention can be modified in many ways. Such modifications should not be considered as departing from the spirit and scope of the present invention, and all such modifications that are obvious to those skilled in the art are included within the scope of the following claims. Intended.

It is a parallel structure figure of the phase change memory of 1st Embodiment according to this invention. It is another parallel structure figure of the phase change memory of 2nd Embodiment according to this invention. 2 illustrates a manufacturing process of a phase change memory according to the present invention. 2 illustrates a manufacturing process of a phase change memory according to the present invention. 2 illustrates a manufacturing process of a phase change memory according to the present invention. 2 illustrates a manufacturing process of a phase change memory according to the present invention. 2 illustrates a manufacturing process of a phase change memory according to the present invention. 2 illustrates a manufacturing process of a phase change memory according to the present invention. 2 illustrates a manufacturing process of a phase change memory according to the present invention. 2 illustrates a manufacturing process of a phase change memory according to the present invention. 2 illustrates a manufacturing process of a phase change memory according to the present invention. 6 illustrates another manufacturing process of a phase change memory according to the present invention. 6 illustrates another manufacturing process of a phase change memory according to the present invention. 6 illustrates another manufacturing process of a phase change memory according to the present invention. 6 illustrates another manufacturing process of a phase change memory according to the present invention. 6 illustrates another manufacturing process of a phase change memory according to the present invention. 6 illustrates another manufacturing process of a phase change memory according to the present invention. 6 illustrates another manufacturing process of a phase change memory according to the present invention. FIG. 6 is an explanatory diagram of four memory states of a phase change memory according to the present invention. FIG. 6 is an explanatory diagram of four memory states of a phase change memory according to the present invention. FIG. 6 is an explanatory diagram of four memory states of a phase change memory according to the present invention. FIG. 6 is an explanatory diagram of four memory states of a phase change memory according to the present invention. FIG. 6 is a characteristic diagram of four memory states of a phase change memory according to the present invention. FIG. 6 is a characteristic diagram of four memory states of a phase change memory according to the present invention. FIG. 6 is a characteristic diagram of four memory states of a phase change memory according to the present invention. FIG. 6 is a characteristic diagram of four memory states of a phase change memory according to the present invention. 6 illustrates an operation for memory state conversion of a phase change memory according to the present invention. 6 illustrates an operation for memory state conversion of a phase change memory according to the present invention. 2 is a serial structure diagram of a phase change memory according to the present invention; FIG. FIG. 5 is another serial structure diagram of a phase change memory according to the present invention. 2 illustrates a manufacturing process of a phase change memory according to the present invention. 2 illustrates a manufacturing process of a phase change memory according to the present invention. 2 illustrates a manufacturing process of a phase change memory according to the present invention. 2 illustrates a manufacturing process of a phase change memory according to the present invention. 2 illustrates a manufacturing process of a phase change memory according to the present invention. FIG. 6 is an explanatory diagram of four memory states of a phase change memory according to the present invention. FIG. 6 is an explanatory diagram of four memory states of a phase change memory according to the present invention. FIG. 6 is an explanatory diagram of four memory states of a phase change memory according to the present invention. FIG. 6 is an explanatory diagram of four memory states of a phase change memory according to the present invention. FIG. 6 is an experimental diagram of four memory states of a phase change memory according to the present invention. FIG. 6 is an experimental diagram of four memory states of a phase change memory according to the present invention. FIG. 6 is an experimental diagram of four memory states of a phase change memory according to the present invention. FIG. 6 is an experimental diagram of four memory states of a phase change memory according to the present invention. 2 illustrates an operation method for memory state conversion of a phase change memory according to the present invention; 2 illustrates an operation method for memory state conversion of a phase change memory according to the present invention;

Claims (49)

Phase change memory,
A first phase change layer having a first characteristic curve of current-time relationship including at least a crystalline state and an amorphous state;
A second phase change layer having a second characteristic curve of current-time relationship including at least a crystalline state and an amorphous state;
The first and second characteristic curves intersect each other to form a first state, a second state, a third state, and a fourth state, and in the first state, the first phase change layer And the second phase change layer is in a crystalline state, and in the second state, the first phase change layer is in an amorphous state, the second phase change layer is in a crystalline state, and in the third state, A phase change memory in which one phase change layer is in a crystalline state, a second phase change layer is in an amorphous state, and in the fourth state, the first phase change layer and the second phase change layer are in an amorphous state . The memory of claim 1, wherein the material of the first phase change layer and the second phase change layer is the same. The memory of claim 1, wherein the first phase change layer and the second phase change layer are made of different materials. Phase change memory,
A first phase change layer having a crystalline state and an amorphous state;
A second phase change layer having a crystalline state and an amorphous state;
Formed on one surface of the first phase change layer and the second phase change layer in order to change the states of the first phase change layer and the second phase change layer by supplying an electric signal; A first top electrode and a second top electrode;
A phase change memory comprising: a first phase change layer and at least one bottom electrode formed on another surface of the second phase change layer. The memory of claim 4, wherein the material of the first phase change layer and the second phase change layer is the same. The memory of claim 4, wherein a material of the first phase change layer and the second phase change layer is different. The memory according to claim 4, wherein the materials of the first top electrode and the second top electrode are the same. The memory according to claim 4, wherein materials of the first top electrode and the second top electrode are different. The memory according to claim 4, wherein a contact area between the first top electrode and the first phase change layer is the same as a contact area between the second top electrode and the second phase change layer. The memory according to claim 4, wherein a contact area between the first top electrode and the first phase change layer is different from a contact area between the second top electrode and the second phase change layer. The memory according to claim 4, wherein the bottom electrode is composed of one electrode connected to the first phase change layer and the second phase change layer. The memory according to claim 4, comprising two electrodes respectively connected to the first phase change layer and the second phase change layer. The memory of claim 12, wherein the materials of the two bottom electrodes are the same. The memory of claim 12, wherein the materials of the two bottom electrodes are different. The memory according to claim 4, further comprising a functional layer formed between the first top electrode and the first phase change layer. The functional layer includes a heating layer for improving heating efficiency, a nucleation acceleration layer for accelerating the crystallization speed of the first phase change layer, and a gap between the first phase change layer and the first top electrode. The memory of claim 15, wherein the memory is one or any combination of diffusion stop layers to prevent diffusion in the memory. The memory according to claim 4, further comprising a functional layer formed between the second top electrode and the first phase change layer. The functional layer includes a heating layer for improving the heating efficiency, a nucleation acceleration layer for accelerating the crystallization speed of the second phase change layer, and a space between the first phase change layer and the second top electrode. The memory of claim 17, wherein the memory is one or any combination of diffusion stop layers to prevent diffusion in the memory. A manufacturing method for manufacturing a phase change memory, comprising:
Providing a substrate having metal contacts formed therein;
Forming a bottom electrode on the substrate;
Forming a phase change layer on the bottom electrode;
Implanting ions into a portion of the phase change layer to form a first phase change layer and a second phase change layer;
Forming a first top electrode and a second top electrode on the corresponding first phase change layer and second phase change layer. The method of claim 19, further comprising the step of etching the bottom electrode and the phase change layer. The manufacturing method according to claim 19, wherein the ion implanting element is one selected from the group consisting of a group IIIA, a group IVA, a group VA, a group VIA, and a rare earth transition metal. The method of claim 19, further comprising the step of etching the first phase change layer and the second phase change layer to separate the first phase change layer and the second phase change layer. The functional layer is formed before forming the first top electrode, and the functional layer is a heating layer for improving the heating efficiency, and nucleation acceleration for accelerating the crystallization speed of the first phase change layer. 20. The fabrication of claim 19, wherein the layer is one of or any combination of diffusion stop layers to prevent diffusion between the first phase change layer and the first top electrode. Method. The functional layer is formed before forming the second top electrode, and the functional layer includes a heating layer for improving heating efficiency, and a nucleation acceleration for accelerating the crystallization speed of the second phase change layer. 20. The fabrication of claim 19, wherein the layer is one of a diffusion stop layer to prevent diffusion between the second phase change layer and the second top electrode, or any combination thereof. Method. A manufacturing method for manufacturing a phase change memory, comprising:
Providing a substrate having metal contacts formed therein;
Forming a bottom electrode on the substrate;
Forming a first phase change layer and a second phase change layer on the bottom electrode;
Forming a first top electrode and a second top electrode on the corresponding first phase change layer and second phase change layer. The functional layer is formed before forming the first top electrode, and the functional layer is a heating layer for improving the heating efficiency, and nucleation acceleration for accelerating the crystallization speed of the first phase change layer. 26. The fabrication of claim 25, wherein the layer is one of or any combination of diffusion stop layers to prevent diffusion between the first phase change layer and the first top electrode. Method. The functional layer is formed before forming the second top electrode, and the functional layer includes a heating layer for improving heating efficiency, and a nucleation acceleration for accelerating the crystallization speed of the second phase change layer. 26. The fabrication of claim 25, wherein the layer is one of or any combination of diffusion stop layers to prevent diffusion between the second phase change layer and the second top electrode. Method. A phase change memory state conversion method according to claim 4,
Applying a first pulse to crystallize the first phase change layer and the second phase change layer;
Applying a second pulse to change the crystal states of the first phase change layer and the second phase change layer. A phase change memory state conversion method according to claim 4,
A state conversion method comprising a step of applying a pulse to change the crystal states of the first phase change layer and the second phase change layer. Phase change memory,
A first phase change layer;
A second phase change layer;
An intermediate layer formed between the first phase change layer and the second phase change layer;
A first electrode formed on the other side of the first phase change layer;
And a second electrode formed on the other side of the second phase change layer. 32. The memory of claim 30, wherein the material of the first phase change layer and the second phase change layer is the same. 32. The memory of claim 30, wherein the materials of the first phase change layer and the second phase change layer are different. The memory of claim 30, wherein the material of the first electrode and the second electrode is the same. 32. The memory of claim 30, wherein the material of the first electrode and the second electrode is different. 32. The memory of claim 30, wherein a contact area between the first electrode and the first phase change layer is the same as a contact area between the second electrode and the second phase change layer. 32. The memory of claim 30, wherein a contact area between the first electrode and the first phase change layer is different from a contact area between the second electrode and the second phase change layer. 32. The memory of claim 30, further comprising a first functional layer formed between the first electrode and the first phase change layer. The first functional layer includes a heating layer for improving heating efficiency, a nucleation promoting layer for accelerating the crystallization speed of the first phase change layer, and the first phase change layer and the first electrode. 38. The memory of claim 37, wherein the memory is one or any combination of diffusion stop layers to prevent diffusion between. 32. The memory of claim 30, further comprising a second functional layer formed between the second electrode and the second phase change layer. The second functional layer includes a heating layer for improving heating efficiency, a nucleation acceleration layer for accelerating the crystallization speed of the second phase change layer, a second phase change layer, a second electrode, 40. The memory of claim 39, wherein the memory is one or any combination of diffusion stop layers to prevent diffusion between. A manufacturing method for manufacturing a phase change memory, comprising:
Providing a substrate having metal contacts formed therein;
Forming a first electrode on a substrate;
Forming a first phase change layer and sequentially forming an intermediate layer and a second phase change layer on the first electrode;
Forming a second electrode on the second phase change layer. 42. The manufacturing method according to claim 41, further comprising forming a first functional layer on the first electrode. 42. The method according to claim 41, further comprising forming a second functional layer on the second phase change layer. The first functional layer is formed before the first electrode is formed, and the first functional layer accelerates the crystallization speed of the heating layer and the first phase change layer for improving the heating efficiency. 42. A nucleation accelerating layer for the first and a diffusion stop layer for preventing diffusion between the first phase change layer and the first electrode, or any combination thereof. The manufacturing method as described in. The second functional layer is formed before the second electrode is formed, and the second functional layer accelerates the crystallization speed of the heating layer and the second phase change layer for improving the heating efficiency. 43. A nucleation accelerating layer for and a diffusion stop layer for preventing diffusion between the second phase change layer and the second electrode, or any combination thereof. The manufacturing method as described in. 42. The method of claim 41, further comprising forming an oxide layer before forming the first electrode. 42. The method of claim 41, further comprising forming an oxide layer before forming the second electrode. A state change method for a phase change memory comprising at least a first phase change layer and a second phase change layer, each of these layers comprising at least a crystalline state and an amorphous state so that four memory states are formed And the method comprises:
Applying a first pulse that is a voltage signal to crystallize the first phase change layer and the second phase change layer;
Applying a second pulse as a voltage signal to change the crystal states of the first phase change layer and the second phase change layer. A state change method for a phase change memory comprising at least a first phase change layer and a second phase change layer, each of these layers comprising at least a crystalline state and an amorphous state so that four memory states are formed And the method comprises:
A state conversion method comprising a step of changing a crystal state of a first phase change layer and a second phase change layer by applying a pulse which is a voltage signal.

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