JPWO2005031752A1 - Multilevel memory and recording method for phase change recording medium therefor - Google Patents

Abstract

By controlling the number of electric pulses applied to the phase change recording medium, the stepwise change in the resistance value is controlled to record multi-value information according to the difference in resistance value. The electrical pulse changes the resistance value stepwise by the first application means for changing the phase change recording medium from the high resistance state to the low resistance state and the second application means for changing from the low resistance state to the high resistance state. . Then, from the comparison difference between the recorded information and the information to be written, an electric pulse necessary for changing to the information to be written is selected and the number of times of application is calculated. According to the present invention, a multi-value memory having a simple circuit configuration and suitable for high integration is provided.

Description

  The present invention relates to a method for recording multilevel information on a phase change recording medium using a phase change material, and a multilevel memory using a nonvolatile multilevel information recording medium to which the method is applied.

In recent years, as the advanced information society progresses, the demand for large-capacity memory devices continues to increase, and high integration and high performance are required.
The realization of a large-capacity memory device is roughly classified into a method of miniaturizing the device itself and a method of giving a plurality of information to one device (multi-valued). However, since there is a limit to miniaturization of the element itself, a method for recording multi-value information on the element is desired.
As a means for recording a plurality of information in one element, a phase change type information recording medium using a phase change material can be mentioned.
For the phase change material, an alloy mainly composed of a so-called chalcogen-based material is used. The resistivity in the amorphous state with low conductivity (high resistance) and the resistivity in the crystalline state with high conductivity (low resistance). Since there is a large difference, the logic values “0” and “1” are assigned to the respective states (resistance values) and used as recording elements.
Such a phase change type information recording medium is described in US Pat. No. 5,536,947 (Patent Document 1) as realizing multi-value recording, that is, information recording of binary values of “0” and “1”. There is a way.
In Patent Document 1, the current value applied at the time of rewriting of the recording element is controlled so that the resistance value of the recording element takes a resistance value between the high resistance state and the low resistance state, and the multi-value is increased. Is to be realized.
An example of a circuit configuration for realizing rewriting of a recording element described in Patent Document 1 is shown in FIG. Reference numeral 101 denotes a word line, and 102 denotes a bit line. One end of the recording element 104 and the bit line 102 are connected via a selection transistor 110. The other end of the recording element 104 is connected to the constant voltage source 103. The bit line 102 is connected to a switch circuit unit 106 that controls the rewrite current of the recording element 104. The switch circuit unit 106 includes a plurality of write switches 107 and erase switches 108 and a read switch 109. By combining a plurality of write and erase switches 107 and 108, the rewrite current value is controlled. The resistance value of the selected recording element 104 is output as information by driving the read switch 109 and inputting the current flowing through the recording element 104 to the amplification / comparison unit 105. In some cases, the potential of the ground potential and the potential of the constant voltage source 103 are reversed.
In the rewriting method described in Patent Document 1, since a large number of switches 107 and 108 must be prepared for rewriting one recording element 104, a large number of parts are required, resulting in an increase in cost. Will be invited. Furthermore, the occupied area of the switch circuit unit 106 increases with the heavy use of the switches 107 and 108, which is against high integration.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and to provide a recording method on a phase change recording medium that has a simple circuit configuration and is suitable for high integration, and a multi-value memory using the same. To do.
The features of this multi-level memory and its main effects are as follows.
(1) A multilevel memory according to the present invention includes a memory element that stores information of three or more values according to a difference in resistance value of a phase change recording medium, and a predetermined electric pulse applied to the memory element a plurality of times to store information. A rewrite control circuit for rewriting and a read control circuit for reading information by energizing the memory element are provided.
According to the present invention, the resistance value of the phase-change recording medium can be changed in a stepwise manner not by the magnitude (current value) of the energy pulse but by the number of times the electric pulse is applied, corresponding to the difference in resistance value. Thus, multi-value information can be stored by assigning each information.
(2) In a preferred aspect of the multi-value memory according to the present invention, on the premise of the invention of (1), the rewrite control circuit applies an electric pulse for changing the resistance value of the phase change recording medium to a high resistance. It is characterized by comprising first application means and second application means for applying an electric pulse for changing the resistance value of the phase change recording medium to a low resistance.
According to the present invention, the resistance value of the memory element can be reversibly changed from a high resistance to a low resistance or from a low resistance to a high resistance by an applied electric pulse. The first application means can be changed from low resistance to high resistance, and the second application means can be changed from high resistance to low resistance.
(3) A preferred aspect of the multi-level memory of the present invention is based on the invention of (2) above, and the rewrite control circuit compares the information read by the read control circuit with the information to be written; And means for selecting the first application means or the second application means based on the comparison result of the comparison means, and means for calculating the number of times of applying the electric pulse based on the comparison result. .
According to the present invention, first, the information read by the reading control circuit is compared with the information to be written, and the electric pulse to be applied is selected according to the magnitude of the corresponding resistance value of both. When the information to be written is high resistance, the first application means is selected, and when the information is low resistance, the second application means is selected. Then, the number of application times of the electric pulse necessary to reach the resistance value corresponding to the information to be written is determined from the difference between the two resistance values.
The method of the present invention has the following features.
(4) A first method of the present invention is a method for stepwise decreasing the resistance value of an amorphous phase change recording medium, and the electric pulse of (a) below is applied to the phase change recording medium. The resistance value of the phase change recording medium is lowered stepwise according to the number of times of applying the electric pulse.
(A) The phase change recording medium does not transition to a complete crystal state by only one application to the phase change recording medium in the amorphous state, and the transition to the crystal state is not performed by multiple applications. An electrical pulse with a pulse voltage and / or pulse width selected to progress in stages.
(5) The electrical pulse (a) is an electrical pulse having a pulse voltage and / or a pulse width smaller than that of the electrical pulse (A) below.
(A) An electric pulse that takes a value when the phase change recording medium is completely crystallized by one application and the resistance value of the medium is crystallized.
(6) The second method of the present invention is a method for stepwise increasing the resistance value of the phase change recording medium in the crystalline state, and applying the electric pulse of (b) below to the phase change recording medium. The resistance value of the phase change recording medium is increased stepwise according to the number of times of application of the electric pulse.
(B) The phase-change recording medium does not transition to a completely amorphous state by only one application to the phase-change recording medium in the crystalline state. An electric pulse having a pulse voltage and / or a pulse width selected so that the transition of each proceeds stepwise with each application.
(7) The electric pulse of (b) is an electric pulse having a pulse width smaller than that of the electric pulse of (B) below.
(B) An electric pulse having the energy that the phase change recording medium is completely amorphized by one application.
Changing the resistance value of the phase change recording medium stepwise (decrease or increase) means that information is written and rewritten by the type of the step including the original step.

FIG. 1 is a conceptual explanatory diagram of a phase change recording medium used in the present invention.
FIG. 2 is a circuit configuration diagram according to the embodiment of the present invention.
FIG. 3 is a schematic cross-sectional view relating to the memory element structure.
FIG. 4 is a process flow diagram relating to the rewrite process.
FIG. 5 is a graph showing the resistance change of the phase change recording medium according to the embodiment of the present invention.
FIG. 6 is a circuit configuration diagram of a conventional multilevel memory.
Reference numerals in the drawings indicate the following. DESCRIPTION OF SYMBOLS 1; Word line, 2; Bit line, 3; Constant voltage source, 4; Memory element, 5; Amplification / comparison part, 6; Switch circuit part, 7; Write switch, 8; Erase switch, 9; Selection transistor 101; word line 102; bit line 103; constant voltage source 104; recording element 105; amplification / comparison unit 106; switch circuit sound unit 107; write switch 108; erase switch 109; readout switch, 110; selection transistor

Hereinafter, the present invention will be described in detail based on embodiments shown in the accompanying drawings. The embodiments described below are preferable specific examples for carrying out the present invention, and thus various technical limitations are made. However, the present invention is particularly limited in the following description. Unless otherwise specified, the present invention is not limited to these forms.
FIG. 1 is a diagram for explaining the concept of the present invention. In FIG. 1A, the vertical axis represents the resistance value of the phase change recording medium, and the horizontal axis represents the number of electric pulses applied. In FIG. 1B, the voltage of the electric pulse applied on the vertical axis is taken, and the time is taken on the horizontal axis.
When an electric pulse as shown in FIG. 1B is applied to an amorphous phase change recording medium, the resistance value of the phase change recording medium changes stepwise as shown in FIG. It becomes like this.
As described above, the first method according to the present invention is to reduce the resistance value of the phase change recording medium to three or more levels by an electric pulse.
Such a phenomenon is explained as follows.
When the phase change recording medium is in an amorphous state, it is in a high resistance state. In this state, when the temperature of the phase change recording medium is not lower than the crystallization temperature and not higher than the melting point and is maintained for a certain period of time, the crystal changes to a low resistance crystal state. Therefore, the phase change recording medium in an amorphous state can be obtained by applying an electric pulse that provides energy for generating a quantity of heat so that the temperature of the phase change recording medium is higher than the crystallization temperature and lower than the melting point (preferably lower than the melting point). The medium can be transitioned to the crystalline state.
Such an electric pulse is called a set pulse, and is determined by a predetermined pulse voltage and a pulse width (time) depending on conditions such as the material of the phase change recording medium and the structure of the memory element. This set pulse is the electric pulse (A) referred to in (5) above.
The set pulse varies depending on the material of the phase change recording medium and the structure of the memory element, and is not limited. However, as an example of a general-purpose range, the pulse voltage is preferably 0.1 to 10 (V), preferably the illustrated 1 to 3 (V) is, as the pulse width ^{1nsec~1msec (1 × 10- 9 ~1 ×} 10- 3 ( s)), preferably ^{50nsec~1μsec (5 × 10- 8 ~1 ×} 10 ^-6 (seconds)).
However, when an electric pulse having a pulse voltage and / or pulse width smaller than that of the set pulse is applied to the phase change recording medium in the amorphous state, a sufficient amount of heat is not generated, so that the transition to the complete crystal state does not occur. A crystalline state and a crystalline state are partially mixed.
Such an electric pulse is referred to as a small set pulse, and this small set pulse is the electric pulse (a) referred to in (4) above. When a small set pulse is applied only once to a phase change recording medium in an amorphous state, the resistance value slightly decreases by the amount of transition to the crystalline state, and then, by applying a small set pulse, the crystal The amount of transition to the state increases and the resistance value further decreases. That is, as shown in FIG. 1, the resistance value decreases step by step in accordance with the number of small set pulse applications.
After the phase change recording medium is completely crystallized, the resistance value does not decrease any further even if a small set pulse is further applied. In this case, the interval between the small set pulses may be set to a time interval such that the influence of heat by the previous small set pulse is eliminated.
Similarly to the set pulse, the small set pulse is not limited because it differs depending on the material of the phase change recording medium and the structure of the memory element. However, as an example, the pulse voltage is 0.1 to 5 (V). And preferably 0.5 to 3 (V), and the pulse width is 1 nsec to 0.5 msec (1 × 10 ^{−9 to} 5 × 10 ⁻⁴ (second)), preferably 50 nsec to 1 μsec (5 × 10 5). ^-8 to 1 × 10 ⁻⁶ (seconds)).
From these ranges, a pulse voltage and / or a pulse width may be appropriately selected so as to function preferably as a small set pulse so as to be smaller than the set pulse value.
In addition, the second method according to the present invention is to increase the resistance value of the phase change recording medium to three or more levels by an electric pulse. This is explained as follows.
When the phase change recording medium is in a crystalline state, it is in a low resistance state. In this state, if the temperature of the phase change recording medium is heated to a melting point or higher (preferably a temperature exceeding the melting point) and then rapidly cooled, the phase change recording medium transitions to a high resistance amorphous state. At this time, if the cooling rate is low, the memory element is crystallized. Therefore, the phase change type recording medium in the crystalline state can be transitioned to the amorphous state by applying an electric pulse that gives energy for generating an amount of heat that makes the memory element equal to or higher than the melting point with a reduced pulse width. .
Such an electric pulse is called a reset pulse, and is determined by a predetermined pulse voltage and a pulse width (time) depending on conditions such as the material of the phase change recording medium and the structure of the memory element. This reset pulse is the electric pulse (B) referred to in (7) above.
Similarly to the set pulse, the reset pulse is not limited because it varies depending on the material of the phase change recording medium and the structure of the memory element. However, as an example, the pulse voltage is preferably 1 to 15 (V), preferably is 1 to 7 (V), as the pulse width ^{0.1nsec~10msec (1 × 10 -10 ~1 ×} 10 -2 ( sec)), preferably ^{1nsec~1μsec (1 × 10 -9 ~1 ×} 10 - ⁶ (seconds)).
When an electric pulse having a pulse voltage or a pulse width smaller than the reset pulse is applied to the phase change recording medium in the crystalline state, a sufficient amount of heat is not generated, so that the amorphous state does not completely shift to the amorphous state. The state and the crystalline state are partially mixed.
Such an electric pulse is referred to as a small reset pulse, and this small reset pulse is the electric pulse of (b) referred to in (6) above. When a small reset pulse is applied only once to a crystalline phase change recording medium, the resistance value slightly rises by the transition to the amorphous state. The resistance value further increases by the amount of transition to the crystalline state. That is, contrary to the case of FIG. 1, the resistance value increases stepwise according to the number of times of applying the small reset pulse.
After the phase change recording medium is completely in an amorphous state, the resistance value does not increase any more even if a small reset pulse is further applied.
Similarly to the set pulse, the small reset pulse is not limited because it differs depending on the material of the phase change recording medium, the structure of the memory element, etc. For example, the pulse voltage is preferably 1 to 10 (V), preferably Is 1 to 5 (V), and the pulse width is 0.1 nsec to 1 msec (1 × 10 ⁻¹⁰ to 1 × 10 ⁻³ (second), preferably 1 nsec to 100 nsec (1 × 10 ⁻⁹ to 1 × 10 ^−7). (Seconds)).
From these ranges, an appropriate selection may be made so that the pulse width is smaller than the reset pulse so that it preferably functions as a small reset pulse.
As described above, the resistance value of the phase change recording medium can be changed in a plurality of stages according to the number of times of applying the small set pulse or the small reset pulse applied to the phase change recording medium. A memory element using a medium can have information of three or more values due to a difference in resistance value.
Examples of the phase change recording medium used in the present invention include an alloy mainly composed of a chalcogen (chalcogenide) material described in Patent Document 1.
Examples of more specific material compositions are given below.
(A) A material containing Te, for example, Ge _x Sb _y Te _z , where x + y + z = 100, x is 5 atomic% or more, y is 5 atomic% or more, and z is 5 atomic% or more.
Atomic% is the ratio of the number of atoms of the constituent element.
(B) As an additive to the material of (a), Na, Mg, Al, P, S, Ca, Ga, As, Se, Cd, In, Sn, I, Cs, Ta, Re, Hg, Pb , Ag, W, Mo, Pt, Co, Ni, Si, Au, Cu, Fe, Bi, and a material containing one or more elements selected from Mn.
(C) A material containing Te, for example, Ge _x Bi _y Te _z , where x + y + z = 100, x is 5 atomic% or more, y is 5 atomic% or more, and z is 5 atomic% or more.
(D) In addition to the material of (c) above, Na, Mg, Al, P, S, Ca, Ga, As, Se, Cd, In, Sn, I, Cs, Ta, Re, Hg, Pb , Ag, W, Mo, Pt, Co, Ni, Si, Au, Cu, Fe, and a material containing one or more elements selected from Mn.
(E) A material containing Te, for example, Ge _x Cu _y Te _z , where x + y + z = 100, x is 5 atomic% or more, y is 5 atomic% or more, and z is 5 atomic% or more.
(F) As an additive to the material of (e), Na, Mg, Al, P, S, Ca, Ga, As, Se, Cd, In, Sn, I, Cs, Ta, Re, Hg, Pb , Ag, W, Mo, Pt, Co, Ni, Si, Au, Fe, Bi, and a material containing one or more elements selected from Mn.
(G) A material containing Te, for example, Se _x Sb _y Te _z , where x + y + z = 100, x is 5 atomic% or more, y is 5 atomic% or more, and z is 5 atomic% or more.
(H) As an additive to the material of (g), Na, Mg, Al, P, S, Ca, Ga, As, Cd, In, Sn, I, Cs, Ta, Re, Hg, Pb, Ag A material containing one or more elements selected from W, Mo, Pt, Co, Ni, Si, Au, Cu, Fe, Bi, and Mn.
(I) A material containing Te, for example, As _X Sb _y Te _z , where x + y + z = 100, x is 5 atomic% or more, y is 5 atomic% or more, and z is 5 atomic% or more.
(J) In addition to the material of (i), Na, Mg, Al, P, S, Ca, Ga, Se, Cd, In, Sn, I, Cs, Ta, Re, Hg, Pb, Ag A material containing one or more elements selected from W, Mo, Pt, Co, Ni, Si, Au, Cu, Fe, Bi, and Mn.
The shape of the phase change recording medium is not limited, but from the viewpoint of effectively applying a small set pulse and a small reset pulse, the thickness of the phase change recording medium disposed between the applied electrodes (= interelectrode distance) Is about 1 nm to 1 μm, particularly 10 nm to 200 nm.
A method for forming the phase change recording medium layer as described above is not limited, and a known film formation method may be used. From the viewpoint of a device formation process, sputtering, flash vapor deposition, and the like are preferable. Can be mentioned.
FIG. 2 shows a circuit configuration according to the embodiment of the present invention. In FIG. 2, 1 is a word line, 2 is a bit line, and one end of the memory element 4 and the bit line 2 are connected via a selection transistor 10. The other end of the memory element 4 is connected to the constant voltage source 3. The bit line 2 is connected to a switch circuit unit 6 that controls a rewrite energy pulse of the memory element 4. The switch circuit unit 6 includes a write switch 7 and an erase switch 8 that are rewrite control circuits, and a read switch 9 that is a read control circuit. Since this circuit configuration is equivalent to the existing binary information recording switch circuit configuration, it is not necessary to newly design a circuit configuration for the switch circuit unit 6 of the present invention. Also, the ground potential and the potential of the constant voltage source 3 can be set in reverse.
When the write switch 7 which is the first application means is driven, a small set pulse can be applied, and when the erase switch 8 which is the second application means is driven, a small reset pulse can be applied. By applying a small set pulse or a small reset pulse to the memory element 4 and changing the resistance value of the memory element 4 in a plurality of stages, one memory element 4 can have information of three or more values. The resistance value of the selected memory element 4 is output as information by driving the read switch 9 and inputting the current flowing through the memory element 4 to the amplifying / comparing unit 5.
FIG. 3 shows a cross-sectional structure of the memory element 4 and the selection transistor 10. In the silicon substrate 20, a diffusion layer 22 is formed in a well portion 21, and an oxide film 23 is laminated on the upper surface thereof. A source electrode 24, a drain electrode 25, and a gate electrode 26 are formed on the upper surface of the oxide film 23. The source electrode 24 and the drain electrode 25 penetrate the oxide film 23 and are electrically connected to the diffusion layer 22, respectively. Yes. As described above, the selection transistor 10 is configured as a MOS-FET.
The source electrode 24 is electrically connected to a wiring 27 corresponding to the bit line 2, and the gate electrode 26 is electrically connected to a wiring 28 corresponding to the word line 1. The memory element 4 has a structure in which a phase change recording medium layer 29 made of a chalcogenide-based material is sandwiched between an upper electrode 30 and a lower electrode 31, and the lower electrode 31 includes a via 31a and a metal layer 31b. Since the via 31a is made of a refractory metal, even when the phase change of the phase change recording medium layer 29 is changed, it is not deformed or altered. Further, since the via 3a can make the contact area with the phase change recording medium layer 29 smaller than that of the metal layer 31b, the volume of the phase change portion of the phase change recording medium layer 29 can be reduced. The set current or reset current can be reduced. The metal layer 31b can be formed at the same time when the bit line 51 is formed. The via 31a is electrically connected to the drain electrode 25.
As shown in FIG. 3, since the phase change recording medium layer 29 can be formed on the selection transistor 10, there is almost no area newly required for forming the phase change recording medium layer 29. The mounting area can be reduced. Further, the upper and lower electrodes 30 and 31 sandwiching the phase change recording medium layer 29 also have a function as a heat radiation (cooling) plate after the pulse application. The use of a chalcogenide-based material has a high affinity with a normal CMOS process, and can be applied as a memory unit such as a system-on-chip (SOC).
FIG. 4 shows a processing flow for writing information to the memory element 4. When the rewrite process is started, the write information (Rw) is read (S100). Next, the read switch 9 is driven, the memory element 4 is energized, and the record information (Rm) corresponding to the resistance value is read (S101). Then, Rw and Rm are compared (S102). If Rw is larger, the number of small reset pulses applied is calculated from the difference between the two (S103), and the erase switch 8 is driven by the calculated number of applications. (S104) and the process ends. If Rw is not large, it is checked whether both are equal (S105). If Rw is smaller than Rm, the number of small set pulse applications is calculated from the difference between the two (S106), the write switch 7 is driven for the calculated number of applications (S107), and the process ends.
On the other hand, a switch that applies a set pulse that is completely crystallized by one application and a reset pulse that is completely amorphous by one application may be added. By combining these, the rewriting speed can be further increased.

FIG. 5 shows a change in resistance value when a small set pulse is applied to the memory element 4 in the circuit configuration shown in FIG. In FIG. 5, the vertical axis represents the resistance value of the memory element 4, and the horizontal axis represents the number of small set pulse applications.
The resistance value was measured every time a small set pulse was applied to the memory element 4 in the amorphous state, and a total of 6 small set pulses were applied. The pulse voltage of the small set pulse (voltage of the constant voltage source 3) was 2.7 V, and the pulse width was 500 ns (nanoseconds). Similar to the concept shown in FIG. 1, FIG. 5 shows a state in which the resistance value of the memory element 4 decreases stepwise each time a small set pulse is applied. By assigning an information value to each of the resistance values in a plurality of stages, one element can be given information of two or more values. In FIG. 5, 7-value information can be provided. Note that the power supply voltage, pulse width, and pulse interval of the energy pulse applied to the memory element 4 strongly depend on the material used for the memory element 4 and its element structure.
INDUSTRIAL APPLICABILITY According to the present invention, the stepwise change in the resistance value of the phase change recording medium can be controlled by the number of electric pulses applied, that is, the digital value. As the electric pulse, rewriting control can be performed with two kinds of electric pulses of the first applying means and the second applying means, and the circuit configuration is the same as that in the case of conventional binary information rewriting control. Therefore, unlike the conventional multi-value information recording method, it is not necessary to prepare a plurality of switches for the purpose of changing the magnitude (current value) of the energy pulse. Therefore, it is possible to record multi-value information with a circuit area and the number of parts comparable to those of a conventional binary information recording memory. Furthermore, since the circuit configuration of the switch circuit unit used in the memory using the conventional phase change type information recording medium for recording binary information can be used, there is no need for a significant design change.
In the present invention, the electrical pulse is selected based on the comparison result between the information read by the reading control circuit and the information to be written, and the number of times of application is determined. Can be changed. Therefore, an increase in power consumption can be suppressed even when recording multi-value information.
From the above, the present invention can record multi-value information with a circuit configuration as simple as a conventional binary information recording memory, that is, multi-value suitable for high integration. Memory can be provided.
This application is based on Japanese Patent Application No. 2003-335133 filed in Japan, the contents of which are incorporated in full herein.

Claims (7)

A memory element that stores information of three or more values due to a difference in resistance value of a phase change recording medium, a rewrite control circuit that rewrites information by applying a predetermined electrical pulse to the memory element a plurality of times, and energizing the memory element And a reading control circuit for reading information. The rewrite control circuit applies a first applying means for applying an electric pulse for changing the resistance value of the phase change recording medium to a high resistance, and an electric pulse for changing the resistance value of the phase change recording medium to a low resistance. The multi-value memory according to claim 1, further comprising a second applying means. The rewrite control circuit includes a comparison unit that compares information read by the read control circuit with information to be written, and a unit that selects the first application unit or the second application unit based on a comparison result of the comparison unit. The multi-value memory according to claim 2, further comprising: means for calculating the number of application times of the electric pulse based on the comparison result. A method of gradually reducing the resistance value of an amorphous phase change recording medium, wherein the phase change recording is performed by applying the electrical pulse of (a) below to the phase change recording medium a plurality of times. The method according to claim 1, wherein the resistance value of the medium is decreased stepwise in accordance with the number of times the electric pulse is applied.
(A) The phase change recording medium does not transition to a complete crystal state by only one application to the phase change recording medium in the amorphous state, and the transition to the crystal state is not performed by multiple applications. An electrical pulse with a pulse voltage and / or pulse width selected to progress in stages. 5. The method according to claim 4, wherein the electric pulse (a) is an electric pulse having a pulse voltage and / or a pulse width smaller than that of the electric pulse (A) below.
(A) An electric pulse that takes a value when the phase change recording medium is completely crystallized by one application and the resistance value of the medium is crystallized. A method of stepwise increasing the resistance value of a phase change recording medium in a crystalline state by applying an electric pulse of (b) below to the phase change recording medium, The method is characterized in that it is raised stepwise according to the number of times of application of the electric pulse.
(B) The phase change recording medium does not transition to a completely amorphous state by only one application to the phase change recording medium in the crystalline state. An electric pulse whose pulse voltage and / or pulse width is selected so that the transition proceeds stepwise with each application. The method according to claim 6, wherein the electric pulse of (b) is an electric pulse having a pulse width smaller than that of the electric pulse of (B) below.
(B) An electric pulse having the energy that the phase change recording medium is completely amorphized by one application.

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