WO2005031752A1

WO2005031752A1 - Multinary memory and method for recording to phase-change type recording medium for it

Info

Publication number: WO2005031752A1
Application number: PCT/JP2004/014450
Authority: WO
Inventors: Kazuya Nakayama; Akio Kitagawa
Original assignee: Kanazawa University Technology Licensing Organization Ltd.
Priority date: 2003-09-26
Filing date: 2004-09-24
Publication date: 2005-04-07
Also published as: JPWO2005031752A1

Abstract

By controlling the number of times electric pulse is applied to a phase-change type recording medium so as to control the stepwise change of the resistance value, multinary information is recorded according to the difference in resistance values. The electric pulse stepwise changes its resistance value by the first application means for changing the phase-change type recording medium from a high resistance state to a low resistance state and second application means for changing it from the low resistance state to the high resistance state. According to a difference between the information which has been recorded and the information to be recorded, an electric pulse required for changing to the information to be written is selected and its number of application times is calculated. The present invention provides a multinary memory appropriate for a simple circuit configuration with high integration.

Description

Specification

Multi-valued memory and method for recording on phase change recording medium therefor

Technical field

The present invention relates to a method for recording multilevel information on a phase change recording medium using a phase change material, and a multilevel memory using a nonvolatile multilevel information recording medium to which the method is applied.

Background art

In recent years, with the advance of the information-oriented society, the demand for large-capacity memory devices continues to increase, and high integration and high performance are required.

The realization of large-capacity memory devices can be broadly classified into a method of miniaturizing the device itself and a method of providing multiple information in one device (multi-valued). However, there is a limit to the miniaturization of the device itself, and a method of recording multi-value information on the device is desired.

As a means for recording a plurality of pieces of information in one element, there is a phase change type information recording medium using a phase change material.

As the phase change material, an alloy containing a so-called chalcogen-based material as a main component is used. The resistivity of the amorphous state with low conductivity (high resistance) and the resistance of the crystalline state with high conductivity (low resistance) are used. Since there is a large difference in the rates, each state (resistance) is assigned a logical value of “0” or “1” and used as a recording element.

In such a phase change type information recording medium, U.S. Pat.No. 5,533,694,771 (Patent No. 1) discloses a multi-valued recording medium, that is, recording of two or more values of "0" and "1". There is a method described in literature 1).

In Patent Document 1, by controlling the current value applied at the time of rewriting of the recording element, the resistance value of the recording element is set to a resistance value between a high resistance state and a low resistance state. Is to be realized.

FIG. 6 shows an example of a circuit configuration for realizing rewriting of a recording element described in Patent Document 1. 101 indicates a word line, 102 indicates a bit line, and one end of the recording element 104 is connected to the bit line 102 via the selection transistor 110. It is. The other end of the recording element 104 is connected to a constant voltage source 103. The bit line 102 is connected to a switch circuit 106 that controls the rewrite current of the recording element 104. The switch circuit section 106 includes a plurality of write switches 107, an erase switch 108, and a read switch 109. The current value for rewriting is controlled by combining a plurality of writing and erasing switches 107 and 108. The resistance value of the selected recording element 104 is output as information by driving the readout switch 109 and inputting the current flowing through the recording element 104 to the width comparator 105. The ground potential and the constant voltage source 103 potential may have opposite potential levels.

In the rewriting method described in Patent Document 1, a large number of switches 107 and 108 must be prepared for rewriting one recording element 104, so that many parts are required. This leads to an increase in cost. Furthermore, the occupation area of the switch circuit section 106 increases with the frequent use of the switches 107 and 108, which is against high integration.

Disclosure of the invention

An object of the present invention is to solve the above-mentioned problems, and to provide a recording method for a phase-change recording medium which has a simple circuit configuration and is suitable for high integration, and a multi-valued memory using the same. And

The features of the multi-level memory of this effort are as follows. (1) A multi-valued memory according to the present invention includes a memory element that stores three or more values of information due to a difference in resistance value of a phase change recording medium, and a predetermined electric pulse applied to the memory element a plurality of times to store information. A rewrite control circuit for rewriting; and a read control circuit for reading information by energizing the memory element.

According to the present invention, the resistance value of the phase change recording medium can be changed stepwise according to the number of times the electric pulse is applied instead of the magnitude (current value) of the energy pulse. It is possible to store multi-valued information by allocating information correspondingly. (2) In a preferred embodiment of the multi-valued memory according to the present invention, based on the premise of the above (1), the self-rewriting control circuit is provided with an electric panel for changing the resistance value of the phase change recording medium to a high resistance. It is characterized by comprising a first applying means for applying, and a second applying means for applying an electric pulse for changing a resistance value of the phase change type recording medium to a low resistance.

According to the disclosure, the resistance value of the memory element can be reversibly changed from high resistance to low resistance or from low resistance to high resistance by the applied electric pulse. The first application means can change from low resistance to resistance, and the second application means can change from high resistance to low resistance.

(3) In a preferred aspect of the multi-valued memory according to the present invention, based on the premise of the above (2), the rewriting control circuit includes a comparing unit that compares information read by the read control circuit with information to be written. A means for selecting the first application means or the previous IB second application means based on the comparison result of the comparison means; and a means for calculating the number of times of application of the electric pulse based on the comparison result. And

According to this description, first, the information read by the read control circuit and the information to be written are compared, and the electric pulse to be applied is selected according to the magnitude of the resistance value corresponding to both. If the information to be written has a high resistance, the first application means is selected, and if the information to be written has a low resistance, the second application means is selected. Then, from the difference between the two resistance values, the number of times of application of the electric pulse necessary until the resistance value corresponding to the information to be written is determined.

The method of the present invention has the following features.

(4) The first method of the present invention is a method of gradually lowering the resistance value of an amorphous phase-change recording medium, wherein the following electric pulse (a) is applied to the phase-change recording medium. By applying a plurality of times to the medium, the resistance value of the phase change type recording medium is reduced stepwise according to the number of times of application of the electric pulse.

(a) A single application to an amorphous phase-change recording medium does not cause the phase-change recording medium to transition to a completely crystalline state, An electrical pulse in which the pulse voltage and Z or pulse width are selected so that the transition to the state proceeds in steps.

(5) The electric pulse of (a) is an electric pulse having a smaller pulse voltage and / or a smaller pulse width than the electric pulse of (A) below.

(A) An electric pulse whose phase change type recording medium is completely crystallized by one application and whose resistance value becomes the value when the medium is crystallized.

(6) The second method of the present invention is a method of gradually increasing the resistance value of a crystalline phase change type recording medium, and applying the following electric pulse (b) to the phase change type recording medium. In addition, the resistance value of the phase change recording medium is stepwise increased in accordance with the number of times of application of the electric pulse.

(b) A single application to a crystalline phase-change recording medium does not cause the phase-change recording medium to transition to a completely amorphous state, but to an amorphous state by multiple applications. An electrical pulse with a pulse voltage and / or pulse width selected so that the transition to 進行 progresses step by step with each application.

(7) The electric pulse in (b) above is an electric pulse with a smaller pulse width than the electric pulse in (B) below.

(B) An electric pulse having energy to completely amorphize a phase change recording medium by one application.

Changing the resistance value of the variable-gap recording medium stepwise (decreasing, increasing) means writing and rewriting information only in the type of the step including the original step.

Brief Description of Drawings

FIG. 1 is a conceptual explanatory diagram of a phase change recording medium used in the present invention.

FIG. 2 is a circuit configuration diagram according to the embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view related to a memory element structure.

FIG. 4 is a processing flow diagram relating to the rewriting process.

m5 is a graph showing a resistance change of the phase change recording medium according to the embodiment of the present invention. FIG. 6 is a circuit configuration diagram of a conventional multilevel memory.

The reference numerals in the drawings indicate the following, respectively. 1; word line, 2; bit line, 3; constant voltage source, 4; memory element, 5; amplification / comparison section, 6; switch circuit section, 7; write switch, 8; erase switch, 9; read switch, '10: Selection transistor, 101: Lead line, 102: Bit line, 103: Constant voltage source, 104: Recording element, 105: Amplification / comparison unit, 106: Switch times Path β, 107: Write switch, 108: Erase switch, 109: Read switch, 110: Select transistor

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the present invention will be described in detail based on embodiments shown in the accompanying drawings. The embodiment described below is a preferred specific example for carrying out the present invention, and thus various technical limitations are made. However, the present invention particularly limits the present invention in the following description. It is not limited to these forms unless otherwise specified.

FIG. 1 is a diagram illustrating the concept of the present invention. In Fig. 1 (a), the vertical axis shows the resistance value of the phase-change type recording medium, and the horizontal axis shows the number of electric pulses applied. In Fig. 1 (b), the vertical axis indicates the voltage of the applied electric pulse, and the horizontal axis indicates time. When an electric pulse as shown in Fig. 1 (b) is applied to an amorphous phase-change recording medium, the resistance of the phase-change recording medium changes stepwise as shown in Fig. 1 (a). It becomes like.

As described above, the first method according to the present invention is to lower the resistance value of the phase change recording medium to three or more levels by the electric pulse.

These phenomena are explained as follows.

When the subject change type recording medium is in an amorphous state, it is in a high resistance state. In this state, if the temperature of the phase change recording medium is maintained at a temperature equal to or higher than the crystallization temperature and equal to or lower than the melting point, and is maintained for a certain period of time or more, a transition to a low-resistance crystal state occurs. Therefore, the temperature of the phase-change recording medium should be higher than the crystallization temperature and lower than the melting point (preferably the melting point). By applying an electric pulse that provides energy for generating a calorific value that causes the amorphous phase change recording medium to transition to the crystalline state. Such an electric pulse is called a set pulse, and is determined by a predetermined pulse voltage and a predetermined pulse width (time) according to conditions such as the material of the phase change recording medium and the structure of the memory element. This set pulse is the electric pulse of (A) described in (5) above.

The set pulse varies depending on the material of the phase-change recording medium and the structure of the memory element, and is not limited. However, as an example of a general-purpose range, the pulse voltage is 0.1 to 10 (V), preferably exemplified 1 to 3 (V) is, as the pulse width 1 n sec~ 1 msec (1 X 1 0- 9 ~ 1 X 1 0- 3 ( s)), preferably 5 0 n sec ~ 1 sec (5 X 1 0- 8 ~ 1 X 1 0- 6 ( s)) are exemplified.

However, when an electric panel with a pulse voltage Z or a pulse width smaller than the set pulse is applied to the amorphous phase-change recording medium, sufficient heat is not generated, and the crystal does not transition to the perfect crystalline state. Thus, the amorphous state and the crystalline state are in a mixed state.

Such an electric pulse is referred to as a small set pulse, and this small set pulse is the electric pulse of (a) referred to in the above (4). When a small set pulse is applied only once to an amorphous phase-change recording medium, the resistance value drops slightly by the transition to the crystalline state, and by subsequently applying the small set pulse, The amount of transition to the crystalline state increases and the resistance value further decreases. That is, as shown in FIG. 1, the resistance value decreases stepwise according to the number of times of application of the / J ヽ set pulse. After the recording medium is completely crystallized, the resistance value does not decrease any further even if a small set pulse is further applied. In this case, the interval between the small set pulses should be such that the heat effect of the previous small set pulse is eliminated.

Like the set pulse, the / j and the set pulse are also not limited because they differ depending on the material of the phase change type recording medium and the structure of the memory element, but, for example, the pulse voltage is 0.1 to 5 (V), preferably 0.5 to 3 (V), Panoresu 1 _{n S} is the width ec~0. 5 msec (1 X 1 0- 9 ~5 X 1 0- 4 ( s)), preferably 5 0 n sec~ 1 ^ sec ( 5 X 1 0- 8 ~ : LX 1 0 ⁶ (s)) of Ru is illustrated.

These range powers may be appropriately selected so that the pulse voltage or the pulse width is smaller than the set pulse value so as to preferably function as a small set pulse.

The second method according to the present invention is to increase the resistance value of the phase change recording medium to three or more levels by an electric pulse. This is explained as follows. When the phase change recording medium is in a crystalline state, it is in a low resistance state. In this state, if the phase-change recording medium is heated to a temperature equal to or higher than the melting point (preferably a temperature exceeding the melting point) and then rapidly cooled, the phase-change recording medium transitions to a high-resistance amorphous state. At this time, if the cooling rate is low, the memory element will crystallize. Therefore, the phase change recording medium in a crystalline state can be changed to an amorphous state by applying a pulse having a small pulse width to an electric pulse that provides energy for generating a heat quantity that causes the memory element to have a melting point or more. Can be.

Such an electric pulse is called a reset pulse, and is determined by a predetermined pulse voltage and a predetermined pulse width (time) depending on conditions such as the material of the phase change recording medium and the structure of the memory element. This reset pulse is the electric pulse of (B) referred to in the above (7). The reset pulse is also not limited as it is different depending on the material of the phase change type recording medium and the structure of the memory element as in the case of the set pulse, but, for example, the pulse voltage is 1 to 15 (V) , preferably 1 to 7 (V), is a pulse width 0. 1 n sec~l 0 msec ( 1 X 1 0- 1 .~ 1 X 1 0- 2 ( s)), preferably 1 n sec to 1 see (1 X 10 — ⁹ to 1 X 10 — ⁶ (seconds)) is exemplified.

When an electric pulse having a pulse voltage or a pulse width smaller than that of the reset pulse is applied to a phase change recording medium in a crystalline state, a sufficient amount of heat is not generated. The state is such that the state and the crystalline state are partly mixed.

Such an electric pulse is called a small reset pulse. _b.f3 This is the electric pulse of (b) in (6). When a small reset pulse is applied only once to a crystalline phase-change recording medium, the resistance slightly increases by the transition to the amorphous state, and the small reset pulse is subsequently applied. The resistance value is further increased by the transition to the amorphous state. That is, contrary to the case of FIG. 1, the resistance value increases stepwise according to the number of application of / J and the reset pulse. After the phase-change recording medium is completely in an amorphous state, the resistance value does not further increase even if a small reset pulse is further applied.

Like the set pulse, the small reset pulse is also not limited because it differs depending on the material of the phase change recording medium and the structure of the memory element, but is not limited to this. For example, the pulse voltage is 1 to 10 (V ), Preferably 1 to 5 (V), and the pulse width is 0.1 nsec to: L msec (1 X 10 0 to ^1. LX 10 to ³ (seconds), preferably 1 n sec to 1 0 0 n sec (1 X 1 0- 9 ~: LX 1 0- 7 ( s)) are exemplified.

From these ranges, the pulse width may be appropriately selected such that the pulse width is smaller than the reset pulse so as to function favorably as the small reset pulse.

As described above, the resistance value of the phase change recording medium can be changed in a plurality of steps according to the number of application of the small set pulse or the small reset pulse applied to the phase change type recording medium. A memory element using a recording medium can have three or more values of information due to a difference in resistance value.

Examples of the phase-change recording medium used in the present invention include an alloy mainly containing a chalcogen-based (chalcogenide-based) material described in Patent Document 1.

Examples of more specific material compositions are given below.

(A) a material containing Te, for example, a Ge _x Sb _y Te _z, when the x + y + z = 100, X is 5 atomic% or more, y is 5 atomic% or more, z is 5 atomic. /. More than that.

atomic% is the ratio of the number of atoms in the constituent elements.

(b) Addition of Na, Mg, Al, P, S, Ca, Ga, As,

One or more selected from Se, Cd, In, Sn, I, Cs, Ta, Re, Hg, Pb, Ag, W, Mo, Pt, Co, Ni, Si, Au, Cu, Fe, Bi, and Mn Materials containing elements. (c) A material containing Te, for example, Ge _x Bi _y Te _z , where x + y + z = 100, x is 5 atomic. /. Above, y is 5 atomic% or more, and z is 5 atomic ⁰ /. More than that.

(d) As an additive, Na, Mg, Al, P, S, Ca, Ga, As, Se, Cd, In, Sn, I, Cs, Ta, Re, Hg, Pb A material containing one or more elements selected from the group consisting of: Ag, Ag, Mo, Pt, Co, Ni, Si, Au, Cu, Fe, and Mn.

(e) When the material containing Te, for example, Ge _x Cu _y Te _z , and x + y + z = 100, X is 5 atomic. /. Above, y is 5 atomic% or more, z is 5 atomic%. /. More than that.

(f) As an additive, Na, Mg, Al, P, S, Ca, Ga, As, Se, Cd, In, Sn, I, Cs, Ta, Re, Hg, Pb A material containing one or more elements selected from the group consisting of: Ag, W, Mo, Pt, Co, Ni, Si, Au, Fe, Bi, and Mn.

(G) material containing Te, for example, a Se _x Sb _y Te _z, when the x + y + z = 100, X is 5 atomic% or more, y is 5 atomic% or more, z is 5 atomic% or more Stuff.

(h) As an additive, Na, Mg, Al, P, S, Ca, Ga, As, Cd, In, Sn, I, Cs, Ta, Re, Hg, Pb, Ag A material containing one or more elements selected from, W, Mo, Pt, Co, Ni, Si, Au, Cu, Fe, Bi, and Mn.

(I) material containing Te, for example, a As _x Sb _y Te _z, when the x + y + z = 100, X is 5 atomic% or more, y is 5 atomic% or more, z is 5 atomic. /. More than that.

(j) As an additive, Na, Mg, Al, P, S, Ca, Ga, Se, Cd, In, Sn, I, Cs, Ta, Re, Hg, Pb, Ag A material containing at least one element selected from the group consisting of, W, Mo, Pt, Co, Ni, Si, Au, Cu, Fe, Bi, and Mn.

Although the shape of the phase change recording medium is not limited, the thickness of the phase change recording medium disposed between the applied electrodes (= distance between the electrodes) is effective in applying the small set pulse and the small reset pulse. ) Is lnm ~: about Lzm, especially 10nm ~ 200nm is a preferable value.

The method for forming the phase-change recording medium layer as described above is not limited, and a known film forming method may be used. No. FIG. 2 shows a circuit configuration according to the embodiment of the present invention. In FIG. 2, 1 indicates a word line, 2 indicates a bit line, and one end of the memory element 4 and the bit line 2 are connected via a selection transistor 10. The other end of the memory element 4 is connected to the constant voltage source 3. The bit line 2 is connected to a switch circuit section 6 for controlling a rewriting energy pulse of the memory element 4. The switch circuit section 6 includes a write switch 7 and an erase switch 8 as a rewrite control circuit, and a read switch 9 as a read control circuit. Since this circuit configuration is equivalent to the existing switch circuit configuration for recording binary information, it is not necessary to newly design a circuit configuration for the switch circuit unit 6 of the present invention. Further, the ground potential and the potential of the constant voltage source 3 can be set to be opposite.

When the write switch 7 as the first application unit is driven, a small set pulse can be applied, and when the erase switch 8 as the second application unit is driven, a small reset pulse can be applied. By applying a small set pulse or a small reset pulse to the memory element 4 and changing the resistance value of the memory element 4 in a plurality of stages, one memory element 4 can have three or more values of information. The resistance value of the selected memory element 4 is output as information by driving the readout switch 9 and inputting the current flowing through the memory element 4 to the amplification Z comparison unit 5. FIG. 3 shows a cross-sectional structure of a memory element 4 and a selection transistor 10. A diffusion layer 22 is formed on a silicon substrate 20 in a well portion 21, and an oxide film 23 is laminated on the upper surface thereof. A source electrode 24, a drain electrode 25 and a gate electrode 26 are formed on the upper surface of the oxide film 23, and the source electrode 24 and the drain electrode 25 pass through the oxide film 23. Are electrically connected to the diffusion layers 22 respectively. As described above, the selection transistor 10 is configured as MOS-FET.

Source electrode 24 is electrically connected to wiring 27 corresponding to bit line 2, and gate electrode 26 is electrically connected to wiring 28 corresponding to word line 1. The memory element 4 is a phase-change recording medium layer made of a chalcogenide-based material. 29 has a structure sandwiched between an upper electrode 30 and a lower electrode 31. The lower electrode 31 includes a via 31 a and a metal layer 31. Since the via 31 a is made of a high-melting-point metal, it does not deform or change even when the phase change recording medium layer 29 changes phase. In addition, since the via 3a can have a smaller contact area with the phase change type recording medium layer 29 than the metal layer 31b, the volume of the phase change portion of the phase change type recording medium layer 29 must be reduced. Therefore, the set current or the reset current can be reduced. The 3 lb metal layer can be made at the same time that the bit line 51 is formed. Then, the via 31 a is electrically connected to the drain electrode 25.

As shown in FIG. 3, since the phase-change recording medium layer 29 can be formed above the selection transistor 10, almost no new area is required for forming the phase-change recording medium layer 29. Therefore, the mounting area can be reduced. The upper and lower electrodes 30, 31 sandwiching the phase change recording medium layer 29 also have a function as a heat radiation (cooling) plate after pulse application. The use of chalcogenide-based materials has a high affinity with ordinary CMOS processes, and can be applied to memory units such as system-on-chip (SOC).

FIG. 4 shows a processing flow for writing information to the memory element 4. When the rewriting process is started, the writing information (Rw) is read (S100). Next, the read switch 9 is driven to energize the memory element 4 and read the recorded information (Rm) corresponding to the resistance value (S101). Then, Rw and Rm are compared (S102). If Rw is larger, the number of application of the small reset pulse is calculated from the difference between the two (S103), and the number of application of the erase switch 8 is calculated. The minute drive control is performed (S104), and the process ends. If Rw is not large, it is checked whether they are equal (S105), and if they are equal, the process ends. If Rw is smaller than Rm, the number of application of the small set pulse is calculated from the difference between the two (S106), the write switch 7 is drive-controlled by the calculated number of application (S107), and the process ends. . On the other hand, a switch for applying a set pulse for completely crystallizing with one application and a reset pulse for completely amorphizing with one application may be added. Group these By combining them, the rewriting speed can be further increased.

Example

FIG. 5 shows a change in resistance value when a small set pulse is applied to the memory element 4 in the circuit configuration shown in FIG. In FIG. 5, the vertical axis represents the resistance value of the memory element 4, and the horizontal axis represents the number of small set pulse applications.

Each time a small set pulse is applied to the amorphous memory element 4, the resistance is measured.

A total of six small set pulses were applied. The pulse voltage of the small set pulse (the voltage of the constant voltage source 3) was 2.7 V, and the width of the panel was 500 ns (nanoseconds). Similar to the concept shown in FIG. 1, FIG. 5 shows that the resistance value of the memory element 4 gradually decreases each time a small set pulse is applied. By assigning an information value to each of the resistance values in the plurality of stages, one element can have two or more values of information. In FIG. 5, seven-value information can be provided. Note that the power supply voltage, pulse width, and pulse interval of the energy pulse applied to the memory element 4 strongly depend on the material used for the memory element 4 and its element structure.

Industrial applications

According to the present invention, the stepwise change in the resistance value of the phase change recording medium can be controlled by the number of times of application of the electric pulse, that is, the digital value. Rewriting control can be performed by using two types of electric pulses of the first applying means and the second applying means as the electric pulse, and the circuit configuration is the same as that of the conventional binary information rewriting control. For this reason, it is not necessary to prepare a plurality of switches for changing the magnitude (current value) of the energy pulse as in the conventional multi-value information recording method. Therefore, it is possible to record multi-valued information with a circuit area and the number of parts which are almost equal to those of a conventional memory for recording binary information. Further, since the circuit configuration of the switch circuit unit used for the memory using the conventional phase change type information recording medium for recording binary information can be used, there is no need for a significant design change.

Further, in the present invention, an electric pulse is selected and the number of application times is determined based on a comparison result between the information read by the read control circuit and the information to be written. Therefore, the resistance value can be changed with the minimum necessary number of times of application. Therefore, an increase in power consumption can be suppressed even when recording multilevel information.

From the above, according to the present invention, it is possible to record multi-valued information with a circuit configuration as simple as a conventional memory for recording binary information, that is, a multi-valued information suitable for high integration. Memory can be provided.

This application is based on a patent application No. 2003-335133 filed in Japan, the contents of which are incorporated in full herein.

Claims

The scope of the claims

1. A memory element that stores information of three or more values due to a difference in resistance value of a phase change recording medium, a rewriting control circuit that rewrites information by applying a predetermined electric pulse to the memory element a plurality of times, and the memory A multivalued memory comprising: a read control circuit that reads information by energizing an element.

2. The rewriting control circuit includes a first application unit that applies an electric pulse that changes the resistance value of the phase change recording medium to a high resistance, and an electric power that changes the resistance value of the phase change recording medium to a low resistance. 2. The multi-value memory according to claim 1, further comprising: a second application unit that applies a pulse.

3. The rewriting control circuit includes a comparing unit that compares information read by the reading control circuit with information to be written, and selects the first applying unit or the second applying unit based on a comparison result of the comparing unit. 3. The multi-valued memory according to claim 2, further comprising: means for calculating the number of times of application of the electric pulse based on the comparison result.

4. A method for gradually lowering the resistance of an amorphous phase-change recording medium, wherein the electric pulse of the following (a) is applied to the phase-change recording medium a plurality of times to obtain the phase change. The method according to claim 1, wherein the resistance value of the recording medium is reduced stepwise according to the number of times of application of the electric pulse.

(a) A single application to an amorphous phase-change recording medium does not cause the phase-change recording medium to transition to a completely crystalline state, but to a crystalline state by multiple applications. An electrical pulse in which the pulse voltage and z or pulse width are selected so that they progress in steps.

5. The method according to claim 4, wherein the electric pulse of (a) is an electric pulse having a smaller pulse voltage or a smaller pulse width than the electric pulse of (A) below.

6. A method for gradually increasing the resistance value of a phase-change recording medium in a crystalline state, (B) applying an electric pulse to a phase-change recording medium, and increasing a resistance value of the phase-change recording medium in a stepwise manner in accordance with the number of times of application of the electric pulse. The method.

(b) A single application to a crystalline phase-change recording medium does not cause the phase-change recording medium to transition to a completely amorphous state, but to an amorphous state by multiple applications. An electric pulse whose pulse voltage and pulse width or pulse width are selected so that the transition of each step progresses with each application.

7. The method according to claim 6, wherein the electric pulse in (b) is an electric pulse having a smaller pulse width than the electric pulse in (B) below.

(B) An electric pulse having energy to completely amorphize a phase change type recording medium by one application.