WO2005031752A1 - Memoire a multiniveaux et procede associe d'enregistrement sur support d'enregistrement de type a changement de phase - Google Patents

Memoire a multiniveaux et procede associe d'enregistrement sur support d'enregistrement de type a changement de phase Download PDF

Info

Publication number
WO2005031752A1
WO2005031752A1 PCT/JP2004/014450 JP2004014450W WO2005031752A1 WO 2005031752 A1 WO2005031752 A1 WO 2005031752A1 JP 2004014450 W JP2004014450 W JP 2004014450W WO 2005031752 A1 WO2005031752 A1 WO 2005031752A1
Authority
WO
WIPO (PCT)
Prior art keywords
recording medium
pulse
phase
electric pulse
change recording
Prior art date
Application number
PCT/JP2004/014450
Other languages
English (en)
Japanese (ja)
Inventor
Kazuya Nakayama
Akio Kitagawa
Original Assignee
Kanazawa University Technology Licensing Organization Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kanazawa University Technology Licensing Organization Ltd. filed Critical Kanazawa University Technology Licensing Organization Ltd.
Priority to JP2005514294A priority Critical patent/JPWO2005031752A1/ja
Publication of WO2005031752A1 publication Critical patent/WO2005031752A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells

Definitions

  • the present invention relates to a method for recording multilevel information on a phase change recording medium using a phase change material, and a multilevel memory using a nonvolatile multilevel information recording medium to which the method is applied.
  • the realization of large-capacity memory devices can be broadly classified into a method of miniaturizing the device itself and a method of providing multiple information in one device (multi-valued).
  • a method of miniaturizing the device itself there is a limit to the miniaturization of the device itself, and a method of recording multi-value information on the device is desired.
  • phase change type information recording medium using a phase change material.
  • phase change material an alloy containing a so-called chalcogen-based material as a main component is used.
  • the resistivity of the amorphous state with low conductivity (high resistance) and the resistance of the crystalline state with high conductivity (low resistance) are used. Since there is a large difference in the rates, each state (resistance) is assigned a logical value of “0” or “1” and used as a recording element.
  • Patent No. 1 discloses a multi-valued recording medium, that is, recording of two or more values of "0" and "1". There is a method described in literature 1).
  • Patent Document 1 by controlling the current value applied at the time of rewriting of the recording element, the resistance value of the recording element is set to a resistance value between a high resistance state and a low resistance state. Is to be realized.
  • FIG. 6 shows an example of a circuit configuration for realizing rewriting of a recording element described in Patent Document 1.
  • 101 indicates a word line
  • 102 indicates a bit line
  • one end of the recording element 104 is connected to the bit line 102 via the selection transistor 110. It is.
  • the other end of the recording element 104 is connected to a constant voltage source 103.
  • the bit line 102 is connected to a switch circuit 106 that controls the rewrite current of the recording element 104.
  • the switch circuit section 106 includes a plurality of write switches 107, an erase switch 108, and a read switch 109.
  • the current value for rewriting is controlled by combining a plurality of writing and erasing switches 107 and 108.
  • the resistance value of the selected recording element 104 is output as information by driving the readout switch 109 and inputting the current flowing through the recording element 104 to the width comparator 105.
  • the ground potential and the constant voltage source 103 potential may have opposite potential levels.
  • An object of the present invention is to solve the above-mentioned problems, and to provide a recording method for a phase-change recording medium which has a simple circuit configuration and is suitable for high integration, and a multi-valued memory using the same.
  • a multi-valued memory includes a memory element that stores three or more values of information due to a difference in resistance value of a phase change recording medium, and a predetermined electric pulse applied to the memory element a plurality of times to store information.
  • the resistance value of the phase change recording medium can be changed stepwise according to the number of times the electric pulse is applied instead of the magnitude (current value) of the energy pulse. It is possible to store multi-valued information by allocating information correspondingly.
  • the self-rewriting control circuit is provided with an electric panel for changing the resistance value of the phase change recording medium to a high resistance. It is characterized by comprising a first applying means for applying, and a second applying means for applying an electric pulse for changing a resistance value of the phase change type recording medium to a low resistance.
  • the resistance value of the memory element can be reversibly changed from high resistance to low resistance or from low resistance to high resistance by the applied electric pulse.
  • the first application means can change from low resistance to resistance
  • the second application means can change from high resistance to low resistance.
  • the rewriting control circuit includes a comparing unit that compares information read by the read control circuit with information to be written.
  • the information read by the read control circuit and the information to be written are compared, and the electric pulse to be applied is selected according to the magnitude of the resistance value corresponding to both. If the information to be written has a high resistance, the first application means is selected, and if the information to be written has a low resistance, the second application means is selected. Then, from the difference between the two resistance values, the number of times of application of the electric pulse necessary until the resistance value corresponding to the information to be written is determined.
  • the method of the present invention has the following features.
  • the first method of the present invention is a method of gradually lowering the resistance value of an amorphous phase-change recording medium, wherein the following electric pulse (a) is applied to the phase-change recording medium.
  • the resistance value of the phase change type recording medium is reduced stepwise according to the number of times of application of the electric pulse.
  • the electric pulse of (a) is an electric pulse having a smaller pulse voltage and / or a smaller pulse width than the electric pulse of (A) below.
  • the second method of the present invention is a method of gradually increasing the resistance value of a crystalline phase change type recording medium, and applying the following electric pulse (b) to the phase change type recording medium.
  • the resistance value of the phase change recording medium is stepwise increased in accordance with the number of times of application of the electric pulse.
  • a single application to a crystalline phase-change recording medium does not cause the phase-change recording medium to transition to a completely amorphous state, but to an amorphous state by multiple applications.
  • the electric pulse in (b) above is an electric pulse with a smaller pulse width than the electric pulse in (B) below.
  • Changing the resistance value of the variable-gap recording medium stepwise means writing and rewriting information only in the type of the step including the original step.
  • FIG. 1 is a conceptual explanatory diagram of a phase change recording medium used in the present invention.
  • FIG. 2 is a circuit configuration diagram according to the embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional view related to a memory element structure.
  • FIG. 4 is a processing flow diagram relating to the rewriting process.
  • FIG. 6 is a circuit configuration diagram of a conventional multilevel memory.
  • FIG. 1 is a diagram illustrating the concept of the present invention.
  • the vertical axis shows the resistance value of the phase-change type recording medium
  • the horizontal axis shows the number of electric pulses applied.
  • the vertical axis indicates the voltage of the applied electric pulse
  • the horizontal axis indicates time.
  • the first method according to the present invention is to lower the resistance value of the phase change recording medium to three or more levels by the electric pulse.
  • the subject change type recording medium When the subject change type recording medium is in an amorphous state, it is in a high resistance state. In this state, if the temperature of the phase change recording medium is maintained at a temperature equal to or higher than the crystallization temperature and equal to or lower than the melting point, and is maintained for a certain period of time or more, a transition to a low-resistance crystal state occurs. Therefore, the temperature of the phase-change recording medium should be higher than the crystallization temperature and lower than the melting point (preferably the melting point).
  • Such an electric pulse is called a set pulse, and is determined by a predetermined pulse voltage and a predetermined pulse width (time) according to conditions such as the material of the phase change recording medium and the structure of the memory element.
  • This set pulse is the electric pulse of (A) described in (5) above.
  • the set pulse varies depending on the material of the phase-change recording medium and the structure of the memory element, and is not limited.
  • the pulse voltage is 0.1 to 10 (V), preferably exemplified 1 to 3 (V) is, as the pulse width 1 n sec ⁇ 1 msec (1 X 1 0- 9 ⁇ 1 X 1 0- 3 ( s)), preferably 5 0 n sec ⁇ 1 sec (5 X 1 0- 8 ⁇ 1 X 1 0- 6 ( s)) are exemplified.
  • the amorphous phase-change recording medium when an electric panel with a pulse voltage Z or a pulse width smaller than the set pulse is applied to the amorphous phase-change recording medium, sufficient heat is not generated, and the crystal does not transition to the perfect crystalline state. Thus, the amorphous state and the crystalline state are in a mixed state.
  • Such an electric pulse is referred to as a small set pulse, and this small set pulse is the electric pulse of (a) referred to in the above (4).
  • a small set pulse is applied only once to an amorphous phase-change recording medium, the resistance value drops slightly by the transition to the crystalline state, and by subsequently applying the small set pulse, The amount of transition to the crystalline state increases and the resistance value further decreases. That is, as shown in FIG. 1, the resistance value decreases stepwise according to the number of times of application of the / J ⁇ set pulse. After the recording medium is completely crystallized, the resistance value does not decrease any further even if a small set pulse is further applied. In this case, the interval between the small set pulses should be such that the heat effect of the previous small set pulse is eliminated.
  • the / j and the set pulse are also not limited because they differ depending on the material of the phase change type recording medium and the structure of the memory element, but, for example, the pulse voltage is 0.1 to 5 (V), preferably 0.5 to 3 (V), Panoresu 1 n S is the width ec ⁇ 0. 5 msec (1 X 1 0- 9 ⁇ 5 X 1 0- 4 ( s)), preferably 5 0 n sec ⁇ 1 ⁇ sec ( 5 X 1 0- 8 ⁇ : LX 1 0 6 (s)) of Ru is illustrated.
  • These range powers may be appropriately selected so that the pulse voltage or the pulse width is smaller than the set pulse value so as to preferably function as a small set pulse.
  • the second method according to the present invention is to increase the resistance value of the phase change recording medium to three or more levels by an electric pulse. This is explained as follows. When the phase change recording medium is in a crystalline state, it is in a low resistance state. In this state, if the phase-change recording medium is heated to a temperature equal to or higher than the melting point (preferably a temperature exceeding the melting point) and then rapidly cooled, the phase-change recording medium transitions to a high-resistance amorphous state. At this time, if the cooling rate is low, the memory element will crystallize.
  • the phase change recording medium in a crystalline state can be changed to an amorphous state by applying a pulse having a small pulse width to an electric pulse that provides energy for generating a heat quantity that causes the memory element to have a melting point or more. Can be.
  • Such an electric pulse is called a reset pulse, and is determined by a predetermined pulse voltage and a predetermined pulse width (time) depending on conditions such as the material of the phase change recording medium and the structure of the memory element.
  • This reset pulse is the electric pulse of (B) referred to in the above (7).
  • the reset pulse is also not limited as it is different depending on the material of the phase change type recording medium and the structure of the memory element as in the case of the set pulse, but, for example, the pulse voltage is 1 to 15 (V) , preferably 1 to 7 (V), is a pulse width 0.
  • Such an electric pulse is called a small reset pulse.
  • _b.f3 This is the electric pulse of (b) in (6).
  • the resistance slightly increases by the transition to the amorphous state, and the small reset pulse is subsequently applied.
  • the resistance value is further increased by the transition to the amorphous state. That is, contrary to the case of FIG. 1, the resistance value increases stepwise according to the number of application of / J and the reset pulse. After the phase-change recording medium is completely in an amorphous state, the resistance value does not further increase even if a small reset pulse is further applied.
  • the small reset pulse is also not limited because it differs depending on the material of the phase change recording medium and the structure of the memory element, but is not limited to this.
  • the pulse voltage is 1 to 10 (V ), Preferably 1 to 5 (V), and the pulse width is 0.1 nsec to: L msec (1 X 10 0 to 1.
  • LX 10 to 3 (seconds), preferably 1 n sec to 1 0 0 n sec (1 X 1 0- 9 ⁇ : LX 1 0- 7 ( s)) are exemplified.
  • the pulse width may be appropriately selected such that the pulse width is smaller than the reset pulse so as to function favorably as the small reset pulse.
  • the resistance value of the phase change recording medium can be changed in a plurality of steps according to the number of application of the small set pulse or the small reset pulse applied to the phase change type recording medium.
  • a memory element using a recording medium can have three or more values of information due to a difference in resistance value.
  • phase-change recording medium used in the present invention examples include an alloy mainly containing a chalcogen-based (chalcogenide-based) material described in Patent Document 1.
  • (A) a material containing Te, for example, a Ge x Sb y Te z, when the x + y + z 100, X is 5 atomic% or more, y is 5 atomic% or more, z is 5 atomic. /. More than that.
  • atomic% is the ratio of the number of atoms in the constituent elements.
  • FIG. 2 shows a circuit configuration according to the embodiment of the present invention.
  • 1 indicates a word line
  • 2 indicates a bit line
  • one end of the memory element 4 and the bit line 2 are connected via a selection transistor 10.
  • the other end of the memory element 4 is connected to the constant voltage source 3.
  • the bit line 2 is connected to a switch circuit section 6 for controlling a rewriting energy pulse of the memory element 4.
  • the switch circuit section 6 includes a write switch 7 and an erase switch 8 as a rewrite control circuit, and a read switch 9 as a read control circuit. Since this circuit configuration is equivalent to the existing switch circuit configuration for recording binary information, it is not necessary to newly design a circuit configuration for the switch circuit unit 6 of the present invention. Further, the ground potential and the potential of the constant voltage source 3 can be set to be opposite.
  • FIG. 3 shows a cross-sectional structure of a memory element 4 and a selection transistor 10.
  • a diffusion layer 22 is formed on a silicon substrate 20 in a well portion 21, and an oxide film 23 is laminated on the upper surface thereof.
  • a source electrode 24, a drain electrode 25 and a gate electrode 26 are formed on the upper surface of the oxide film 23, and the source electrode 24 and the drain electrode 25 pass through the oxide film 23. Are electrically connected to the diffusion layers 22 respectively.
  • the selection transistor 10 is configured as MOS-FET.
  • Source electrode 24 is electrically connected to wiring 27 corresponding to bit line 2
  • gate electrode 26 is electrically connected to wiring 28 corresponding to word line 1.
  • the memory element 4 is a phase-change recording medium layer made of a chalcogenide-based material. 29 has a structure sandwiched between an upper electrode 30 and a lower electrode 31.
  • the lower electrode 31 includes a via 31 a and a metal layer 31. Since the via 31 a is made of a high-melting-point metal, it does not deform or change even when the phase change recording medium layer 29 changes phase. In addition, since the via 3a can have a smaller contact area with the phase change type recording medium layer 29 than the metal layer 31b, the volume of the phase change portion of the phase change type recording medium layer 29 must be reduced. Therefore, the set current or the reset current can be reduced.
  • the 3 lb metal layer can be made at the same time that the bit line 51 is formed. Then, the via 31 a is electrically connected to the drain electrode 25.
  • phase-change recording medium layer 29 can be formed above the selection transistor 10, almost no new area is required for forming the phase-change recording medium layer 29. Therefore, the mounting area can be reduced.
  • the upper and lower electrodes 30, 31 sandwiching the phase change recording medium layer 29 also have a function as a heat radiation (cooling) plate after pulse application.
  • the use of chalcogenide-based materials has a high affinity with ordinary CMOS processes, and can be applied to memory units such as system-on-chip (SOC).
  • FIG. 4 shows a processing flow for writing information to the memory element 4.
  • the writing information (Rw) is read (S100).
  • the read switch 9 is driven to energize the memory element 4 and read the recorded information (Rm) corresponding to the resistance value (S101).
  • Rw and Rm are compared (S102). If Rw is larger, the number of application of the small reset pulse is calculated from the difference between the two (S103), and the number of application of the erase switch 8 is calculated.
  • the minute drive control is performed (S104), and the process ends. If Rw is not large, it is checked whether they are equal (S105), and if they are equal, the process ends.
  • the number of application of the small set pulse is calculated from the difference between the two (S106), the write switch 7 is drive-controlled by the calculated number of application (S107), and the process ends. .
  • a switch for applying a set pulse for completely crystallizing with one application and a reset pulse for completely amorphizing with one application may be added. Group these By combining them, the rewriting speed can be further increased.
  • FIG. 5 shows a change in resistance value when a small set pulse is applied to the memory element 4 in the circuit configuration shown in FIG.
  • the vertical axis represents the resistance value of the memory element 4
  • the horizontal axis represents the number of small set pulse applications.
  • FIG. 5 shows that the resistance value of the memory element 4 gradually decreases each time a small set pulse is applied.
  • one element can have two or more values of information. In FIG. 5, seven-value information can be provided. Note that the power supply voltage, pulse width, and pulse interval of the energy pulse applied to the memory element 4 strongly depend on the material used for the memory element 4 and its element structure.
  • the stepwise change in the resistance value of the phase change recording medium can be controlled by the number of times of application of the electric pulse, that is, the digital value.
  • Rewriting control can be performed by using two types of electric pulses of the first applying means and the second applying means as the electric pulse, and the circuit configuration is the same as that of the conventional binary information rewriting control. For this reason, it is not necessary to prepare a plurality of switches for changing the magnitude (current value) of the energy pulse as in the conventional multi-value information recording method. Therefore, it is possible to record multi-valued information with a circuit area and the number of parts which are almost equal to those of a conventional memory for recording binary information. Further, since the circuit configuration of the switch circuit unit used for the memory using the conventional phase change type information recording medium for recording binary information can be used, there is no need for a significant design change.
  • an electric pulse is selected and the number of application times is determined based on a comparison result between the information read by the read control circuit and the information to be written. Therefore, the resistance value can be changed with the minimum necessary number of times of application. Therefore, an increase in power consumption can be suppressed even when recording multilevel information.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)

Abstract

Selon la présente invention, la régulation du nombre de fois qu'une impulsion électrique est appliquée sur un support d'enregistrement à changement de phase afin de réguler la modification par étapes de la valeur de résistance, permet d'enregistrer des informations à multiniveaux en fonction de la différence des valeurs de résistance. L'impulsion électrique permet de modifier progressivement sa valeur de résistance au moyen du premier dispositif d'application visant à modifier le support d'enregistrement à changement de phase d'un état de résistance élevée à un état de résistance basse et au moyen du second dispositif d'application servant à le modifier de l'état de résistance basse à l'état de résistance élevée. En fonction d'une différence entre les informations enregistrées et les informations à enregistrer, une impulsion électrique requise pour modifier les informations à écrire est sélectionnée et le nombre de fois qu'elle est appliquée est calculé. Cette invention a aussi trait à une mémoire à multiniveaux appropriée à une configuration de circuit simple à intégration élevée.
PCT/JP2004/014450 2003-09-26 2004-09-24 Memoire a multiniveaux et procede associe d'enregistrement sur support d'enregistrement de type a changement de phase WO2005031752A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005514294A JPWO2005031752A1 (ja) 2003-09-26 2004-09-24 多値メモリおよびそのための相変化型記録媒体への記録方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003335133 2003-09-26
JP2003-335133 2003-09-26

Publications (1)

Publication Number Publication Date
WO2005031752A1 true WO2005031752A1 (fr) 2005-04-07

Family

ID=34386050

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2004/014450 WO2005031752A1 (fr) 2003-09-26 2004-09-24 Memoire a multiniveaux et procede associe d'enregistrement sur support d'enregistrement de type a changement de phase

Country Status (2)

Country Link
JP (1) JPWO2005031752A1 (fr)
WO (1) WO2005031752A1 (fr)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006351780A (ja) * 2005-06-15 2006-12-28 Sony Corp 記憶素子及び記憶装置
JP2007311791A (ja) * 2006-05-19 2007-11-29 Samsung Electronics Co Ltd ＧｅＢｉＴｅ膜を相変化物質膜として採用する相変化記憶セル、それを有する相変化記憶素子、それを有する電子システム及びその製造方法
JP2007329471A (ja) * 2006-05-18 2007-12-20 Qimonda North America Corp ドープされた相変化材料を含むメモリセル
JP2009135409A (ja) * 2007-11-29 2009-06-18 Samsung Electronics Co Ltd 相変化メモリ素子の動作方法
US7558105B2 (en) 2006-01-05 2009-07-07 Samsung Electronics Co., Ltd. Phase change memory devices and multi-bit operating methods for the same
US7583525B2 (en) 2006-04-24 2009-09-01 Sony Corporation Method of driving storage device
US7715220B2 (en) 2006-06-07 2010-05-11 Sony Corporation Memory apparatus
JP2013008948A (ja) * 2011-06-23 2013-01-10 Macronix International Co Ltd ＧｅリッチなＧＳＴ−２１２相変化材料
EP4322731A3 (fr) * 2014-04-14 2024-04-24 Pragmatic Printing Ltd Circuit électronique et système de stockage de données

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002541613A (ja) * 1999-04-12 2002-12-03 エナージー コンバーション デバイセス インコーポレイテッド ユニバーサルメモリ素子を使用するシステムを有するユニバーサルメモリ素子と、同メモリ素子を読み取り、書き込み、またプログラムするための装置と方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002541613A (ja) * 1999-04-12 2002-12-03 エナージー コンバーション デバイセス インコーポレイテッド ユニバーサルメモリ素子を使用するシステムを有するユニバーサルメモリ素子と、同メモリ素子を読み取り、書き込み、またプログラムするための装置と方法

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006351780A (ja) * 2005-06-15 2006-12-28 Sony Corp 記憶素子及び記憶装置
JP4715320B2 (ja) * 2005-06-15 2011-07-06 ソニー株式会社 記憶素子及び記憶装置
US7558105B2 (en) 2006-01-05 2009-07-07 Samsung Electronics Co., Ltd. Phase change memory devices and multi-bit operating methods for the same
US7583525B2 (en) 2006-04-24 2009-09-01 Sony Corporation Method of driving storage device
JP2007329471A (ja) * 2006-05-18 2007-12-20 Qimonda North America Corp ドープされた相変化材料を含むメモリセル
JP2007311791A (ja) * 2006-05-19 2007-11-29 Samsung Electronics Co Ltd ＧｅＢｉＴｅ膜を相変化物質膜として採用する相変化記憶セル、それを有する相変化記憶素子、それを有する電子システム及びその製造方法
US7715220B2 (en) 2006-06-07 2010-05-11 Sony Corporation Memory apparatus
JP2009135409A (ja) * 2007-11-29 2009-06-18 Samsung Electronics Co Ltd 相変化メモリ素子の動作方法
JP2013008948A (ja) * 2011-06-23 2013-01-10 Macronix International Co Ltd ＧｅリッチなＧＳＴ−２１２相変化材料
EP4322731A3 (fr) * 2014-04-14 2024-04-24 Pragmatic Printing Ltd Circuit électronique et système de stockage de données

Also Published As

Publication number Publication date
JPWO2005031752A1 (ja) 2006-12-07

Similar Documents

Publication Publication Date Title
US7535756B2 (en) Method to tighten set distribution for PCRAM
US8094488B2 (en) Set algorithm for phase change memory cell
US5687112A (en) Multibit single cell memory element having tapered contact
JP3749847B2 (ja) 相変化型不揮発性記憶装置及びその駆動回路
US7701759B2 (en) Memory cell device and programming methods
US7423300B2 (en) Single-mask phase change memory element
US7254059B2 (en) Multilevel phase-change memory element and operating method
TWI422013B (zh) 具有一個或多個非定值摻雜濃度分佈的相變化記憶體
US5933365A (en) Memory element with energy control mechanism
KR100738092B1 (ko) 상전이 메모리 소자의 멀티-비트 동작 방법
US7233017B2 (en) Multibit phase change memory device and method of driving the same
US8077505B2 (en) Bipolar switching of phase change device
US20100171087A1 (en) Semiconductor device and process for producing the same
JP4911845B2 (ja) 相変化型不揮発性メモリ素子、該相変化型不揮発性メモリ素子を用いたメモリアレーおよび該相変化型不揮発性メモリ素子の情報記録方法
US20060077741A1 (en) Multilevel phase-change memory, manufacturing and status transferring method thereof
KR101058856B1 (ko) 기억소자 및 이를 이용한 기억장치
JP2001502848A (ja) 相変化性メモリ材料と誘電材料との混合物から成る複合メモリ材料
JPH11510317A (ja) 電気的に消去可能で直接上書き可能な複数ビット単一セル記憶素子及びそれらで作製されるアレイ
JP2004311015A (ja) 低電流高速相変化メモリ素子及びその駆動方法
JP2008091682A (ja) 多値記録相変化メモリ素子、多値記録相変化チャンネルトランジスタおよびメモリセルアレイ
US7483292B2 (en) Memory cell with separate read and program paths
JP2003100084A (ja) 相変化型不揮発性記憶装置
US11917930B2 (en) Resistance change device and storage device
WO2005031752A1 (fr) Memoire a multiniveaux et procede associe d'enregistrement sur support d'enregistrement de type a changement de phase
US20080273369A1 (en) Integrated Circuit, Memory Module, Method of Operating an Integrated Circuit, and Computing System

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

DPEN Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed from 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2005514294

Country of ref document: JP

122 Ep: pct application non-entry in european phase