JP2734017B2 - Non-volatile memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory, and more particularly, to an electrically writable and erasable nonvolatile memory.

[Prior art] Conventionally, in an electrically writable and erasable non-volatile memory (hereinafter referred to as an EEPROM [electrically erasable programmable read only memory]), various characteristics of a memory cell are selected as a write / erase voltage. Have been. That is, the deterioration characteristics (Endurance characteristic) of the memory cell due to repetition of writing and erasing, the loss of data due to high-temperature storage, the writing characteristic (Retention characteristic), and the writing and erasing characteristics such as the minimum erasable voltage and the writing and erasing voltage for one hour. , The capability of the memory cell is evaluated, and the optimum and assurable voltage for writing and erasing of the memory cell is selected by statistical data processing (for example, 25
V) Then set.

[Problems to be solved by the invention]

In the above-mentioned conventional EEPROM, the set write / erase voltage should be an optimum value for a standard that can be guaranteed, but it is not necessarily optimal because there is actually a variation in memory cell characteristics. Disappears.

That is, the conventional EEPROM has a drawback that the characteristics of the memory cell are changed while repeatedly performing writing and erasing, and there is a possibility that writing and erasing cannot be performed in the initially set writing and erasing time. In addition, since the conventional EEPROM has a fixed write / erase voltage, the same stress as in the initial state is applied to the memory cell even when the memory cell is deteriorated due to repeated write / erase, thereby shortening the life of the memory cell. There are drawbacks.

An object of the present invention is to provide a nonvolatile memory (EEPROM) capable of performing such stable writing / erasing and extending the life.

[Means for solving the problem]

An EEPROM of the present invention is an electrically erasable and erasable nonvolatile memory, comprising: a first memory cell for storing data; and a small-scale second memory for setting a write / erase voltage for the first memory cell. When charge is injected into the cell and the second memory cell and when the charge is not injected, a threshold voltage of the second memory cell is sampled, and a maximum value and a minimum value are detected therefrom. The second memory, comprising: detecting means; and write / erase voltage selecting means for determining a write / erase voltage of the first memory cell from a maximum value and a minimum value of a threshold voltage detected by the detector. The first memory cell is configured to change a write / erase voltage based on cell characteristics.

A detecting circuit for sampling a threshold voltage of the second memory cell; a sampling voltage selecting circuit for selecting a maximum value and a minimum value of the threshold voltage from the sampling circuit; A comparison circuit that compares the sampling voltage from the sampling voltage selection circuit with a predetermined reference voltage and creates a correction signal for changing the write / erase voltage of the first memory cell with respect to the write / erase voltage selector. It is composed.

Further, the first memory cell and the second memory cell may be configured to be controlled by a common column decoder and a common row decoder.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an EEPROM showing a first embodiment of the present invention.

As shown in FIG. 1, the EEPROM of this embodiment has a first memory cell array 1 for storing data, and a column decoder 2 and a row decoder 3 for receiving and developing an address for accessing the memory cell array 1 from outside. A write / erase voltage selection circuit 4 for selecting a write / erase voltage based on a write / erase request; a second memory cell array 5 having a smaller capacity than the first memory cell array 1;
And an OR gate 6 which takes the logic of the erase request 16, a write / erase voltage switching circuit 7, a high voltage generating circuit 8, a comparing circuit 9, a comparative value selecting circuit 10, a sampling voltage selecting circuit 11, a read voltage generating circuit 12, Sampling circuit 13
And a write erasure control circuit 14 for the first memory cell array 1.

 Next, the function of each circuit of the EEPROM will be described.

First, when the write request 15 or the erase request 16 is emitted based on the write / erase request, the write / erase control circuit 14 selects the address indicated by the column decoder 2 and the row decoder 3 by the write / erase voltage selection circuit 4. A write / erase voltage is applied. This write / erase voltage selection circuit 4
At the time of writing, based on the correction signal 19 from the comparison circuit 9, a write / erase selection signal 18 corresponding to the correction signal 19 is sent out to the write / erase voltage switching circuit 7, and the selected write voltage
17 is supplied to the write / erase control circuit 14. When the write request 15 is emitted, the sampling circuit 13 detects an ON current in each memory cell of the second memory cell array 5 and converts the ON current into a voltage. Read voltage generation circuit 12
Supplies a voltage (read voltage) for turning on the memory cells to the second memory cell array 5 when the write request 15 is emitted. On the other hand, the sampling voltage selection circuit
11 selects an arbitrary one from the sampling voltages from the sampling circuit 13 and sends a detection signal 20 to the read voltage generation circuit 12 indicating that the sampling voltage from the sampling circuit 13 has been detected. Further, the comparison circuit 9 compares the sampling voltage selected from the sampling voltage selection circuit 11 with the reference voltage from the comparison value selection circuit 10, and outputs a correction signal 19 to the write / erase voltage selection circuit 4. The comparison value selection circuit 10 storing the above-described reference value stores the threshold value of the memory cell obtained from various characteristics of the memory cell and the correction value of the erase voltage with respect to the write voltage. A circuit for exchanging data. Further, the write / erase voltage switching circuit 7 is a circuit for selecting an arbitrary write / erase voltage 17 from the write / erase voltage selection signal 18 from the write / erase voltage selection circuit 4, and the high voltage generation circuit 8 connected to the switch circuit 7. Is a circuit for generating a plurality of write / erase voltages.

The function and operation of each constituent circuit have been described above. The overall circuit operation of the present embodiment will be described below with reference to FIGS. 1 and 2.

FIG. 2 is a signal waveform diagram of each section of the memory shown in FIG.

Now, in the EEPROM, the write state is defined as a state in which charges are injected into the memory cell, and the erase state is defined as a state in which charges are not injected into the memory cell.

As shown in FIG. 1 and FIG. 2, when a write request 15 is issued to a memory cell of the memory cell array 1,
In synchronization with the write signal 22, writing is performed by the write / erase voltage 17 from the write / erase voltage switching circuit 7. At this time, the write / erase voltage 17 is determined by the initial characteristics of the memory cell. At the time of this write operation, data is simultaneously written to the second memory cell array 5 in addition to the first memory cell array 1. Thereafter, when the write signal 22 falls, the write request 15
Synchronized with Φ issued in the second memory cell array 5
, A minimum voltage capable of turning on the memory cell is applied from the read voltage generation circuit 12. The minimum voltage at which the memory cell can be turned on is determined from various characteristics of the memory cell. In an ideal memory, the threshold voltage is plus α. The current flowing when each memory cell is turned on is sampled by the sampling circuit 13 for each bit and converted into a voltage. At this time, when only one bit in each memory cell is turned ON and when all the bits are turned ON, the sampling voltage selection circuit 11
, And outputs a detection signal 20. The read voltage generation circuit 12 varies the read voltage according to the detection signal 20. Further, the sampling voltage selection circuit 11 selects the maximum value and the minimum value from the sampling voltage of each memory cell, and sends them to the comparison circuit 9. Therefore, the comparison circuit 9 compares the maximum and minimum sampling voltages from the sampling voltage selection circuit 11 with the voltage (hereinafter referred to as VTM) for reading the first memory cell array 1 from the comparison value selection circuit 10, and If the sampling voltage is small, the correction signal 19 is not output to the write / erase voltage selection circuit 4, and if both the maximum and minimum sampling voltages are high, the correction signal 19 is output. Here, the correction signal 19 differs depending on the difference between the voltage VTM for reading the first memory cell array 1 and the maximum and minimum sampling voltages. If the difference from the VTM is small, a correction signal 19 for increasing the write voltage is output, and if the difference from the VTM is large, a correction signal 19 for decreasing the write voltage is output. The difference between the maximum and minimum sampling voltages is small as long as there is no significant variation, so there is no problem even if it is not taken into consideration. Based on the correction signal 19, the write / erase voltage selection circuit 4 sends a signal for selecting the corrected write voltage to the write / erase voltage switching circuit 7. As a result, the write / erase voltage switching circuit 7 selects one from a plurality of write voltages applied from the high voltage generation circuit 8. In this way, a write voltage suitable for the actual memory cell is always supplied from the next write.

This is performed only at the time of writing, not at the time of erasing. That is, the change in the threshold value of the memory can be estimated by checking any of the write states, and the other change can be estimated. Accordingly, at the time of erasing, the comparison circuit 9 performs correction at the time of erasing from the comparison value selecting circuit 10 and selects an actual erasing voltage from a plurality of erasing voltages from the high voltage generating circuit 8.

In the present embodiment, it can be seen that the accuracy of the write voltage can be increased by increasing the number of the second memory cell arrays 5 to be sampled.

FIG. 3 is a block diagram of a nonvolatile memory showing a second embodiment of the present invention.

As shown in FIG. 3, this embodiment operates basically in the same manner as the above-described first embodiment, except that all the addresses of the first memory cell array 1 or a column for sampling the memory cells corresponding to a specific address. Control signals are also required for decoder 2 and row decoder 3. That is,
This embodiment has the advantage that it is not necessary to have a memory cell dedicated to detecting the threshold voltage of the memory cell, and the sampling number can be arbitrarily varied.

〔The invention's effect〕

As described above, the EEPROM of the present invention can always sample the characteristics of a memory cell that changes every time the data is written or erased, and can set (variable) the write / erase voltage in accordance with the characteristics. Even if the characteristics change, there is an effect that writing and erasing can be performed stably.
Further, since the present invention prevents unnecessary stress from being applied to the memory cell, there is an effect that the life of the memory cell can be extended.

[Brief description of the drawings]

FIG. 1 is a block diagram of a nonvolatile memory showing a first embodiment of the present invention, FIG. 2 is a signal waveform diagram of each part of the memory shown in FIG. 1, and FIG. 3 is a second embodiment of the present invention. It is a block diagram of the non-volatile memory shown. 1,5 ... memory cell array, 2 ... column decoder, 3 ...
Row decoder 4, write / erase voltage selection circuit 7, write / erase voltage switching circuit 8, high voltage generation circuit 9, 9
Comparison circuit, 10: Comparison value selection circuit, 11: Sampling voltage selection circuit, 12: Read voltage generation circuit, 13: Sampling circuit, 14: Write / erase control circuit, 15: Write request, 16: Erase request, 17 ... Write / erase voltage, 18 ...
... write / erase voltage selection signal, 19 ... correction signal, 20 ... detection signal, 21 ... read voltage.

Claims (3)

(57) [Claims] 1. An electrically writable and erasable nonvolatile memory, a first memory cell for storing data, and a small second memory cell for setting a write / erase voltage for the first memory cell. Detecting when the charge is injected into the second memory cell and when the charge is not injected, sampling the threshold voltage of the second memory cell and detecting the maximum value and the minimum value from the sampled value Means for determining the write / erase voltage of the first memory cell from the maximum value and the minimum value of the threshold voltage detected by the detection means, and the second memory cell A non-volatile memory, wherein a write / erase voltage of the first memory cell is changed based on characteristics. 2. A sampling circuit for sampling a threshold voltage of the second memory cell;
A sampling voltage selection circuit for selecting a maximum value and a minimum value of the threshold voltage from the sampling circuit, and a sampling voltage and a predetermined reference voltage from the sampling voltage selection circuit, 2. The non-volatile memory according to claim 1, further comprising: a comparison circuit for generating a correction signal for changing a write / erase voltage of said first memory cell. 3. The nonvolatile memory according to claim 1, wherein said first memory cell and said second memory cell are both controlled by a common column decoder and row decoder.