JPH02123597A - Nonvolatile memory - Google Patents

Abstract

PURPOSE:To stabilize writing and easing, to eliminate unnecessary stress to be applied to a memory cell, and to give a longer life to the memory cell by always sampling the characteristic of an EEPROM to change whenever the writing and erasing is executed and variably setting writing and erasing voltage according to the characteristic. CONSTITUTION:The maximum sampling voltage and the minimum sampling voltage from a sampling voltage selecting circuit 11 are compared with voltage for reading out the first memory cell array 1 from a comparing and selecting circuit 10 in a comparator circuit 9. At this time, when the minimum sampling voltage is smaller, a correcting signal 19 is not outputted to a writing and erasing voltage selecting circuit 4, and when both the maximum sampling voltage and the minimum sampling voltage are larger, the signal 19 is outputted. After that, a selecting signal is sent from the circuit 4 to a writing and erasing voltage switching circuit 7 based on this correcting signal 19, and the optimum voltage is selected out of plural types of writing voltage given by a high voltage generating circuit 8 in the circuit 7. Thus, from the next writing, the writing voltage to match the capability of the actual memory cell can always be supplied.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to non-volatile memories, and more particularly to electrically writable and erasable non-volatile memories.

[Conventional technology]

Conventionally, in electrically programmable and erasable non-volatile memories (hereinafter referred to as EEPROMs (Electrically Erasable Programmable Read-Only Memories)), the program and erase voltages are selected based on various characteristics of the memory cells. , deterioration characteristics of memory cells due to repeated programming and erasing (Endurance characteristics), data loss due to high temperature storage, and leakage characteristics (Rete
The ability of the memory cell is evaluated from the write/erase characteristics such as the minimum voltage that can be written and erased, and the write/erase voltage vs. time, and the optimum and guaranteed write/erase of the memory cell is determined by statistical data processing. A possible voltage (for example, 25V) is selected and set.

[Problem to be solved by the invention]

In the conventional EEPROM described above, the set write/erase voltage is supposed to be the optimum value for the guaranteed standard, but in reality, it is not necessarily the optimum value because of variations in memory cell characteristics. It disappears.

That is, the conventional EEPROM has a drawback that the characteristics of the memory cell change during repeated programming and erasing, and there is a possibility that programming and erasing cannot be performed within the initially set programming and erasing time. In addition, conventional EEPRO
Since the write/erase voltage of M is fixed, even when the memory cell deteriorates due to repeated writing/erasing, the same stress as in the initial state is applied to the memory cell.
It has the disadvantage of shortening the lifespan of memory cells.

The object of the present invention is to provide a non-volatile memory (EEPROM) capable of stable writing/erasing and a long service life.
).

[Means to solve the problem]

The EEF ROM of the present invention is an electrically programmable and erasable nonvolatile memory that includes a memory cell and a threshold value of the memory cell when charge is injected into the memory cell and when charge is not injected into the memory cell. The memory cell includes means for detecting a voltage, and means for determining a write/erase voltage from the detected threshold voltage, and is configured to change the write/erase voltage based on the memory cell characteristics.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is an EEPR showing a first embodiment of the present invention.

It is a block diagram of 0M.

As shown in FIG. 1, the EEPROM of this embodiment includes a first memory cell array 1 that stores data, a column decoder 2 and a row decoder 3 that receive and develop addresses for accessing the memory cell array 1 from the outside. , a write/erase voltage selection circuit 4 that selects a write/erase voltage based on a write/erase request, etc., and the first memory cell array 1
, an OR gate 6 that takes the logic of the write request 15 and the erase request 16, a write/erase voltage switching circuit 7, a high voltage generation circuit 8, a comparison circuit 9, and a comparison value selection circuit. circuit 10 and sampling voltage selection circuit 11. It is comprised of a reading ratio voltage generation circuit 12, a sampling circuit 13, and a write/erase control circuit 14 for the first memory cell array 1.

Next, the functions of each circuit of this EEPROM will be explained.

First, when a write request 15 or an erase request 16 is issued based on a write/erase request, the write/erase control circuit 14 selects a voltage selected by the write/erase voltage selection circuit 4 for the address indicated by the column decoder 2 and row decoder 3. Apply write/erase voltage. This write/erase voltage selection circuit 4
is a write/erase selection signal 1 corresponding to the correction signal 19 based on the correction signal 19 from the comparator circuit 9 during writing.
8 is sent to the write/erase voltage switching circuit 7, and the selected write voltage 17 is supplied to the write/erase control circuit 14.

Furthermore, when the write request 15 is issued, the sampling circuit 13 detects the ON current in each memory cell of the second memory cell array 5 and converts it into a voltage. The read voltage generation circuit 12 outputs memory cells to the second memory cell array 5 when the write request 15 is issued.
A voltage (reading ratio voltage) is supplied to make the voltage N. on the other hand,
The sampling voltage selection circuit 11 is the sampling circuit 13
An arbitrary one is selected from the sampling voltages from the sampling circuit 13, and a detection signal 20 indicating that the sampling voltage from the sampling circuit 13 has been detected is sent to the reading ratio voltage generation circuit 12. Further, the comparison circuit 9 compares the sampling voltage selected from the sampling voltage selection circuit 11 and the reference voltage from the comparison value selection circuit 10 and outputs a correction signal 19 to the write/erase voltage selection circuit 4. The comparison value selection circuit 10, which stores the above-mentioned reference value, stores the threshold value of the memory cell obtained from the initial characteristics of the memory cell and the correction value of the erase voltage for the write voltage. This is a circuit that exchanges data. Furthermore, the write/erase voltage switching circuit 7 is a circuit that selects an arbitrary write/erase voltage 17 from the write/erase voltage selection signal 18 from the write/erase voltage selection circuit 4;
A high voltage generating circuit 8 connected to is a circuit that generates a plurality of write/erase voltages.

The functions and operations of each component circuit have been explained above, and the overall circuit operation of this embodiment will be explained below with reference to FIGS. 1 and 2.

FIG. 2 is a signal waveform diagram of each part of the memory shown in FIG. 1.

In EEPRO'M, a written state is defined as a state in which charges are injected into a memory cell, and an erased state is defined as a state in which charges are not injected into a memory cell.

As shown in FIGS. 1 and 2, a memory cell array 1
When write request 15 is issued to the memory cell of
Writing is performed using the write/erase voltage 17 from the write/erase voltage switching circuit 7 in synchronization with the write signal 22 . The write/erase voltage 17 at this time is determined by the initial characteristics of the memory cell.

During this write operation, data is written into the second memory cell array 5 as well as the first memory cell array 1 at the same time. Thereafter, when the write signal 22 falls, in synchronization with Φ issued in the write request 15, the read voltage generation circuit 12 can turn on the memory cells of the second memory cell array 5. A voltage is applied. The minimum voltage that can turn on this memory cell is determined from the initial characteristics of the memory cell, and in an ideal memory cell is the threshold voltage plus α. The current flowing when each memory cell is turned on is sampled for each bit by a sampling circuit 13 and converted into a voltage. At this time, the sampling voltage selection circuit 11 outputs a detection signal 20 to the read voltage generation circuit 12 when only one bit in each memory cell is turned ON or when all bits are ONL.

Based on this detection signal 20, the read voltage generating circuit 12 varies the read voltage. Further, the sampling voltage selection circuit 11 selects the maximum value and the minimum value from the sampling voltages of each memory cell, and sends them to the comparison circuit 9. Therefore, the comparison circuit 9 uses the maximum and minimum sampling voltages from the sampling voltage selection circuit 11 and the comparison value selection circuit 10.
If the minimum sampling voltage is small, the correction signal 19 is not output to the write/erase voltage selection circuit 4, and the maximum, minimum sampling voltage is If both sampling voltages are large, a correction signal 19 is output. Here, one correction signal is the maximum voltage VTM for reading the first memory cell array 1.

It differs depending on the difference from the minimum sampling voltage. Correction signal 1 that increases the write voltage if the difference with this VTM is small
9 is output, and conversely, if the difference with VTM is large, a correction signal 19 is output that lowers the difference. The difference between the maximum and minimum sampling voltages is small unless there is considerable variation, so there is no problem even if it is not taken into consideration. Based on this one correction signal, the write/erase voltage selection circuit 4 sends a signal to the write/erase voltage switching circuit 7 for selecting the corrected write voltage. Thereby, the write/erase voltage switching circuit 7 selects one of the plurality of write voltages applied from the high voltage generation circuit 8. By doing this, from the next write onwards, a write voltage that matches the actual capacity of the memory cell is always supplied.

Note that this is performed only during writing and not during erasing. That is, by checking one of the write states, it is possible to estimate the fluctuation of the memory threshold value by checking the other writing state. Therefore, at the time of erasing, the comparator circuit 9 applies correction during erasing from the comparison value selection circuit 10, and selects the actual erasing voltage from a plurality of erasing voltages from the high voltage generating circuit 8.

In this embodiment, it can be seen that in order to improve the accuracy of the write voltage, it is sufficient to increase the number of second memory cell arrays 5 to be sampled.

FIG. 3 is a block diagram of a nonvolatile memory showing a second embodiment of the present invention.

As shown in FIG. 3, this embodiment basically operates in the same way as the first embodiment described above, but in order to sample memory cells corresponding to all addresses or a specific address in the first memory cell array 1, Control signals are also required for decoder 2 and row decoder 3. That is, this embodiment has the advantage that it is not necessary to have a memory cell dedicated to detecting the threshold voltage of the memory cell, and the number of samplings can be arbitrarily varied.

〔Effect of the invention〕

As explained above, the EEPROM of the present invention constantly samples the characteristics of the memory cell that change each time it is written or erased, and sets the write/erase voltage according to the characteristics (
This has the advantage that even if the characteristics of the memory cell change, writing and erasing can be performed stably. Further, since the present invention prevents unnecessary stress from being applied to the memory cells, it has the effect of extending the life of the memory cells.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a nonvolatile memory showing a first embodiment of the present invention, FIG. 2 is a signal waveform diagram of each part of the memory shown in FIG. 1, and FIG. 3 is a block diagram of a nonvolatile memory showing a first embodiment of the present invention. FIG. 2 is a block diagram of a nonvolatile memory shown in FIG. 1.5...Memory cell array, 2...Column decoder,
3... Row decoder, 4... Write/erase voltage selection circuit, 7... Write/erase voltage switching circuit, 8... High voltage generation circuit, 9... Comparison circuit, 10... Comparison value selection Circuit, 11... Sampling voltage selection circuit, 12... Read voltage generation circuit, 13... Sampling circuit, 14
...Write/erase control circuit, 15...Write request, 1
6... Erase request, 17... Write/erase voltage, 18.
...Write/erase voltage selection signal, 19...Correction signal, 2
0...Detection signal, 21...Read voltage.

Claims (1)

[Claims] In an electrically programmable and erasable non-volatile memory, a memory cell, means for detecting a threshold voltage of the memory cell when charge is injected into the memory cell and when charge is not injected into the memory cell; and means for determining a write/erase voltage from a threshold voltage determined by the memory cell, the nonvolatile memory being characterized in that the write/erase voltage is changed based on the memory cell characteristics.