JPH05258581A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To perform an appropriate writing/erasing operation in a single action without sequentially executing additional writing/erasing operation by utilizing the processed voltages by means of a differential voltage operating means as a writing voltage/erasing voltage in a writing means/erasing means. CONSTITUTION:After executing prescribed number of times of writing/erasing for an objective cell transistor while measuring the threshold voltage of this transistor, the measurement of an accurate threshold voltage absorbing a dispersion in the elements is carried out, the measurement by a differential type sense amplifier is realized and the measurement of the threshold voltage of the objective transistor is facilitated. The memory device concretely consists of a measuring means for threshold voltage 1, a differential voltage operating means 2, a cell transistor CT, a word line WL, a sense amplifier made of a dummy cell DM, a writing means 4 and an erasing means 5. The means 1 consists of a deciding part 6, a controller 7, a counter 8 and a DAC 9, data are successively outputted from the counter 8 through the DAC 9 by means of the control signal from the controller 7 and the threshold voltage of the objective cell is obtained by means of the deciding part 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more specifically, for example, an EEPROM (Electric)
The present invention relates to a nonvolatile semiconductor memory device capable of rewriting data, which is suitable for use in fields such as ally erasable programmable read only memory). 2. Description of the Related Art In recent years, with the spread of information processing devices such as computers and word processors, for example, EEPROM and Fl used inside the information processing devices.
Many non-volatile semiconductor memory devices represented by non-volatile semiconductor memories such as ashEEPROM (hereinafter, simply referred to as flash memory) have been developed.

This is a non-volatile memory which can be programmed by a general user and can be rewritten by electrically erasing predetermined data written in advance. However, there are proper voltage values for writing and erasing, and excessive writing and erasing lead to deterioration of the device.
Therefore, it is necessary to perform proper writing and erasing.

[0003]

2. Description of the Related Art Conventionally, as a semiconductor memory device which is a non-volatile memory that can be rewritten by erasing predetermined data written in advance, for example, EPROM and EEPROM are known. However, EPROM
Has an advantage that the cell size is small, but has a disadvantage that the data erasing is troublesome because ultraviolet rays are used for erasing the data, and the EEPROM can easily erase the data because the data can be electrically erased. However, the cell size is larger than that of the EPROM, so that it is difficult to increase the capacity.

Therefore, for example, a semiconductor memory device called NOR type or NAND type flash memory, which has the advantages of each of these memories, has been developed. FIG. 6 is a sectional view of a typical cell of a flash memory. In the figure,
CG is a control gate, FG is a floating gate, D is an N ⁺ type drain, S is an N ⁺ type source, PS
Is a P-type substrate.

FIG. 7 is a circuit diagram showing a cell matrix structure of the flash memory shown in FIG. In the figure, C is each memory cell, WL _x is a word line, BL _x is a bit line, SL _x
Indicates a select line. (However, _x represents _i , _j , _a , _m , _n in the figure.) Next, the operation will be described.

First, when writing to the memory cell C, the high potential voltage V _PP is applied to the control gate CG and the drain D, and electrons are injected into the floating gate FG by avalanche injection in the vicinity of the drain D, so that the memory is erased. Cell C is cut off. To delete,
A high potential voltage VPP is applied to the source S with the drain D floated, and electrons are removed from the floating gate FG, thereby erasing the written data.

The potential levels of the control gate CG, the drain D, the source S, and the substrate PS in the above-mentioned operating state are set to the values shown in Table 1.

[0008]

[Table 1]

[0009]

However, in such a conventional semiconductor memory device, by applying the high potential voltage V _PP to the control gate CG and the drain D, the avalanche injection in the vicinity of the drain D is performed. Since the configuration is such that electrons are injected into the floating gate FG to write data, and the written data is erased by removing electrons from the floating gate FG, there are problems as described below. It was

That is, in NOR type flash memory, F
In the case of performing -N channeling erasing, if the cell transistor is excessively erased, a non-selected memory cell causes a leak current to flow and become conductive, which makes it impossible to read the written cell. Also, NAN
When performing F-N channeling writing to the D-type flash memory, excessive writing causes non-conduction of non-selected memory cells, making it impossible to read cells without writing, and also to prevent tunneling of the tunnel oxide film. There is a problem that reliability deteriorates due to deterioration, the number of times of writing and erasing is reduced, and finally writing and erasing cannot be performed.

Therefore, in order to avoid these problems, as shown in FIG. 8, the threshold voltage of the cell transistor is estimated at the time of verification by providing the sense amplifier with a threshold value dedicated to verification, which is different from that during normal reading and writing. There are some methods to make the threshold voltage uniform by performing additional writing / erasing little by little. In this case,
Since additional writing / erasing is performed little by little, additional writing / erasing needs to be performed many times, which causes a new problem that writing / erasing takes time.

[Object] Therefore, an object of the present invention is to provide a non-volatile semiconductor memory device which performs appropriate writing / erasing with a small number of writing / erasing times.

[0013]

In order to achieve the above object, a non-volatile semiconductor memory device according to the present invention has a plurality of cell transistors for storing and holding predetermined data, and a plurality of cell transistors among the plurality of cell transistors. Writing means for writing to any cell transistor of a predetermined writing voltage, and threshold voltage measuring means for measuring a threshold voltage of a predetermined cell transistor to be written by the writing means,
A threshold voltage value measured by the threshold voltage measuring means,
And a difference voltage calculation means for calculating a difference voltage value with respect to an appropriate voltage value required for writing which is set in advance, and the writing means uses the voltage value calculated by the difference voltage calculation means as a write voltage. Is configured as follows.

According to a second aspect of the present invention, a plurality of cell transistors for storing and holding predetermined data, an erasing means for erasing an arbitrary cell transistor in the plurality of cell transistors with a predetermined erasing voltage, and Of the threshold voltage measuring means for measuring the threshold voltage of a predetermined cell transistor to be erased by the erasing means, the threshold voltage value measured by the threshold voltage measuring means, and a preset appropriate voltage value necessary for erasing The erasing means is configured to use the voltage value calculated by the differential voltage calculating means as the erasing voltage.

According to a third aspect of the invention, the threshold voltage measuring means is configured to measure the threshold voltage of the cell transistor after writing or erasing the cell transistor a predetermined number of times. According to the invention of claim 4,
The differential voltage calculation means includes a high voltage regulator,
The output voltage of the high voltage regulator is changed based on the difference voltage value which is the calculation result of the difference voltage calculation means.

According to a fifth aspect of the present invention, the threshold voltage measuring means operates based on the threshold voltage of a cell transistor to be written or erased and the threshold voltage of a dummy cell paired with the cell transistor. Type sense amplifier, and the threshold voltage of the cell transistor is measured by sequentially scanning the gate voltage of the dummy cell.

[0017]

According to the present invention, the voltage value calculated by the differential voltage calculation means is equal to the write voltage / write voltage in the writing means / erasing means.
Since the erase voltage is used, proper writing / erasing can be performed once without additional writing / erasing. That is, appropriate writing / erasing is performed with a small number of writing / erasing times.

Further, by measuring the threshold voltage of this cell transistor after writing / erasing a predetermined number of times with respect to the target cell transistor, variations between elements are absorbed, and an accurate threshold voltage is measured. In addition, the threshold voltage of the target cell transistor can be easily measured by using the differential sense amplifier.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. 1 to 5 are views showing an embodiment of a nonvolatile semiconductor memory device according to the present invention, and FIG. 1 is a view showing a main configuration of the present embodiment. First, the configuration will be described with reference to FIG.

The nonvolatile semiconductor memory device of this embodiment is roughly classified into a cell transistor CT, a threshold voltage measuring means 1,
It is composed of a differential voltage calculation means 2, a sense amplifier 3, a writing means 4, and an erasing means 5. In the figure, WL is a word line and DM is a dummy cell. Threshold voltage measuring means 1
Is composed of a determination unit 6, a control unit 7, a counter 8, and a DAC 9. The control signal from the control unit 7 causes the dummy cell DM located on the opposite side of the cell transistor CT (hereinafter referred to as the target cell) to be measured. 4-bit output a,
The counter 8 having b, c, and d outputs the sequentially incremented data via the DAC 9, and the counter when the determination cell 6 balances the target cell and the dummy cell DM based on the output signal from the sense amplifier 3. The outputs a, b, c and d of 8 are used as the threshold voltage value of the target cell.

FIG. 2 is a circuit diagram showing the differential voltage calculation means. The differential voltage calculation means 2 includes a charge pump 10, a diode D1, a resistor R1, N channel MOS transistors NM1 to NM9, and a P channel MOS transistor PM1.
~ PM6. N-channel MOS
The transistors NM5, NM8, NM9 are depletion type MOS transistors.

The differential voltage calculating means 2 has a predetermined high potential voltage value set in advance in the circuit itself, and receives the 4-bit outputs a, b, c, d from the counter 8 as inputs, and the difference voltage from the high potential voltage value. It outputs a value. FIG. 3 is a circuit diagram showing a sense amplifier. The sense amplifier 3, as shown in FIG. 3, has N-channel MOS transistors NM11 to NM11.
NM14, P-channel MOS transistors PM11, P
It is a differential type sense amplifier composed of M12. The N-channel MOS transistors NM11, NM12
Is a high voltage MOS transistor.

FIG. 4 is a circuit diagram for explaining an operation example of this embodiment. As shown in FIG. 4, the writing means 4 and the erasing means 5 are respectively composed of high voltage switches S1 and S2 and AND gates AND1 and AND2. Next, the operation will be described. First, the counter 7 is set to “0” by the control unit 7.
It is sequentially incremented from 000 "and input to the DAC 9.

In the DAC 9, the input 4-bit digital value is converted into an analog value, and the writing of the voltage level corresponding to the 4-bit data input from the counter 8 is performed on the dummy cell DM forming a pair with the target cell. Is done. Then, the threshold voltage of the target cell and the dummy cell DM is compared by the sense amplifier 3, and the determination unit 6 determines the magnitude of the threshold voltage of the target cell and the dummy cell DM based on the comparison result from the sense amplifier 3.

Specifically, the output values a, b, c, d of the counter 3 at the time when the output from the sense amplifier 3 is inverted.
Is recognized as the threshold voltage of the target cell, and 4-bit data (abcd) from the counter 8 is output to the differential voltage calculation means 2. In the differential voltage calculation means 2, the high potential voltage level necessary for writing / erasing is set in the circuit itself, and the 4-bit data a, b, c, d are set from this high potential voltage level.
The differential voltage obtained by subtracting the value represented by is output to the writing unit 4 and the erasing unit 5.

In the writing means 4 and the erasing means 5, as described above, the control gate C depends on the operating state.
By setting the potential levels of G, the drain D, the source S, and the substrate PS to the values shown in Table 1, writing / erasing is performed with a predetermined write voltage / erase voltage. FIG. 5 is a diagram for explaining an operation example at the time of writing and erasing of the present embodiment. In this example, after writing / erasing a small potential level to the dummy cell DM twice,
The threshold voltage of the target cell is measured, and then writing / erasing is performed at an appropriate voltage level.

In other words, in the present embodiment, the writing / erasing of a small potential level is first performed twice to prevent the deterioration of the measurement accuracy due to the variation between the elements and the loss of the charge. The threshold voltage of can be measured. As described above, in this embodiment, the voltage value calculated by the differential voltage calculation means is set as the write voltage / erase voltage in the write means / erase means, so that it is possible to perform additional write / erase little by little. Appropriate writing / erasing can be done once.

Therefore, proper writing / erasing can be performed with a small number of writing / erasing times. In addition,
In the above-described embodiment, the writing / erasing is completed by the third writing / erasing for the purpose of preventing the measurement error due to the variation between the elements and the loss of charge, but the number of times is arbitrary, and the number of times is arbitrary. It goes without saying that writing / erasing may be performed.

Also, regarding the number of bits of the counter when measuring the threshold voltage of the target cell, regardless of the above embodiment,
You can set it freely. In this case, the measurement accuracy can be further improved by increasing the number of bits.

[0030]

According to the present invention, since the voltage value calculated by the differential voltage calculation means is used as the write voltage / erase voltage in the write means / erase means, even if the additional write / erase is not performed little by little, Appropriate writing / erasing can be done in a single operation. Therefore, appropriate writing / erasing can be performed with a small number of writing / erasing times.

Further, the threshold voltage of this cell transistor is measured after writing / erasing a target cell transistor a predetermined number of times, so that variations between elements are absorbed and an accurate threshold voltage is measured. In addition, the threshold voltage of the target cell transistor can be easily measured by using a differential sense amplifier.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a main part of this embodiment.

FIG. 2 is a circuit diagram showing a differential voltage calculation means of FIG.

FIG. 3 is a circuit diagram showing the sense amplifier of FIG.

FIG. 4 is a circuit diagram for explaining an operation example of the present embodiment.

FIG. 5 is a diagram for explaining an operation example during writing and erasing according to the present embodiment.

FIG. 6 is a cross-sectional view of a memory cell in a conventional flash memory.

FIG. 7 is a circuit diagram showing a cell matrix configuration of a conventional flash memory.

FIG. 8 is a diagram for explaining an operation example of conventional writing and erasing.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 threshold voltage measuring means 2 differential voltage calculating means 3 sense amplifier 4 writing means 5 erasing means 6 judging section 7 control section 8 counter 9 DAC 10 charge pump CT cell transistor DM dummy cell NM1 to NM N channel MOS transistor PM1 to PM P channel MOS transistor CG Control gate FG Floating gate D Drain S Source PS Substrate C Memory cell WL _x Word line BL _x Bit line SL _x Select line

Claims (5)

[Claims] 1. A plurality of cell transistors for storing and holding predetermined data, a writing means for writing to any cell transistor of the plurality of cell transistors at a predetermined writing voltage, and the writing means. Threshold voltage measuring means for measuring the threshold voltage of a predetermined cell transistor to be written by, and the threshold voltage value measured by the threshold voltage measuring means,
A difference voltage calculation means for calculating a difference voltage value with respect to an appropriate voltage value required for writing set in advance; and the writing means, wherein the voltage value calculated by the difference voltage calculation means is a write voltage. A non-volatile semiconductor memory device comprising: 2. A plurality of cell transistors for storing and holding predetermined data, an erasing means for erasing an arbitrary cell transistor among the plurality of cell transistors at a predetermined erasing voltage, and an erasing target by the erasing means. A threshold voltage measuring means for measuring a threshold voltage of a predetermined cell transistor, and a threshold voltage value measured by the threshold voltage measuring means,
A difference voltage calculating means for calculating a difference voltage value with respect to an appropriate voltage value required for preset erasing, wherein the erasing means uses the voltage value calculated by the difference voltage calculating means as an erase voltage. And a nonvolatile semiconductor memory device. 3. The non-volatile according to claim 1, wherein the threshold voltage measuring means measures the threshold voltage of the cell transistor after writing or erasing the cell transistor a predetermined number of times. Semiconductor memory device. 4. The differential voltage calculation means comprises a high voltage regulator, and the output voltage of the high voltage regulator is changed based on the difference voltage value which is the calculation result of the differential voltage calculation means. Claim 1, 2, or 3
The nonvolatile semiconductor memory device described. 5. The threshold voltage measuring means includes a differential sense amplifier that operates based on a threshold voltage of a cell transistor to be written or erased and a threshold voltage of a dummy cell paired with the cell transistor. By sequentially scanning the gate voltage of the dummy cell,
5. The non-volatile semiconductor memory device according to claim 1, wherein the threshold voltage of the cell transistor is measured.