JP2809921B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly, for example, to an EEPROM (Electric
The present invention relates to a data rewritable nonvolatile semiconductor memory device suitable for use in fields such as ally erasable programmable read only memory (RAM). In recent years, with the spread of information processing devices such as computers and word processors, for example, EEPROMs, FL
Many non-volatile semiconductor storage devices represented by a non-volatile semiconductor memory such as an flash EEPROM (hereinafter simply referred to as a flash memory) have been developed.

This is a non-volatile memory that can be programmed by a general user and can be rewritten by electrically erasing predetermined data written in advance. However, there is an appropriate voltage value for writing and erasing, and excessive writing and erasing cause device deterioration.
Therefore, it is necessary to perform appropriate writing and erasing.

[0003]

2. Description of the Related Art Conventionally, for example, an EPROM or an EEPROM is known as a semiconductor memory device which is a nonvolatile memory which can be rewritten by erasing predetermined data which has been previously written. However, EPROM
Has the advantage that the cell size is small, but has the disadvantage that data erasure is troublesome because ultraviolet light is used for data erasure, and the data erasure is easy because EEPROM can electrically erase data. However, it has a disadvantage that it is difficult to increase the capacity because of the large cell size as compared with the EPROM.

Therefore, a semiconductor memory device called a NOR type or NAND type flash memory, which has the advantages of these memories, has been developed. FIG. 6 is a sectional view of a typical cell of the flash memory. In the figure,
CG is a control gate, FG is a floating gate, D is an N ⁺ type drain, S is an N ⁺ type source, PS
Is a P-type substrate.

FIG. 7 is a circuit diagram showing a cell matrix configuration of the flash memory shown in FIG. In the figure, C is the memory cell, WL _x denotes a word line, BL _x bit line, SL _x
Indicates a select line. (However, _x indicates _i , _j , _a , _m , _n in the figure) Next, the operation will be described.

First, when writing data to the memory cell C, a high potential voltage V _PP is applied to the control gate CG and the drain D, and electrons are injected into the floating gate FG by avalanche injection near the drain D, so that the memory cell C is written. Cell C is cut off. If you want to delete,
The high potential voltage VPP is applied to the source S while the drain D is floated, and electrons are removed from the floating gate FG, thereby erasing the written data.

The potential levels of the control gate CG, drain D, source S, and substrate PS in the above-described operating state are set to values as shown in Table 1.

[0008]

[Table 1]

[0009]

However, in such a conventional semiconductor memory device, avalanche injection near the drain D is performed by applying a high potential voltage V _PP to the control gate CG and the drain D. In this configuration, data is written by injecting electrons into the floating gate FG, and the written data is erased by extracting electrons from the floating gate FG. Therefore, the following problems arise. Was.

That is, in a NOR flash memory, F
In the case of performing −N channeling erasing, if excessive erasing is performed on a cell transistor, a non-selected memory cell causes a leakage current to flow to cause conduction, and there is a problem that reading of a written cell becomes impossible. Also, NAN
When performing FN channeling writing to a D-type flash memory, if excessive writing is performed, non-conductivity of a non-selected memory cell occurs, so that reading of a cell without writing becomes impossible, and a tunnel oxide film is formed. There has been a problem that the reliability is reduced due to the deterioration, and further, the number of times of writing and erasing is reduced, so that writing and erasing cannot be performed finally.

Therefore, in order to avoid these problems, as shown in FIG. 8, the sense amplifier is provided with a threshold different from that for normal reading and writing at the time of verifying to estimate the threshold voltage of the cell transistor at the time of verifying. Several methods have been considered to make the threshold voltage uniform by performing additional writing / erasing little by little. In this case,
Since additional writing / erasing is performed little by little, a large number of additional writing / erasing operations are required, and a new problem has arisen in that it takes a long time for writing / erasing.

[Purpose] Accordingly, it is an object of the present invention to provide a nonvolatile semiconductor memory device which performs proper programming / erasing with a small number of programming / erasing operations.

[0013]

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention is characterized in that a plurality of cell transistors for storing and holding predetermined data and a predetermined cell to be written are provided. Cell transistor threshold voltage
Threshold voltage measuring means for measuring pressure, and the threshold voltage measuring means
Threshold voltage value measured by
Differential voltage to calculate the differential voltage value from the appropriate
Voltage calculating means, and any one of the plurality of cell transistors.
For the cell transistor, the differential voltage calculating means
Writing means for writing with the voltage value calculated by
The differential voltage calculation means includes a high voltage regulator.
A difference voltage value which is a calculation result of the difference voltage calculation means.
Changing the output voltage of the high-voltage regulator based on
The threshold voltage measuring means includes a cell transistor to be written.
The gate voltage of the dummy cell paired with the transistor changes sequentially
The threshold voltage of the cell transistor.
And then write to the cell transistor.
It is configured as follows.

According to the second aspect of the present invention, a plurality of cell transistors for storing and holding predetermined data, and a cell transistor to be erased are provided.
Threshold voltage measurement to measure the threshold voltage of a fixed cell transistor
Determining means, and a threshold value measured by the threshold voltage measuring means.
Between the voltage value and the proper voltage value required for preset erase.
A differential voltage calculating means for calculating a differential voltage value;
For any of the cell transistors
The voltage value calculated by the differential voltage calculation means.
Erasing means for erasing, wherein said differential voltage calculating means
Comprises a high voltage regulator, and said differential voltage calculating means
The high voltage regulation is performed based on the differential voltage
Changing the output voltage of the threshold voltage,
Dummy cell paired with the cell transistor to be erased
By sequentially changing the gate voltage of the
The threshold voltage of the transistor is measured and then the cell transistor is
The configuration is such that erasure is performed on the master.

[0015]

[0016]

[0017]

According to the present invention, the voltage value calculated by the differential voltage calculating means is determined by the write voltage / write voltage in the writing means / erasing means.
Since the erasing voltage is used, proper writing / erasing can be performed once without performing additional writing / erasing little by little. That is, appropriate writing / erasing is performed with a small number of writing / erasing times.

Further, the threshold voltage of the cell transistor is measured after a predetermined number of write / erase operations on the target cell transistor, so that variations between the elements are absorbed, and the accurate threshold voltage is measured. At the same time, the threshold voltage of the target cell transistor is easily measured by performing measurement using a differential sense amplifier.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. 1 to 5 are views showing one embodiment of a nonvolatile semiconductor memory device according to the present invention, and FIG. 1 is a view showing a main part configuration of the present embodiment. First, the configuration will be described with reference to FIG.

The nonvolatile semiconductor memory device of this embodiment is roughly divided into a cell transistor CT, a threshold voltage measuring means 1,
It comprises a differential voltage calculating means 2, a sense amplifier 3, a writing means 4, and an erasing means 5. In the figure, WL is a word line, and DM is a dummy cell. Threshold voltage measuring means 1
Is composed of a determination unit 6, a control unit 7, a counter 8, and a DAC 9, and is controlled by a control signal from the control unit 7 with respect to a dummy cell DM located on the opposite side of a cell transistor CT (hereinafter, referred to as a target cell) to be measured. , 4-bit output a,
A counter 8 having b, c, and d outputs sequentially incremented data via a DAC 9, and a counter when the target cell and the dummy cell DM are balanced by the determination unit 6 based on an output signal from the sense amplifier 3. The outputs a, b, c, and d of No. 8 are used as threshold voltage values of the target cell.

FIG. 2 is a circuit diagram showing the differential voltage calculating means. The differential voltage calculating means 2 includes a charge pump 10, a diode D1, a resistor R1, N-channel MOS transistors NM1 to NM9, and a P-channel MOS transistor PM1.
To PM6. Note that an N-channel MOS
The transistors NM5, NM8, NM9 are depletion type MOS transistors.

The differential voltage calculating means 2 has a predetermined high potential voltage value set in advance in the circuit itself, receives the 4-bit outputs a, b, c, and d from the counter 8 as inputs and outputs a difference voltage from the high potential voltage value. Outputs the value. FIG. 3 is a circuit diagram showing a sense amplifier. The sense amplifier 3 includes N-channel MOS transistors NM11 to NM11 as shown in FIG.
NM14, P-channel MOS transistors PM11, P
This is a differential sense amplifier composed of M12. The N-channel MOS transistors NM11 and NM12
Is a high withstand voltage type MOS transistor.

FIG. 4 is a circuit diagram for explaining an operation example of this embodiment. As shown in FIG. 4, the writing means 4 and the erasing means 5 include high voltage switches S1 and S2, and AND gates AND1 and AND2, respectively. Next, the operation will be described. First, the control unit 7 sets the counter 8 to “0”.
000 "is sequentially incremented and input to the DAC 9.

In the DAC 9, the input 4-bit digital value is converted into an analog value, and writing of a voltage level corresponding to the 4-bit data input from the counter 8 is performed on the dummy cell DM which is a pair of the target cell. Done. Then, the threshold voltage of the target cell and the dummy cell DM is compared by the sense amplifier 3, and the magnitude of the threshold voltage of the target cell and the dummy cell DM is determined by the determination unit 6 based on the comparison result from the sense amplifier 3.

More specifically, the output values a, b, c, d of the counter 3 at the time when the output from the sense amplifier 3 is inverted.
Is recognized as the threshold voltage of the target cell, and the 4-bit data (abcd) from the counter 8 is output to the difference voltage calculation means 2. In the differential voltage calculation means 2, a high potential voltage level required for writing / erasing is set in the circuit itself, and the 4-bit data a, b, c, d is calculated from the high potential voltage level.
Is output to the writing means 4 and the erasing means 5.

As described above, the writing means 4 and the erasing means 5 control the control gate C according to the operation state.
By setting each potential level of G, drain D, source S, and substrate PS to a value as shown in Table 1, writing / erasing is performed with a predetermined write voltage / erase voltage. FIG. 5 is a diagram for explaining an operation example at the time of writing and erasing of the present embodiment. In this example, after writing / erasing a low potential level twice with respect to the dummy cell DM,
The threshold voltage of the target cell is measured, and then writing / erasing at an appropriate voltage level is performed.

That is, in the present embodiment, the writing / erasing of the low potential level is performed twice first to prevent the deterioration of the measurement accuracy due to the variation between the elements and the loss of the charge. Can be measured. As described above, in the present embodiment, the voltage value calculated by the differential voltage calculation means is set as the write voltage / erase voltage in the write means / erase means, so that additional writing / erasing can be performed little by little. Appropriate writing / erasing can be performed once.

Therefore, appropriate writing / erasing can be performed with a small number of writing / erasing times. In addition,
In the above embodiment, the writing / erasing is completed in the third writing / erasing for the purpose of preventing the measurement error due to the variation between the elements and the missing charge, but the number of times is arbitrary, and once. Needless to say, the writing / erasing may be performed.

Regarding the number of bits of the counter when measuring the threshold voltage of the target cell, regardless of the above embodiment,
You can set it freely. In this case, by increasing the number of bits, the measurement accuracy can be further increased.

[0030]

According to the present invention, the voltage value calculated by the differential voltage calculation means is used as the write voltage / erase voltage in the write means / erase means. Proper writing / erasing can be performed in a single operation. Therefore, appropriate writing / erasing can be performed with a small number of writing / erasing times.

Further, the threshold voltage of the cell transistor is measured after the target cell transistor is written / erased a predetermined number of times, thereby absorbing variations between the elements and accurately measuring the threshold voltage. The threshold voltage of the target cell transistor can be easily measured by performing measurement using a differential sense amplifier.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a main part of the present embodiment.

FIG. 2 is a circuit diagram showing a differential voltage calculating means of FIG.

FIG. 3 is a circuit diagram showing the sense amplifier of FIG. 1;

FIG. 4 is a circuit diagram for explaining an operation example of the present embodiment.

FIG. 5 is a diagram for explaining an operation example at the time of writing and erasing according to the embodiment;

FIG. 6 is a cross-sectional view of a memory cell in a conventional flash memory.

FIG. 7 is a circuit diagram showing a cell matrix configuration of a conventional flash memory.

FIG. 8 is a diagram for explaining a conventional operation example at the time of writing and erasing.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Threshold voltage measuring means 2 Difference voltage calculating means 3 Sense amplifier 4 Writing means 5 Erasing means 6 Judgment part 7 Control part 8 Counter 9 DAC 10 Charge pump CT Cell transistor DM Dummy cell NM1-NM N-channel MOS transistor PM1-PM P-channel MOS transistor CG Control gate FG Floating gate D Drain S Source PS Substrate C Memory cell WL _x Word line BL _x Bit line SL _x Select line

Claims (2)

(57) [Claims] A threshold voltage of a plurality of cell transistors storing and retaining predetermined data and a threshold voltage of a predetermined cell transistor to be written are measured.
Threshold voltage measuring means to determine, a threshold voltage value measured by the threshold voltage measuring means ,
Differential voltage from the appropriate voltage value required for preset programming
A differential voltage calculating means for calculating a value, and an arbitrary cell transistor among the plurality of cell transistors.
Data calculated by the differential voltage calculation means.
Writing means for writing with a voltage value , wherein the differential voltage calculating means includes a high voltage regulator,
Based on the difference voltage value that is the result of the calculation by the difference voltage calculation means.
Then, the output voltage of the high voltage regulator is changed, and the threshold voltage measuring means
The gate voltage of the dummy cell paired with the transistor changes sequentially
The threshold voltage of the cell transistor.
And then write to the cell transistor.
Cormorant It nonvolatile semiconductor memory device according to claim. 2. The method according to claim 1, wherein a plurality of cell transistors storing and retaining predetermined data and a threshold voltage of the predetermined cell transistor to be erased are measured.
Threshold voltage measuring means to determine, a threshold voltage value measured by the threshold voltage measuring means ,
Difference voltage value from proper voltage value required for preset erase
Differential voltage calculating means for calculating an arbitrary cell transistor among the plurality of cell transistors.
Data calculated by the differential voltage calculation means.
Comprising an erasing means for erasing a voltage value, wherein the differential voltage calculating means includes a high voltage regulator,
Based on the difference voltage value that is the result of the calculation by the difference voltage calculation means.
Then, the output voltage of the high-voltage regulator is changed, and the threshold voltage measuring means changes the cell transistor to be erased.
The gate voltage of the dummy cell paired with the
Measuring the threshold voltage of the cell transistor
And erasing the cell transistor thereafter .