JPH11126490A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enlarge the potential difference between a reference potential supplied to a sense amplifier and a bit line and to improve the reading margin, by performing the readout of data dividing to plural times and by optimally setting the current supply power of a load transistor to a memory cell in correspondence to each readout. SOLUTION: In the memory cell, the gate is connected to the word line WL, the drain is connected to the row line BL; and the bit line load transistor 5 charges the row line BL. The sense amplifier section compares the reference potential and the potential of the row line BL to detect the data stored in the memory cell and the current supplying capacity of the transistor 5 is set at the first value to read the data. In response to this result, it is decided whether the current supply power of the transistor 5 is set at the second value larger than the first value or at the third value smaller than the first value to read the data out from the memory cell. By this, data for two bits is stably read out against voltage variation and noise.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory, and more particularly to a nonvolatile semiconductor memory in which one memory cell stores data of a plurality of bits.

[0002]

2. Description of the Related Art A nonvolatile semiconductor memory in which two bits of data are stored in one nonvolatile memory cell is disclosed in Japanese Patent Laid-Open No. 59-121 proposed by the present inventors.
No. 696.

In this conventional memory, a sense amplifier section as shown in FIG. 10 is used, and a level relationship between potentials as shown in FIG. 11 is used. As shown in FIG. 10, three sense amplifiers 1, 2, and 3 and reference potentials 1, 2, and 3 are provided.
The bit line potential read from the memory cell to the bit line is compared with a reference potential by a sense amplifier to detect stored data. That is, the sense amplifiers 1, 2, and 3, to which the reference potentials 1, 2, and 3 are input, respectively, compare the bit line potential with the reference potentials 1, 2, and 3, and determine where the bit line potential is located with respect to the reference potential. 2 bits of data are read depending on whether the data is read.

In this case, as shown in Tables 1 and 2 below, if the bit line potential is lower than the reference potentials 1, 2, and 3, the outputs 1, 2, which are the outputs of the sense amplifiers 1, 2, and 3, respectively. , 3 are both '0', which are detected by, for example, a logic circuit (not shown) and D1 = '0' and D2 = '0' are output as storage data of the memory cells.

[0005]

[Table 1]

[0006]

[Table 2]

Similarly, if the bit line potential is a potential between reference potentials 1 and 2, output 1 is "1" and outputs 2, 3
Are both '0', which are detected by the logic circuit, and D1 = '0' and D2 =
'1' is output.

The combination of the two bits of data is 4
These four types are stored by changing the injection amount of electrons into the floating gate of the nonvolatile memory cell to four types and setting the threshold voltage of the memory cell to four types Vth1 to Vth4 corresponding to the injection amount. ing. That is, if the bit line potential is lower than the smallest reference potential 1 among the reference potentials,
Two bits of data of '00' are stored (the state where the threshold voltage is lowest = Vth1), and if the bit line potential is higher than the highest reference potential 3 among the reference potentials, the data of '11' is stored. (The state with the highest threshold voltage = Vth4), if the bit line potential is between the reference potential 1 and the reference potential 2, '0
1 'is stored (threshold with the third highest threshold voltage =
Vth2), if the bit line potential is between the reference potential 2 and the reference potential 3, the data of '10' is stored (the state where the threshold voltage is the second highest = Vth3).

Here, a sectional structure of the nonvolatile memory cell will be described. FIG. 14A shows a memory cell having no offset gate portion, and FIG. 14B shows a memory cell having an offset gate in which a part of a channel is controlled by a control gate.

At the time of erasing the data of these memory cells, the control gate is set to 0 V, and a high voltage is applied to the drain or the source in the memory cell of FIG. In a memory cell, a high voltage is applied to a drain to emit electrons from a floating gate.

At this time, in the memory cell of the type shown in FIG. 14A, the threshold voltage of the memory cell must be kept from becoming negative, so that the control becomes complicated. Since the memory cell has an offset gate, the threshold voltage of the transistor portion having the channel region controlled by the floating gate may be a negative value, which has an advantage that the control at the time of erasing is simplified.

However, the size of the memory cell is as shown in FIG.
The memory cell of the type (a) has an advantage that it can be smaller than the memory cell of the type of FIG. Next, general writing and erasing (writing of a kind of data) of data to the nonvolatile memory cell as described above will be described.

At the time of writing data, predetermined voltages are respectively applied to the drain and the control gate of the memory cell, the source is set to 0 V, a current flows through the memory cell, and electrons are injected into the floating gate. When writing data, the data is read from the memory cell after the writing (verify reading), and the writing and reading are repeated until the output result from the sense amplifiers 1, 2, and 3 matches the data to be written. Sometimes I stop writing. The coincidence may be determined by reading the data externally and judging externally, or the coincidence may be determined inside the memory chip. ) To detect after.

Before data writing, data erasing is performed. At the time of this data erasing, the control gate of the memory cell is set to 0 V, a high voltage is applied to the drain or source, and electrons are transferred from the floating gate to the drain or source. Release. The state erased in this way corresponds to the state where the data of Vth1, which is the lowest threshold voltage in Table 2, that is, '00' is stored. When erasing data, verify reading is performed after erasing, whether the bit line potential is lower than reference potential 1 is detected by a sense amplifier, and erasing and verify reading are repeatedly performed. When a predetermined threshold voltage is reached, erasing is performed. To end.

Next, a data read operation in the above-described conventional nonvolatile memory will be described with reference to FIGS. FIG. 13 shows the memory cell MC and the load transistor LT connected to the memory cell MC for the sake of simplicity.

Actually, the memory cells MC are arranged in a matrix, and a transistor for selecting a column and a drain voltage of the memory cell are set to a predetermined value between the memory cell MC and the load transistor LT. Bias circuit and the like are connected.

FIG. 12 schematically shows the current flowing through the memory cell and the current flowing through the load transistor to some extent. The voltage (output voltage) VOUT at the connection point between the memory cell and the load transistor in FIG. The vertical axis represents the current flowing through the load transistor and the memory cell, the solid line represents the current flowing through the memory cell when the memory cell is selected, and the dashed line represents the current flowing through the load transistor.

Although the current of the memory cell is shown for each of the threshold voltages Vth1 to Vth3 of the memory cell, when the threshold voltage of the memory cell is Vth4, no current flows even if the memory cell is selected.

The intersection of each solid line and the dashed line indicates VOUT for each of the threshold voltages Vth1 to Vth3 of the memory cell. When the threshold voltage is Vth4, the memory cell is off, and VOUT becomes the power supply voltage VC. .

However, as shown in FIG. 11, the bit line potential is classified into four types, and each threshold voltage Vth1 of the memory cell is determined.
Since the reference potentials 1 to 3 are set between the bit line potentials 1 to 4 corresponding to Vth4 to Vth4, the bit line potential becomes 2 when data of one bit is stored in one conventional memory cell. The difference between the bit line potential and the reference potential is smaller than in the case where the types are distinguished from each other, so that there is a problem that the read margin is reduced and the margin for noise such as power supply fluctuation is small.

[0021]

As described above, the conventional nonvolatile semiconductor memory has a reduced read margin,
There is a problem that a margin is small even for noise such as power supply fluctuation. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a nonvolatile semiconductor memory which can increase a potential difference between a bit line potential and a reference potential and can increase a read margin as compared with the related art. And

[0022]

A nonvolatile semiconductor memory according to the present invention comprises a row line, a column line, a memory cell having a gate connected to the row line, and a drain connected to the column line; A load transistor connected to a line for charging the column line, and comparing a reference potential and a potential of the column line when reading data from the memory cell to detect data stored in the memory cell. The sense amplifier unit sets the current supply capability of the load transistor to the first current supply capability, reads data from the memory cell, and sets the current supply capability of the load transistor to the first current supply according to the read result. Determining whether to set a second current supply capacity larger than the current supply capacity or to set a third current supply capacity smaller than the first current supply capacity;
Data reading means for setting the load transistor to the second or third current supply capability and reading data from the memory cell.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a part of the nonvolatile semiconductor memory according to the first embodiment of the present invention. The memory shown in FIG. 1 has, for example, a memory cell array in which memory cells of the type described above with reference to FIG. 14A are arranged in a matrix.

In FIG. 1, 1 is a memory cell arranged in a matrix, WL is a word line (row line), BL is a bit line (column line), SL is a source line, 2 is a row decoder,
Is a column decoder, 4 is a column selection transistor, 5 is a bit line load transistor, 6 is a bit line potential clamp transistor for setting the drain voltage of the memory cell to a predetermined value, and 7 is a bias potential at the gate of the bit line potential clamp transistor. Is applied to the bias circuit.

The memory cell 1 has a drain, a source,
It has a floating gate and a control gate, and stores a plurality of bits (two bits in this example) of data by varying the amount of charge stored in the floating gate. The drain is connected to the bit line BL, the source is connected to the source line SL, and the control gate is connected to the word line.

Reference numeral 8 denotes data writing to the memory cell 1, verify reading for checking the state of charge accumulation in the floating gate after the writing, and writing when it is determined that desired data has been written by the verify reading. Is completed, and when it is determined that the desired data has not been written by the verify reading, a program means for controlling the writing and the verify reading to be repeated until it is determined that the desired data has been written. A sequence control circuit is used.

FIG. 2 shows a voltage (output voltage) VOUT at a connection point between the memory cell and the load transistor in FIG. 1, a current flowing through the memory cell when the memory cell is selected (solid line), and a current flowing through the load transistor. FIG. 3 is a characteristic diagram schematically showing a relationship with a dash-dot line to some extent.

Hereinafter, an outline of a data read operation in the first embodiment of the nonvolatile semiconductor memory of the present invention will be described with reference to FIG. 2 and Table 2. In the present invention, the data of the upper bit D1 is first read out of the data of two bits (D1, D2) shown in Table 2. That is, the reference potential 2 is compared with the bit line potential, and the sense amplifier detects whether the threshold voltage of the memory cell is lower than Vth2 or higher than Vth3. If the threshold voltage of the memory cell is equal to or lower than Vth2, the data of D1 is "0", and if the threshold voltage is equal to or higher than Vth3, the data of D1 is "1".

As described above, first, whether the threshold voltage of the memory cell is equal to or lower than Vth2 or equal to or higher than Vth3 is detected. B at the intersection of the memory cell current and the current 1 of the load transistor, and the threshold voltage is Vth3
Is determined so as to increase the potential difference between the memory cell current and the point B 'at the intersection of the load transistor current 1 and the difference between the reference potential and the bit line potential can be increased. Can be increased.

In the present invention, after the data is read as described above, the read data is latched. When the read data is '0', the threshold voltage of the memory cell is either Vth1 or Vth2. Therefore, the current supply capability of the load transistor is set large, and the threshold voltage shown in FIG. Since the potential difference between the point A at the intersection of the memory cell current of Vth1 and the current 2 of the load transistor and the point A 'at the intersection of the memory cell current of Vth2 and the current 2 of the load transistor is increased. At this time, the read margin can be increased as compared with the conventional case. In this case, the read data may be latched, but there is no particular need to latch if the load transistor is kept on.

When the data read using the reference potential 2 is "1" as described above, the threshold voltage of the memory cell is either Vth3 or Vth4. Is set to be small, the point C of the intersection of the memory cell current having the threshold voltage Vth3 and the current 3 of the load transistor shown in FIG. 2 and the memory cell current having the threshold voltage Vth4 and the current 3 of the load transistor are set. Intersection,
That is, since the potential difference from the point C 'which is the power supply voltage is increased, the read margin can be increased as compared with the related art.

As described above, according to the present invention, the data stored in the memory cell is read out in two steps, and the performance of the load transistor at that time can be changed to optimize the data in accordance with the threshold voltage of the memory cell. It has the advantage that it can be made larger.

<First Embodiment> The sense amplifier section in the first embodiment uses three sense amplifiers 1, 2, 3 and three reference potentials 1, 2, 3 as shown in FIG. ing. Also, as shown in FIG. 3, the load transistors 5 in FIG.
(First to third) load transistors L1, L2, L3
Is used.

FIG. 3 shows a memory cell 1 according to the first embodiment.
And load transistors L1, L2,
L3 is taken out and shown. Actually, as shown in FIG. 1, the memory cells 1 are arranged in a matrix, and a transistor 4 for selecting a column and the like are connected between the memory cell 1 and the load transistors.

Then, the first load transistor L1
Is connected to the ground potential, the control signal R1 is applied to the gate of the second load transistor L2, and the third
The control signal R2 is applied to the gate of the load transistor L3.

FIG. 4 shows an example of the control signals R1 and R2 used in the circuit of FIG. Next, a read operation of the first embodiment will be described. At the time of the first data read from the memory cell 1, the signal R1 is set to "0" and the signal R1 is set to "0".
2 to “1”, the second load transistor L2 is turned on, and the third load transistor L3 is turned off. Therefore, the first load transistor L1 and the second load transistor L2 serve as load transistors for the memory cell 1.

If the data read in the first reading is "0", the signal R2 is set to "0" and the third load transistor L3 is turned on (that is, the load transistor for the memory cell is set to 3). Load transistors L
1, L2, and L3), thereby increasing the current supply capability of the load transistor and performing the second reading.

If the data read in the first reading is "1", the signal R1 is set to "1", and the second load transistor L2 and the third load transistor L3
Is turned off (that is, only the first load transistor L1 is used as the load transistor for the memory cell), thereby reducing the current supply capability of the load transistor and performing the second reading.

As can be seen from FIG. 2, the first to third reference potentials can be made the same depending on the setting of the load transistor, so that only one reference potential is required. <Second Embodiment> In the second embodiment, as in the first embodiment,
As shown in FIG. 3, three load transistors L1, L2, and L3 are used as the load transistors 5 in FIG.

As shown in FIG. 5, the sense amplifier section in the second embodiment includes two sense amplifiers A and B (5
1, 52), three reference potentials 1, 2, 3; two latch circuits 1, 2 (53, 54); and one switch circuit 55.

The sense amplifier B reads the bit line potential by comparing it with the reference potential 2. The latch circuit 1 latches data read by the sense amplifier B. The switch circuit 55 selects the reference potential 1 or the reference potential 3 according to the logic level of the latch data of the latch circuit 1.

The sense amplifier A reads the bit line potential by comparing it with the reference potential 1 or the reference potential 3 selected by the switch circuit 55. The latch circuit 2 latches the data read by the sense amplifier A.

Next, the outline of the read operation of the second embodiment will be described. At the time of the first reading, data is read by comparing the reference potential 2 with the bit line potential using the sense amplifier B, and the read data is latched in the latch circuit 1. The switch circuit 55 is switched based on the read data and the corresponding reference potential 1 or reference potential 3 is supplied to the sense amplifier A to perform the second read and latch the read data in the latch circuit 2.

In this way, since the number of sense amplifiers can be reduced to two, there is an advantage that the area occupied by the sense amplifier can be reduced and the current consumption in the sense amplifier can be reduced.

FIG. 6 shows an example of the specific circuit configuration of FIG. Each of the sense amplifiers A and B has a pair of NMOs whose corresponding bit line potential and reference potential are input to the gate.
It has a differential voltage comparison circuit composed of an S transistor and a PMOS current mirror circuit connected as a load for these NMOS transistors.

The sense amplifier B compares an output obtained by comparing a bit line potential with a reference potential 2 by a voltage comparison circuit to an inverter circuit I.
1 to the latch circuit 1. This latch circuit 1
Latches an input by a latch signal 1 and latches the latched data through a first NAND circuit N2 via an inverter circuit I2.
A1 is one of the inputs. This first NAND circuit NA1
Receives a signal SW1 as the other input and outputs a signal R2.

The latch data of the latch circuit 1 becomes one input of the second NAND circuit NA2. This second
, The signal SW1 is input as the other input, and the output is one input of the third NAND circuit NA3. The third NAND circuit NA3 receives the signal ATD1 as the other input via the inverter circuit I3, and outputs the signal R1.

On the other hand, the reference potential 1 is a first potential consisting of a PMOS transistor Tr1 and an NMOS transistor Tr2.
, And the reference potential 3 is a PMOS.
Transistor Tr3 and NMOS transistor Tr4
Is input to one end of a second switch circuit composed of The first switch circuit and the second switch circuit are turned on / off complementarily by the signal R2 and a signal obtained by inverting the signal R2 by the inverter circuit I7. In this example, the first switch circuit is turned on when the signal R2 is at the “0” level, and the second switch circuit is turned on when the signal R2 is at the “1” level.
Is turned on.

The sense amplifier A receives the reference potential 1 or 3 from the other end of the first switch circuit or the second switch circuit, and compares the bit line potential with the reference potential 1 or 3 by a voltage comparison circuit. The output is input to the latch circuit 2 via the inverter circuit I4. This latch circuit 2
The input is latched by the latch signal 2.

FIG. 7 is a signal waveform diagram shown for explaining the operation of the circuit of FIG. Next, the read operation of the second embodiment will be described in detail with reference to FIGS. In FIG. 7, a signal ATD is a pulse signal generated by detecting a change in an address input signal. In response to the change of signal ATD, signal ATD1 changes from '1' level to '0' level.

Further, since the signal SW1 is set to the "0" level, as can be seen from the circuit of FIG.
When TD1 goes to the "0" level, the signal R1 is set to "0", the signal R2 is set to "1", the second load transistor L2 in FIG. 3 is turned on, and the two load transistors L1 in FIG. , L2 serve as load transistors for memory cell 1.

After a predetermined period from the change of the signal ATD1, the latch signal 1 becomes "1" level, and the data detected by the sense amplifier B using the reference potential 2 is stored in the latch circuit 1.

After a predetermined period, the latch signal 1 changes to "0", and the data stored in the latch circuit 1 is held until the latch signal 1 becomes the "1" level next time. After this,
The signal SW1 changes to “1”.

If the data from the memory cell latched by the latch circuit 1 is "0", the signals R1 and R2 both become "0", and the second load transistor L2 and the third
Are turned on, and in this state, data is read again from the memory cell.

At this time, since the signal R2 is "0", the first switch circuit is turned on, the reference potential 1 is supplied to the sense amplifier A, and the data is read out by the sense amplifier A using the reference potential 1. .

In a state where the data that has passed a predetermined period after the signal SW1 changes, the latch signal 2
Becomes '1', and the data read by the sense amplifier A is latched by the latch circuit 2.

Then, the latch circuit 1 and the latch circuit 2
Is read out as data stored in the memory cell. When the data from the memory cell latched by the latch circuit 1 is "1", both the signal R1 and the signal R2 become "1" as shown by the broken line in FIG. 7, and the second load transistor L2 and The third load transistor L3 is turned off, and in this state, data is read from the memory cell again.

At this time, since the signal R2 is "1", the second switch circuit is turned on, the reference potential 3 is supplied to the sense amplifier A, and data is read out by the sense amplifier A using the reference potential 3. .

In a state where the data that has passed for a predetermined period after the signal SW1 changes, the latch signal 2
Becomes '1', and the data read by the sense amplifier A is latched by the latch circuit 2.

After that, the latch signal 2 changes to “0”, and the data is held in the latch circuit 2. Thereafter, the signal SW1
Becomes "0", the signal ATD1, the signal R1, and the signal R2 all change to "1", and then wait for the address to change and data to be read from a new memory cell.

<Third Embodiment> In the third embodiment, as in the first embodiment, as shown in FIG. 3, three load transistors L1, L2, L are used as the load transistors in FIG.
3 is used.

As shown in FIG. 8, the sense amplifier section in the third embodiment includes three sense amplifiers 1, 2, 3
(81, 82, 83) and three reference potentials 1, 2, 3
, Two latch circuits 84 and 85, and one switch circuit 86.

The sense amplifier 1 compares the bit line potential with the reference potential 1 for reading, and the sense amplifier 2 compares the bit line potential with the reference potential 2 for reading. Latch circuit 84
Latches the data read by the sense amplifier 2. The sense amplifier 3 compares the bit line potential with the reference potential 3 for reading. The switch circuit 86 includes a latch circuit 84
The output of the sense amplifier 1 or the output of the sense amplifier 3 is selected based on the data of (1), and the latch circuit 85 latches the data selected by the switch circuit 86.

Next, the read operation of the third embodiment will be described. The signal R1 is set to "0" and the second load transistor L
2 is turned on, and the two load transistors L1,
With L2 acting as a load transistor for the memory cell 1, data is read out by the sense amplifier 2 by comparing the bit line potential with the reference potential 2.

Thereafter, at the time of the second read, the signal R1 and the signal R2 are both set to "0" or both set to "1" based on the data of the latch circuit read by the sense amplifier 2. Setting is performed, and the sense amplifiers 1 and 3 read the data by comparing the reference potential 1 and the reference potential 3 with the bit line potential, respectively.

Then, based on the data of the latch circuit 84 read by the sense amplifier 2, the switch circuit 86 is switched to transfer the data from the sense amplifier 1 to the latch circuit 85 or the data from the sense amplifier 3. Is transferred to the latch circuit 85, and the correct data is latched.

<Fourth Embodiment> In the fourth embodiment, as in the first embodiment, the load transistor 5 in FIG.
As shown in FIG. 3, three load transistors L1, L2,
L3 is used.

Further, as shown in FIG. 9, the sense amplifier section in the fourth embodiment includes one sense amplifier 91 and three sense amplifiers.
Reference potentials 1, 2, 3 and one switch circuit 92
And two latch circuits 1 and 2 (93, 94).

The switch circuit 92 selects the reference potential 1 or 2 or 3. The sense amplifier 91 reads the bit line potential by comparing it with a reference potential selected by the switch circuit 92. The latch circuits 1 and 2 latch the output of the sense amplifier 91.

Next, the read operation of the fourth embodiment will be described. At the time of the first reading, as in the third embodiment, the signal R1 is set to "0" to turn on the second load transistor L2, and the switching of the switch circuit 92 is controlled so that the reference potential 2 is sensed. The data is read out by comparing the bit line potential with the reference potential 2. Then, the read data is stored in the latch circuit 1.
Latch.

At the time of the second reading, the signal R1 and the signal R2 are both set to "0" or both to "1" based on the data of the latch circuit 1 read by the sense amplifier 91. In response to this, either the reference potential 1 or the reference potential 3 is selected by the switch circuit 92 and supplied to the sense amplifier 91. The data is read out by comparing with the line potential, and the read out data is latched in the latch circuit 2.

Outputs from the above-described latch circuits 1 and 2 become 2-bit data stored in the memory cells. In such a configuration, since only one sense amplifier is used, current consumption can be reduced, and the number of elements used is reduced, so that the area occupied by the elements is reduced, and the chip size can be reduced. There is.

In each of the above embodiments, as the first embodiment of the present invention, a case where 2-bit data is stored in one memory cell and data read is divided into two times has been described. However, the configuration and the read control procedure of each of the above embodiments can also be applied to a case where two or more bits of data are stored in one memory cell and data read is divided into two or more times.

For example, when eight data of three bits are assigned to eight threshold values Vth1 to Vth8 of one memory cell and stored, a plurality of sense amplifiers and, for example, seven reference potentials 1 to 7 are used. . The threshold is from Vth1 to Vth
8 in the order of “Vth1 <Vth2 <Vth3 <
It is assumed that Vth4 <Vth5 <Vth6 <Vth7 <Vth8. D1 and D are stored data of 3 bits.
2, D3, Vth1 is D1 = '0', D2 =
“0”, D3 = “0”, and Vth2 is D1 =
'0', D2 = '0', D3 = '1', Vth3 is D1
= '0', D2 = '1', D3 = '0', and Vth4 is D
1 = '0', D2 = '1', D3 = '1', Vth5 is D1 = '1', D2 = '0', D3 = '0', Vth6
Are D1 = '1', D2 = '0', D3 = '1', and Vth
7 is D1 = '1', D2 = '1', D3 = '0', and V
th8 corresponds to D1 = '1', D2 = '1', and D3 = '1', respectively.

The potentials of the reference potentials 1 to 7 also increase in order from 1 to 7, and the magnitude relationship between the potentials is expressed as “reference potential 1 <
Reference potential 2 <reference potential 3 <reference potential 4 <reference potential 5 <reference potential 6 <reference potential 7 ". The reference potential 1 is
The bit line potential when the threshold value of the memory cell is Vth1 is set between the bit line potential when the threshold value of the memory cell is Vth2, and the reference potential 2 is the bit line potential when the threshold value of the memory cell is Vth2. The threshold value of the memory cell is set between the bit line potential when the threshold value is Vth3, and the reference potential 3 is the bit line potential when the threshold value of the memory cell is Vth3 and the threshold value of the memory cell is V
It is set between the bit line potential at th4 and the reference potential 4
Is set between the bit line potential when the threshold value of the memory cell is Vth4 and the bit line potential when the threshold value of the memory cell is Vth5, and the reference potential 5 is the bit line potential when the threshold value of the memory cell is Vth5. The reference potential 6 is set between the potential and the bit line potential when the threshold value of the memory cell is Vth6, and the reference potential 6 is the bit line potential when the threshold value of the memory cell is Vth6 and the bit line potential when the threshold value of the memory cell is Vth7. The reference potential 7 is set between the bit line potential when the memory cell threshold is Vth7 and the bit line potential when the memory cell threshold is Vth8.

Then, at the time of the first data reading from the memory cell, the data is detected using the reference potential 4. If the data read in the first read is “0”, D1 is “0”, and then the current supply capability of the load transistor is increased, and the second read is performed using the reference potential 2. If the data read in the first read is “1”, D1 is “1”, and then the current supply capability of the load transistor is reduced, and the reference potential 6
The second reading is performed using.

If the first read data is "0" and the second read data is "0", D2 is "0", and then the current supply of the load transistor is performed. The capability is further increased, and the third reading is performed using the reference potential 1. At this time, if the read data is '0', D3 is '0', and if the read data is '1', D3 is '1'. If the data read in the second reading is “1”, D2 is “1”. Then, the current supply capability of the load transistor is reduced, and the third reading is performed using the reference potential 3.

At this time, if the read data is '0', D3 is '0', and if the read data is '1', D3 is '1'. If the first read data is "1" and the second read data is "0", D2 is "0", and the current supply capability of the load transistor is increased. A third reading is performed using the reference potential 5. At this time, if the read data is '0', D3 is '0', and if the read data is '1', D3 is '1'.
If the first read data is “1” and the second read data is “1”, D2 is “1”.
Then, the third reading is performed using the reference potential 7 by reducing the current supply capability of the load transistor. At this time, if the read data is '0', D3 is '0', and if the read data is '1', D3 is '1'.

That is, according to the present invention, there is provided a memory cell for storing at least two bits of data in which a row line, a column line, a gate is connected to the row line, and a drain is connected to the column line, A load transistor connected to a line for charging the column line, and comparing a reference potential and a potential of the column line when reading data from the memory cell to detect data stored in the memory cell. In a non-volatile semiconductor memory including a sense amplifier unit and data reading means for reading data from the memory cell at least twice, the reading data reading means may supply current of a predetermined current to the load transistor. Data is read from the memory cell by setting the capacity, and the current supply capacity of the load transistor is adjusted in accordance with the read result. Is characterized in that data is read out from the memory cell by reduction.

[0080]

As described above, according to the nonvolatile semiconductor memory of the present invention, when at least two bits of data are stored in one memory cell, data reading is divided into at least two times. Therefore, the current supply capability of the load transistor to the memory cell can be optimized in response to each read operation, so that the potential difference between the reference potential supplied to the sense amplifier and the bit line can be controlled to be large, and the read margin can be increased. Has the advantage that it can be

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a part of a nonvolatile semiconductor memory according to a first embodiment of the present invention.

2 shows a voltage (output voltage) VOUT at a connection point between a memory cell and a load transistor in FIG. 1, a current flowing through the memory cell when the memory cell is selected (solid line), and a current flowing through the load transistor (dashed line). FIG. 3 is a characteristic diagram showing a relationship with the graph.

FIG. 3 is a circuit diagram showing a memory cell and a load transistor according to a first embodiment of the semiconductor memory of FIG. 1;

FIG. 4 is a timing waveform chart showing an example of control signals R1 and R2 used in the circuit of FIG.

FIG. 5 is a block diagram showing a sense amplifier unit of a read system according to a second embodiment of the semiconductor memory of FIG. 1;

FIG. 6 is a circuit diagram showing a specific example of FIG. 5;

FIG. 7 is a signal waveform diagram shown for explaining the operation of the circuit of FIG. 6;

FIG. 8 is a block diagram showing a sense amplifier unit of a reading system according to a third embodiment of the semiconductor memory of FIG. 1;

FIG. 9 is a block diagram showing a sense amplifier unit of a read system according to a fourth embodiment of the semiconductor memory of FIG. 1;

FIG. 10 is a block diagram showing a sense amplifier unit in a conventional memory.

FIG. 11 is a view for explaining a level relationship between reference potentials 1, 2, and 3 and bit line potentials 1, 2, 3, and 4 in FIG. 10;

FIG. 12 is a circuit diagram showing a memory cell and a load transistor in a conventional memory.

FIG. 13 shows a voltage (output voltage) VOUT at a connection point between the memory cell and the load transistor in FIG. 12, a current flowing through the memory cell when the memory cell is selected (solid line), and a current flowing through the load transistor (dashed line). FIG. 3 is a characteristic diagram showing a relationship with the graph.

FIG. 14 is a diagram showing a cross-sectional structure of two different examples of a nonvolatile memory cell used in a nonvolatile semiconductor memory in which data of a plurality of bits is stored in one nonvolatile memory cell.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... memory cell, 2 ... row decoder, 3 ... column decoder, 4 ... column selection transistor, 5 ... bit line load transistor, 6 ... bit line potential clamp transistor, 7 ... bias circuit, 8 ... sequence control circuit.

Claims (11)

[Claims] A memory cell having a row line, a column line, a gate connected to the row line, and a drain connected to the column line; and a memory cell connected to the column line for charging the column line. A load transistor, a sense amplifier for detecting a data stored in the memory cell by comparing a reference potential and a potential of the column line when data is read from the memory cell, and a current supply capability of the load transistor. Setting the first current supply capability to read data from the memory cell;
In response to the read result, the current supply capability of the load transistor is set to a second current supply capability larger than the first current supply capability.
Or a third current supply capability smaller than the first current supply capability, and setting the load transistor to the second or third current supply capability.
Data reading means for reading data from the memory cells by setting the current supply capability of the nonvolatile semiconductor memory. 2. The non-volatile semiconductor memory according to claim 1, wherein said memory cell has a drain, a source, a floating gate, and a control gate connected to said row line, and stores a charge stored in said floating gate. A non-volatile semiconductor memory storing a plurality of bits of data by varying the amount. 3. The nonvolatile semiconductor memory according to claim 1, further comprising a first latch circuit and a second latch circuit, wherein the load transistor has a current supply capability of the first current supply capability. When the data is read from the memory cell by setting the output to the first latch circuit, the output of the sense amplifier unit is latched by the first latch circuit, and the current supply capability of the load transistor is set to the second or A non-volatile semiconductor memory, wherein the control is performed such that an output of the sense amplifier unit is latched by the second latch circuit when data is read from the memory cell with the third current supply capability set. 4. The nonvolatile semiconductor memory according to claim 1, wherein said sense amplifier reads data from said memory cell in a state where a current supply capability of said load transistor is set to said first current supply capability. The data stored in the memory cell is detected by comparing the first reference potential with the potential of the column line, and the current supply capability of the load transistor is set to the second current supply capability. When data is read from the memory cell in a state where the data is read out, the data stored in the memory cell is detected by comparing a second reference potential with the potential of the column line, and the current supply capability of the load transistor is reduced. When data is read from the memory cell in the state set to the third current supply capacity, a third reference potential is compared with the potential of the column line to write the data to the memory cell. Nonvolatile semiconductor memory characterized in that it is controlled so as to detect the data. 5. The nonvolatile semiconductor memory according to claim 4, wherein said sense amplifier unit has a first sense amplifier, a second sense amplifier, and a third sense amplifier, and said current supply capability of said load transistor. When data is read from the memory cell in a state where is set to the first current supply capability, the first sense amplifier compares the first reference potential with the potential of the column line to read the data. When data stored in a memory cell is detected, and when data is read from the memory cell in a state where the current supply capability of the load transistor is set to the second current supply capability, the data is read by the second sense amplifier. The data stored in the memory cell is detected by comparing the second reference potential with the potential of the column line, and the current supply capability of the load transistor is changed to a third current. When data is read from the memory cell with the power supply capacity set, the data is stored in the memory cell by comparing the third reference potential with the potential of the column line by the third sense amplifier. A non-volatile semiconductor memory controlled to detect data. 6. The non-volatile semiconductor memory according to claim 5, wherein said sense amplifier section switches-selects an output of said second sense amplifier and an output of said third sense amplifier to output data. A non-volatile semiconductor memory characterized in that: 7. The nonvolatile semiconductor memory according to claim 4, wherein said sense amplifier has a first sense amplifier and a second sense amplifier, and said load transistor has a current supply capability of said first current. When data is read from the memory cell in a state where the supply capacity is set, the data is stored in the memory cell by comparing the first reference potential with the potential of the column line by the first sense amplifier. When data is detected and data is read from the memory cell in a state where the current supply capability of the load transistor is set to the second current supply capability, the second reference potential is applied by the second sense amplifier. And the potential of the column line is compared to detect data stored in the memory cell. The current supply capability of the load transistor is set to a third current supply capability. When data is read from the memory cell in the state, the data stored in the memory cell is detected by comparing the third reference potential with the potential of the column line by the second sense amplifier. A nonvolatile semiconductor memory characterized by being controlled. 8. The non-volatile semiconductor memory according to claim 7, wherein the second sense amplifier is switched and supplied between the second reference potential and the third reference potential. Nonvolatile semiconductor memory. 9. The non-volatile semiconductor memory according to claim 4, wherein said sense amplifier section includes said first reference potential and said second reference potential.
A non-volatile semiconductor memory, wherein the reference potential and the third reference potential are switched and supplied. 10. The nonvolatile semiconductor memory according to claim 9, further comprising a first latch circuit and a second latch circuit, wherein the first reference potential and the potential of the column line are detected by comparison. The first data is stored in the first latch circuit, and the second data is stored in the second latch circuit.
A nonvolatile semiconductor memory controlled to store data detected by comparing the reference potential or the third reference potential with the potential of the column line in the second latch circuit. 11. A memory cell having a row line, a column line, a gate connected to the row line, and a drain connected to the column line, and a memory cell connected to the column line for charging the column line. A load transistor, a sense amplifier for detecting a data stored in the memory cell by comparing a reference potential and a potential of the column line when data is read from the memory cell, and a current supply capability of the load transistor. Reading data from the memory cell by setting a predetermined current supply capacity,
A non-volatile semiconductor memory, comprising: data read means for reading data from the memory cell by changing a current supply capability of the load transistor in accordance with the read result.